Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Gowin\Workspace\pwm_servo\impl\gwsynthesis\test_pwm_servo.vg
Physical Constraints File	C:\Gowin\Workspace\pwm_servo\src\test_pwm_servo.cst
Timing Constraint File	---
GOWIN version	V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 15:04:21 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 2.375V 85C
Hold Delay Model	Fast 2.625V 0C
Numbers of Paths Analyzed	135
Numbers of Endpoints Analyzed	50
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	1

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk_ibuf/I
clk10khz	Base	10.000	100.000	0.000	5.000			toggle_1/out_s0/Q

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	137.185(MHz)	5	TOP
2	clk10khz	100.000(MHz)	216.717(MHz)	3	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
clk10khz	Setup	0.000	0
clk10khz	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.711	compare_0_s2/Q	compare_4_s16/CE	clk:[R]	clk:[R]	10.000	0.000	7.246
2	2.751	compare_0_s2/Q	compare_1_s2/D	clk:[R]	clk:[R]	10.000	0.000	6.849
3	3.071	compare_0_s2/Q	compare_0_s2/CE	clk:[R]	clk:[R]	10.000	0.000	6.886
4	3.071	compare_0_s2/Q	compare_1_s2/CE	clk:[R]	clk:[R]	10.000	0.000	6.886
5	3.071	compare_0_s2/Q	compare_2_s2/CE	clk:[R]	clk:[R]	10.000	0.000	6.886
6	3.071	compare_0_s2/Q	compare_3_s2/CE	clk:[R]	clk:[R]	10.000	0.000	6.886
7	3.478	compare_0_s2/Q	compare_2_s2/D	clk:[R]	clk:[R]	10.000	0.000	6.122
8	4.306	clkdiv_1/count_1_s0/Q	toggle_1/out_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.294
9	4.512	clkdiv_1/count_1_s0/Q	clkdiv_1/count_1_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.445
10	4.512	clkdiv_1/count_1_s0/Q	clkdiv_1/count_2_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.445
11	4.512	clkdiv_1/count_1_s0/Q	clkdiv_1/count_3_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.445
12	4.512	clkdiv_1/count_1_s0/Q	clkdiv_1/count_4_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.445
13	4.512	clkdiv_1/count_1_s0/Q	clkdiv_1/count_5_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.445
14	4.589	clkdiv_1/count_1_s0/Q	clkdiv_1/count_0_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.368
15	4.589	clkdiv_1/count_1_s0/Q	clkdiv_1/count_6_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.368
16	4.589	clkdiv_1/count_1_s0/Q	clkdiv_1/count_7_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.368
17	4.589	clkdiv_1/count_1_s0/Q	clkdiv_1/count_8_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.368
18	4.589	clkdiv_1/count_1_s0/Q	clkdiv_1/count_9_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	5.368
19	4.975	clkdiv_1/count_1_s0/Q	toggle_1/prev_in_s1/RESET	clk:[R]	clk:[R]	10.000	0.000	4.982
20	5.145	compare_4_s16/Q	compare_0_s2/D	clk:[R]	clk:[R]	10.000	0.000	4.455
21	5.210	compare_4_s16/Q	compare_3_s2/D	clk:[R]	clk:[R]	10.000	0.000	4.390
22	5.386	pwm16_1/count_4_s0/Q	pwm16_1/count_6_s0/RESET	clk10khz:[R]	clk10khz:[R]	10.000	0.000	4.571
23	5.386	pwm16_1/count_4_s0/Q	pwm16_1/count_7_s0/RESET	clk10khz:[R]	clk10khz:[R]	10.000	0.000	4.571
24	6.112	pwm16_1/count_4_s0/Q	pwm16_1/count_1_s0/RESET	clk10khz:[R]	clk10khz:[R]	10.000	0.000	3.845
25	6.112	pwm16_1/count_4_s0/Q	pwm16_1/count_2_s0/RESET	clk10khz:[R]	clk10khz:[R]	10.000	0.000	3.845

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.122	toggle_1/n9_s0/I2	toggle_1/out_s0/D	clk10khz:[R]	clk:[R]	0.000	-1.651	0.558
2	0.710	pwm16_1/count_0_s0/Q	pwm16_1/count_0_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.710
3	0.730	pwm16_1/count_2_s0/Q	pwm16_1/count_2_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.730
4	0.730	pwm16_1/count_6_s0/Q	pwm16_1/count_6_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.730
5	0.730	clkdiv_1/count_2_s0/Q	clkdiv_1/count_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
6	0.730	clkdiv_1/count_6_s0/Q	clkdiv_1/count_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
7	0.730	clkdiv_1/count_8_s0/Q	clkdiv_1/count_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
8	0.853	clkdiv_1/count_1_s0/Q	clkdiv_1/count_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.853
9	0.853	pwm16_1/count_1_s0/Q	pwm16_1/count_1_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.853
10	0.893	clkdiv_1/count_0_s0/Q	clkdiv_1/count_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.893
11	0.962	clkdiv_1/count_5_s0/Q	clkdiv_1/count_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.962
12	0.962	clkdiv_1/count_7_s0/Q	clkdiv_1/count_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.962
13	0.962	pwm16_1/count_5_s0/Q	pwm16_1/count_5_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.962
14	0.965	clkdiv_1/count_9_s0/Q	clkdiv_1/count_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
15	0.966	pwm16_1/count_3_s0/Q	pwm16_1/count_3_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.966
16	0.966	pwm16_1/count_4_s0/Q	pwm16_1/count_4_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.966
17	0.970	clkdiv_1/count_3_s0/Q	clkdiv_1/count_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.970
18	0.970	clkdiv_1/count_4_s0/Q	clkdiv_1/count_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.970
19	0.971	pwm16_1/count_7_s0/Q	pwm16_1/count_7_s0/D	clk10khz:[R]	clk10khz:[R]	0.000	0.000	0.971
20	1.210	clkdiv_1/count_8_s0/Q	toggle_1/prev_in_s1/RESET	clk:[R]	clk:[R]	0.000	0.000	1.225
21	1.223	clkdiv_1/count_9_s0/Q	toggle_1/prev_in_s1/D	clk:[R]	clk:[R]	0.000	0.000	1.223
22	1.387	pwm16_1/count_6_s0/Q	pwm16_1/count_0_s0/RESET	clk10khz:[R]	clk10khz:[R]	0.000	0.000	1.402
23	1.489	clkdiv_1/count_8_s0/Q	clkdiv_1/count_0_s0/RESET	clk:[R]	clk:[R]	0.000	0.000	1.504
24	1.489	clkdiv_1/count_8_s0/Q	clkdiv_1/count_6_s0/RESET	clk:[R]	clk:[R]	0.000	0.000	1.504
25	1.489	clkdiv_1/count_8_s0/Q	clkdiv_1/count_7_s0/RESET	clk:[R]	clk:[R]	0.000	0.000	1.504

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.911	4.161	1.250	Low Pulse Width	clk	compare_4_s16
2	2.911	4.161	1.250	Low Pulse Width	clk	compare_2_s2
3	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_8_s0
4	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_0_s0
5	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_1_s0
6	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_9_s0
7	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_2_s0
8	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_3_s0
9	2.911	4.161	1.250	Low Pulse Width	clk	compare_3_s2
10	2.911	4.161	1.250	Low Pulse Width	clk	compare_0_s2

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.711
Data Arrival Time	9.376
Data Required Time	12.087
From	compare_0_s2
To	compare_4_s16
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
7.868	0.011	tNET	FF	1	R11C15[2][A]	compare_4_s18/I2
8.670	0.802	tINS	FR	5	R11C15[2][A]	compare_4_s18/F
9.376	0.706	tNET	RR	1	R11C13[1][A]	compare_4_s16/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C13[1][A]	compare_4_s16/CLK
12.087	-0.043	tSu		1	R11C13[1][A]	compare_4_s16

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.626, 50.041%; route: 3.162, 43.634%; tC2Q: 0.458, 6.325%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack	2.751
Data Arrival Time	8.979
Data Required Time	11.730
From	compare_0_s2
To	compare_1_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
8.979	1.122	tNET	FF	1	R11C15[0][B]	compare_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[0][B]	compare_1_s2/CLK
11.730	-0.400	tSu		1	R11C15[0][B]	compare_1_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.824, 41.233%; route: 3.567, 52.075%; tC2Q: 0.458, 6.692%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack	3.071
Data Arrival Time	9.016
Data Required Time	12.087
From	compare_0_s2
To	compare_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
7.868	0.011	tNET	FF	1	R11C15[2][A]	compare_4_s18/I2
8.670	0.802	tINS	FR	5	R11C15[2][A]	compare_4_s18/F
9.016	0.346	tNET	RR	1	R11C15[0][A]	compare_0_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
12.087	-0.043	tSu		1	R11C15[0][A]	compare_0_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.626, 52.658%; route: 2.802, 40.685%; tC2Q: 0.458, 6.656%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack	3.071
Data Arrival Time	9.016
Data Required Time	12.087
From	compare_0_s2
To	compare_1_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
7.868	0.011	tNET	FF	1	R11C15[2][A]	compare_4_s18/I2
8.670	0.802	tINS	FR	5	R11C15[2][A]	compare_4_s18/F
9.016	0.346	tNET	RR	1	R11C15[0][B]	compare_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[0][B]	compare_1_s2/CLK
12.087	-0.043	tSu		1	R11C15[0][B]	compare_1_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.626, 52.658%; route: 2.802, 40.685%; tC2Q: 0.458, 6.656%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack	3.071
Data Arrival Time	9.016
Data Required Time	12.087
From	compare_0_s2
To	compare_2_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
7.868	0.011	tNET	FF	1	R11C15[2][A]	compare_4_s18/I2
8.670	0.802	tINS	FR	5	R11C15[2][A]	compare_4_s18/F
9.016	0.346	tNET	RR	1	R11C15[1][A]	compare_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[1][A]	compare_2_s2/CLK
12.087	-0.043	tSu		1	R11C15[1][A]	compare_2_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.626, 52.658%; route: 2.802, 40.685%; tC2Q: 0.458, 6.656%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack	3.071
Data Arrival Time	9.016
Data Required Time	12.087
From	compare_0_s2
To	compare_3_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[3][B]	n246_s34/I0
6.411	1.099	tINS	FF	1	R11C17[3][B]	n246_s34/F
7.232	0.821	tNET	FF	1	R11C15[3][A]	n246_s32/I3
7.858	0.626	tINS	FF	2	R11C15[3][A]	n246_s32/F
7.868	0.011	tNET	FF	1	R11C15[2][A]	compare_4_s18/I2
8.670	0.802	tINS	FR	5	R11C15[2][A]	compare_4_s18/F
9.016	0.346	tNET	RR	1	R11C15[1][B]	compare_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[1][B]	compare_3_s2/CLK
12.087	-0.043	tSu		1	R11C15[1][B]	compare_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.626, 52.658%; route: 2.802, 40.685%; tC2Q: 0.458, 6.656%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack	3.478
Data Arrival Time	8.252
Data Required Time	11.730
From	compare_0_s2
To	compare_2_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
2.588	0.458	tC2Q	RF	6	R11C15[0][A]	compare_0_s2/Q
3.404	0.815	tNET	FF	1	R11C14[3][A]	n245_s37/I0
4.503	1.099	tINS	FF	2	R11C14[3][A]	n245_s37/F
5.312	0.809	tNET	FF	1	R11C17[2][A]	n245_s34/I0
6.411	1.099	tINS	FF	2	R11C17[2][A]	n245_s34/F
7.220	0.810	tNET	FF	1	R11C15[1][A]	n245_s32/I1
8.252	1.032	tINS	FF	1	R11C15[1][A]	n245_s32/F
8.252	0.000	tNET	FF	1	R11C15[1][A]	compare_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[1][A]	compare_2_s2/CLK
11.730	-0.400	tSu		1	R11C15[1][A]	compare_2_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.230, 52.758%; route: 2.434, 39.756%; tC2Q: 0.458, 7.486%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack	4.306
Data Arrival Time	7.424
Data Required Time	11.730
From	clkdiv_1/count_1_s0
To	toggle_1/out_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.782	1.032	tINS	FF	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
6.798	0.016	tNET	FF	1	R9C10[2][A]	toggle_1/n9_s0/I0
7.424	0.626	tINS	FF	1	R9C10[2][A]	toggle_1/n9_s0/F
7.424	0.000	tNET	FF	1	R9C10[2][A]	toggle_1/out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C10[2][A]	toggle_1/out_s0/CLK
11.730	-0.400	tSu		1	R9C10[2][A]	toggle_1/out_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.512, 66.340%; route: 1.324, 25.002%; tC2Q: 0.458, 8.658%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack	4.512
Data Arrival Time	7.575
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.575	0.800	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
12.087	-0.043	tSu		1	R11C9[0][B]	clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 52.893%; route: 2.107, 38.690%; tC2Q: 0.458, 8.418%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack	4.512
Data Arrival Time	7.575
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.575	0.800	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
12.087	-0.043	tSu		1	R11C9[1][A]	clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 52.893%; route: 2.107, 38.690%; tC2Q: 0.458, 8.418%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path11

Path Summary:

Slack	4.512
Data Arrival Time	7.575
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.575	0.800	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
12.087	-0.043	tSu		1	R11C9[1][B]	clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 52.893%; route: 2.107, 38.690%; tC2Q: 0.458, 8.418%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path12

Path Summary:

Slack	4.512
Data Arrival Time	7.575
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.575	0.800	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
12.087	-0.043	tSu		1	R11C9[2][A]	clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 52.893%; route: 2.107, 38.690%; tC2Q: 0.458, 8.418%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack	4.512
Data Arrival Time	7.575
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.575	0.800	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
12.087	-0.043	tSu		1	R11C9[2][B]	clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 52.893%; route: 2.107, 38.690%; tC2Q: 0.458, 8.418%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path14

Path Summary:

Slack	4.589
Data Arrival Time	7.498
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.498	0.722	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/CLK
12.087	-0.043	tSu		1	R11C10[2][A]	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 53.652%; route: 2.030, 37.809%; tC2Q: 0.458, 8.538%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack	4.589
Data Arrival Time	7.498
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.498	0.722	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
12.087	-0.043	tSu		1	R11C10[0][A]	clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 53.652%; route: 2.030, 37.809%; tC2Q: 0.458, 8.538%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path16

Path Summary:

Slack	4.589
Data Arrival Time	7.498
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.498	0.722	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
12.087	-0.043	tSu		1	R11C10[0][B]	clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 53.652%; route: 2.030, 37.809%; tC2Q: 0.458, 8.538%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack	4.589
Data Arrival Time	7.498
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.498	0.722	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
12.087	-0.043	tSu		1	R11C10[1][A]	clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 53.652%; route: 2.030, 37.809%; tC2Q: 0.458, 8.538%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack	4.589
Data Arrival Time	7.498
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I2
6.776	1.026	tINS	FR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
7.498	0.722	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
12.087	-0.043	tSu		1	R11C10[1][B]	clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 53.652%; route: 2.030, 37.809%; tC2Q: 0.458, 8.538%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack	4.975
Data Arrival Time	7.112
Data Required Time	12.087
From	clkdiv_1/count_1_s0
To	toggle_1/prev_in_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RF	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
3.081	0.493	tNET	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/I2
4.113	1.032	tINS	FF	1	R11C9[3][A]	clkdiv_1/tc20khz_s1/F
4.119	0.005	tNET	FF	1	R11C9[3][B]	clkdiv_1/tc20khz_s0/I0
4.941	0.822	tINS	FF	2	R11C9[3][B]	clkdiv_1/tc20khz_s0/F
5.750	0.809	tNET	FF	1	R9C10[0][B]	toggle_1/prev_in_s3/I2
6.776	1.026	tINS	FR	1	R9C10[0][B]	toggle_1/prev_in_s3/F
7.112	0.336	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/CLK
12.087	-0.043	tSu		1	R9C10[1][A]	toggle_1/prev_in_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.880, 57.811%; route: 1.643, 32.989%; tC2Q: 0.458, 9.200%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path20

Path Summary:

Slack	5.145
Data Arrival Time	6.585
Data Required Time	11.730
From	compare_4_s16
To	compare_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C13[1][A]	compare_4_s16/CLK
2.588	0.458	tC2Q	RF	6	R11C13[1][A]	compare_4_s16/Q
3.420	0.832	tNET	FF	1	R11C16[0][A]	compare_4_s24/I3
4.222	0.802	tINS	FR	2	R11C16[0][A]	compare_4_s24/F
4.643	0.421	tNET	RR	1	R11C17[3][A]	compare_4_s22/I0
5.269	0.626	tINS	RF	2	R11C17[3][A]	compare_4_s22/F
5.763	0.495	tNET	FF	1	R11C15[0][A]	n247_s32/I0
6.585	0.822	tINS	FF	1	R11C15[0][A]	n247_s32/F
6.585	0.000	tNET	FF	1	R11C15[0][A]	compare_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[0][A]	compare_0_s2/CLK
11.730	-0.400	tSu		1	R11C15[0][A]	compare_0_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.250, 50.501%; route: 1.747, 39.212%; tC2Q: 0.458, 10.287%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path21

Path Summary:

Slack	5.210
Data Arrival Time	6.520
Data Required Time	11.730
From	compare_4_s16
To	compare_3_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C13[1][A]	compare_4_s16/CLK
2.588	0.458	tC2Q	RF	6	R11C13[1][A]	compare_4_s16/Q
3.416	0.828	tNET	FF	1	R11C15[3][B]	compare_4_s19/I3
4.515	1.099	tINS	FF	1	R11C15[3][B]	compare_4_s19/F
4.521	0.005	tNET	FF	1	R11C15[2][B]	compare_4_s17/I0
5.553	1.032	tINS	FF	2	R11C15[2][B]	compare_4_s17/F
6.520	0.968	tNET	FF	1	R11C15[1][B]	compare_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	17	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[1][B]	compare_3_s2/CLK
11.730	-0.400	tSu		1	R11C15[1][B]	compare_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.131, 48.539%; route: 1.801, 41.021%; tC2Q: 0.458, 10.440%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path22

Path Summary:

Slack	5.386
Data Arrival Time	5.803
Data Required Time	11.189
From	pwm16_1/count_4_s0
To	pwm16_1/count_6_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
1.232	1.232	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
1.690	0.458	tC2Q	RR	3	R11C12[2][A]	pwm16_1/count_4_s0/Q
2.112	0.422	tNET	RR	1	R11C13[1][B]	pwm16_1/tc_s2/I2
3.211	1.099	tINS	RF	1	R11C13[1][B]	pwm16_1/tc_s2/F
3.217	0.005	tNET	FF	1	R11C13[3][B]	pwm16_1/tc_s1/I0
4.278	1.061	tINS	FR	8	R11C13[3][B]	pwm16_1/tc_s1/F
5.803	1.526	tNET	RR	1	R11C13[0][A]	pwm16_1/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk10khz
10.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
11.232	1.232	tNET	RR	1	R11C13[0][A]	pwm16_1/count_6_s0/CLK
11.189	-0.043	tSu		1	R11C13[0][A]	pwm16_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%
Arrival Data Path Delay	cell: 2.160, 47.255%; route: 1.953, 42.718%; tC2Q: 0.458, 10.027%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%

Path23

Path Summary:

Slack	5.386
Data Arrival Time	5.803
Data Required Time	11.189
From	pwm16_1/count_4_s0
To	pwm16_1/count_7_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
1.232	1.232	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
1.690	0.458	tC2Q	RR	3	R11C12[2][A]	pwm16_1/count_4_s0/Q
2.112	0.422	tNET	RR	1	R11C13[1][B]	pwm16_1/tc_s2/I2
3.211	1.099	tINS	RF	1	R11C13[1][B]	pwm16_1/tc_s2/F
3.217	0.005	tNET	FF	1	R11C13[3][B]	pwm16_1/tc_s1/I0
4.278	1.061	tINS	FR	8	R11C13[3][B]	pwm16_1/tc_s1/F
5.803	1.526	tNET	RR	1	R11C13[0][B]	pwm16_1/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk10khz
10.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
11.232	1.232	tNET	RR	1	R11C13[0][B]	pwm16_1/count_7_s0/CLK
11.189	-0.043	tSu		1	R11C13[0][B]	pwm16_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%
Arrival Data Path Delay	cell: 2.160, 47.255%; route: 1.953, 42.718%; tC2Q: 0.458, 10.027%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%

Path24

Path Summary:

Slack	6.112
Data Arrival Time	5.077
Data Required Time	11.189
From	pwm16_1/count_4_s0
To	pwm16_1/count_1_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
1.232	1.232	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
1.690	0.458	tC2Q	RR	3	R11C12[2][A]	pwm16_1/count_4_s0/Q
2.112	0.422	tNET	RR	1	R11C13[1][B]	pwm16_1/tc_s2/I2
3.211	1.099	tINS	RF	1	R11C13[1][B]	pwm16_1/tc_s2/F
3.217	0.005	tNET	FF	1	R11C13[3][B]	pwm16_1/tc_s1/I0
4.278	1.061	tINS	FR	8	R11C13[3][B]	pwm16_1/tc_s1/F
5.077	0.800	tNET	RR	1	R11C12[0][B]	pwm16_1/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk10khz
10.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
11.232	1.232	tNET	RR	1	R11C12[0][B]	pwm16_1/count_1_s0/CLK
11.189	-0.043	tSu		1	R11C12[0][B]	pwm16_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%
Arrival Data Path Delay	cell: 2.160, 56.177%; route: 1.227, 31.903%; tC2Q: 0.458, 11.920%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%

Path25

Path Summary:

Slack	6.112
Data Arrival Time	5.077
Data Required Time	11.189
From	pwm16_1/count_4_s0
To	pwm16_1/count_2_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
1.232	1.232	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
1.690	0.458	tC2Q	RR	3	R11C12[2][A]	pwm16_1/count_4_s0/Q
2.112	0.422	tNET	RR	1	R11C13[1][B]	pwm16_1/tc_s2/I2
3.211	1.099	tINS	RF	1	R11C13[1][B]	pwm16_1/tc_s2/F
3.217	0.005	tNET	FF	1	R11C13[3][B]	pwm16_1/tc_s1/I0
4.278	1.061	tINS	FR	8	R11C13[3][B]	pwm16_1/tc_s1/F
5.077	0.800	tNET	RR	1	R11C12[1][A]	pwm16_1/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk10khz
10.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
11.232	1.232	tNET	RR	1	R11C12[1][A]	pwm16_1/count_2_s0/CLK
11.189	-0.043	tSu		1	R11C12[1][A]	pwm16_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%
Arrival Data Path Delay	cell: 2.160, 56.177%; route: 1.227, 31.903%; tC2Q: 0.458, 11.920%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.232, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.122
Data Arrival Time	0.558
Data Required Time	1.681
From	toggle_1/n9_s0
To	toggle_1/out_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.002	0.002	tNET	RR	1	R9C10[2][A]	toggle_1/n9_s0/I2
0.558	0.556	tINS	RR	1	R9C10[2][A]	toggle_1/n9_s0/F
0.558	0.000	tNET	RR	1	R9C10[2][A]	toggle_1/out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[2][A]	toggle_1/out_s0/CLK
1.681	0.030	tUnc				toggle_1/out_s0
1.681	0.000	tHld		1	R9C10[2][A]	toggle_1/out_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.556, 99.577%; route: 0.000, 0.000%; tC2Q: 0.002, 0.423%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack	0.710
Data Arrival Time	1.587
Data Required Time	0.877
From	pwm16_1/count_0_s0
To	pwm16_1/count_0_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R12C13[0][A]	pwm16_1/count_0_s0/CLK
1.211	0.333	tC2Q	RR	4	R12C13[0][A]	pwm16_1/count_0_s0/Q
1.215	0.005	tNET	RR	1	R12C13[0][A]	pwm16_1/n23_s2/I
1.587	0.372	tINS	RF	1	R12C13[0][A]	pwm16_1/n23_s2/O
1.587	0.000	tNET	FF	1	R12C13[0][A]	pwm16_1/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R12C13[0][A]	pwm16_1/count_0_s0/CLK
0.877	0.000	tHld		1	R12C13[0][A]	pwm16_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path3

Path Summary:

Slack	0.730
Data Arrival Time	1.607
Data Required Time	0.877
From	pwm16_1/count_2_s0
To	pwm16_1/count_2_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[1][A]	pwm16_1/count_2_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C12[1][A]	pwm16_1/count_2_s0/Q
1.213	0.002	tNET	RR	2	R11C12[1][A]	pwm16_1/n21_s/I1
1.607	0.394	tINS	RF	1	R11C12[1][A]	pwm16_1/n21_s/SUM
1.607	0.000	tNET	FF	1	R11C12[1][A]	pwm16_1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[1][A]	pwm16_1/count_2_s0/CLK
0.877	0.000	tHld		1	R11C12[1][A]	pwm16_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path4

Path Summary:

Slack	0.730
Data Arrival Time	1.607
Data Required Time	0.877
From	pwm16_1/count_6_s0
To	pwm16_1/count_6_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C13[0][A]	pwm16_1/count_6_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C13[0][A]	pwm16_1/count_6_s0/Q
1.213	0.002	tNET	RR	2	R11C13[0][A]	pwm16_1/n17_s/I1
1.607	0.394	tINS	RF	1	R11C13[0][A]	pwm16_1/n17_s/SUM
1.607	0.000	tNET	FF	1	R11C13[0][A]	pwm16_1/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C13[0][A]	pwm16_1/count_6_s0/CLK
0.877	0.000	tHld		1	R11C13[0][A]	pwm16_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path5

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_2_s0
To	clkdiv_1/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[1][A]	clkdiv_1/count_2_s0/Q
1.986	0.002	tNET	RR	2	R11C9[1][A]	clkdiv_1/n29_s/I1
2.380	0.394	tINS	RF	1	R11C9[1][A]	clkdiv_1/n29_s/SUM
2.380	0.000	tNET	FF	1	R11C9[1][A]	clkdiv_1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
1.651	0.000	tHld		1	R11C9[1][A]	clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_6_s0
To	clkdiv_1/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C10[0][A]	clkdiv_1/count_6_s0/Q
1.986	0.002	tNET	RR	2	R11C10[0][A]	clkdiv_1/n25_s/I1
2.380	0.394	tINS	RF	1	R11C10[0][A]	clkdiv_1/n25_s/SUM
2.380	0.000	tNET	FF	1	R11C10[0][A]	clkdiv_1/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
1.651	0.000	tHld		1	R11C10[0][A]	clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_8_s0
To	clkdiv_1/count_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][A]	clkdiv_1/count_8_s0/Q
1.986	0.002	tNET	RR	2	R11C10[1][A]	clkdiv_1/n23_s/I1
2.380	0.394	tINS	RF	1	R11C10[1][A]	clkdiv_1/n23_s/SUM
2.380	0.000	tNET	FF	1	R11C10[1][A]	clkdiv_1/count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.651	0.000	tHld		1	R11C10[1][A]	clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack	0.853
Data Arrival Time	2.503
Data Required Time	1.651
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
1.986	0.002	tNET	RR	2	R11C9[0][B]	clkdiv_1/n30_s/I0
2.503	0.517	tINS	RF	1	R11C9[0][B]	clkdiv_1/n30_s/SUM
2.503	0.000	tNET	FF	1	R11C9[0][B]	clkdiv_1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
1.651	0.000	tHld		1	R11C9[0][B]	clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack	0.853
Data Arrival Time	1.730
Data Required Time	0.877
From	pwm16_1/count_1_s0
To	pwm16_1/count_1_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[0][B]	pwm16_1/count_1_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C12[0][B]	pwm16_1/count_1_s0/Q
1.213	0.002	tNET	RR	2	R11C12[0][B]	pwm16_1/n22_s/I0
1.730	0.517	tINS	RF	1	R11C12[0][B]	pwm16_1/n22_s/SUM
1.730	0.000	tNET	FF	1	R11C12[0][B]	pwm16_1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[0][B]	pwm16_1/count_1_s0/CLK
0.877	0.000	tHld		1	R11C12[0][B]	pwm16_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path10

Path Summary:

Slack	0.893
Data Arrival Time	2.544
Data Required Time	1.651
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[2][A]	clkdiv_1/count_0_s0/Q
1.988	0.004	tNET	RR	1	R11C10[2][A]	clkdiv_1/n31_s2/I
2.544	0.556	tINS	RR	1	R11C10[2][A]	clkdiv_1/n31_s2/O
2.544	0.000	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/CLK
1.651	0.000	tHld		1	R11C10[2][A]	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack	0.962
Data Arrival Time	2.613
Data Required Time	1.651
From	clkdiv_1/count_5_s0
To	clkdiv_1/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
1.984	0.333	tC2Q	RF	2	R11C9[2][B]	clkdiv_1/count_5_s0/Q
2.219	0.234	tNET	FF	2	R11C9[2][B]	clkdiv_1/n26_s/I1
2.613	0.394	tINS	FF	1	R11C9[2][B]	clkdiv_1/n26_s/SUM
2.613	0.000	tNET	FF	1	R11C9[2][B]	clkdiv_1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
1.651	0.000	tHld		1	R11C9[2][B]	clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack	0.962
Data Arrival Time	2.613
Data Required Time	1.651
From	clkdiv_1/count_7_s0
To	clkdiv_1/count_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
1.984	0.333	tC2Q	RF	3	R11C10[0][B]	clkdiv_1/count_7_s0/Q
2.219	0.234	tNET	FF	2	R11C10[0][B]	clkdiv_1/n24_s/I1
2.613	0.394	tINS	FF	1	R11C10[0][B]	clkdiv_1/n24_s/SUM
2.613	0.000	tNET	FF	1	R11C10[0][B]	clkdiv_1/count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
1.651	0.000	tHld		1	R11C10[0][B]	clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack	0.962
Data Arrival Time	1.839
Data Required Time	0.877
From	pwm16_1/count_5_s0
To	pwm16_1/count_5_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[2][B]	pwm16_1/count_5_s0/CLK
1.211	0.333	tC2Q	RF	3	R11C12[2][B]	pwm16_1/count_5_s0/Q
1.445	0.234	tNET	FF	2	R11C12[2][B]	pwm16_1/n18_s/I1
1.839	0.394	tINS	FF	1	R11C12[2][B]	pwm16_1/n18_s/SUM
1.839	0.000	tNET	FF	1	R11C12[2][B]	pwm16_1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[2][B]	pwm16_1/count_5_s0/CLK
0.877	0.000	tHld		1	R11C12[2][B]	pwm16_1/count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path14

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_9_s0
To	clkdiv_1/count_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][B]	clkdiv_1/count_9_s0/Q
2.222	0.238	tNET	RR	2	R11C10[1][B]	clkdiv_1/n22_s/I1
2.616	0.394	tINS	RF	1	R11C10[1][B]	clkdiv_1/n22_s/SUM
2.616	0.000	tNET	FF	1	R11C10[1][B]	clkdiv_1/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
1.651	0.000	tHld		1	R11C10[1][B]	clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path15

Path Summary:

Slack	0.966
Data Arrival Time	1.843
Data Required Time	0.877
From	pwm16_1/count_3_s0
To	pwm16_1/count_3_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[1][B]	pwm16_1/count_3_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C12[1][B]	pwm16_1/count_3_s0/Q
1.449	0.239	tNET	RR	2	R11C12[1][B]	pwm16_1/n20_s/I1
1.843	0.394	tINS	RF	1	R11C12[1][B]	pwm16_1/n20_s/SUM
1.843	0.000	tNET	FF	1	R11C12[1][B]	pwm16_1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[1][B]	pwm16_1/count_3_s0/CLK
0.877	0.000	tHld		1	R11C12[1][B]	pwm16_1/count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path16

Path Summary:

Slack	0.966
Data Arrival Time	1.843
Data Required Time	0.877
From	pwm16_1/count_4_s0
To	pwm16_1/count_4_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C12[2][A]	pwm16_1/count_4_s0/Q
1.449	0.239	tNET	RR	2	R11C12[2][A]	pwm16_1/n19_s/I1
1.843	0.394	tINS	RF	1	R11C12[2][A]	pwm16_1/n19_s/SUM
1.843	0.000	tNET	FF	1	R11C12[2][A]	pwm16_1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C12[2][A]	pwm16_1/count_4_s0/CLK
0.877	0.000	tHld		1	R11C12[2][A]	pwm16_1/count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path17

Path Summary:

Slack	0.970
Data Arrival Time	2.621
Data Required Time	1.651
From	clkdiv_1/count_3_s0
To	clkdiv_1/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[1][B]	clkdiv_1/count_3_s0/Q
2.227	0.243	tNET	RR	2	R11C9[1][B]	clkdiv_1/n28_s/I1
2.621	0.394	tINS	RF	1	R11C9[1][B]	clkdiv_1/n28_s/SUM
2.621	0.000	tNET	FF	1	R11C9[1][B]	clkdiv_1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
1.651	0.000	tHld		1	R11C9[1][B]	clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack	0.970
Data Arrival Time	2.621
Data Required Time	1.651
From	clkdiv_1/count_4_s0
To	clkdiv_1/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[2][A]	clkdiv_1/count_4_s0/Q
2.227	0.243	tNET	RR	2	R11C9[2][A]	clkdiv_1/n27_s/I1
2.621	0.394	tINS	RF	1	R11C9[2][A]	clkdiv_1/n27_s/SUM
2.621	0.000	tNET	FF	1	R11C9[2][A]	clkdiv_1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
1.651	0.000	tHld		1	R11C9[2][A]	clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack	0.971
Data Arrival Time	1.849
Data Required Time	0.877
From	pwm16_1/count_7_s0
To	pwm16_1/count_7_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C13[0][B]	pwm16_1/count_7_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C13[0][B]	pwm16_1/count_7_s0/Q
1.455	0.244	tNET	RR	2	R11C13[0][B]	pwm16_1/n16_s/I1
1.849	0.394	tINS	RF	1	R11C13[0][B]	pwm16_1/n16_s/SUM
1.849	0.000	tNET	FF	1	R11C13[0][B]	pwm16_1/count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C13[0][B]	pwm16_1/count_7_s0/CLK
0.877	0.000	tHld		1	R11C13[0][B]	pwm16_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.394, 40.572%; route: 0.244, 25.104%; tC2Q: 0.333, 34.325%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path20

Path Summary:

Slack	1.210
Data Arrival Time	2.876
Data Required Time	1.666
From	clkdiv_1/count_8_s0
To	toggle_1/prev_in_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][A]	clkdiv_1/count_8_s0/Q
2.254	0.270	tNET	RR	1	R9C10[0][B]	toggle_1/prev_in_s3/I1
2.639	0.385	tINS	RR	1	R9C10[0][B]	toggle_1/prev_in_s3/F
2.876	0.237	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/CLK
1.666	0.015	tHld		1	R9C10[1][A]	toggle_1/prev_in_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.385, 31.429%; route: 0.507, 41.360%; tC2Q: 0.333, 27.211%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path21

Path Summary:

Slack	1.223
Data Arrival Time	2.874
Data Required Time	1.651
From	clkdiv_1/count_9_s0
To	toggle_1/prev_in_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][B]	clkdiv_1/count_9_s0/Q
2.874	0.890	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[1][A]	toggle_1/prev_in_s1/CLK
1.651	0.000	tHld		1	R9C10[1][A]	toggle_1/prev_in_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.890, 72.754%; tC2Q: 0.333, 27.246%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path22

Path Summary:

Slack	1.387
Data Arrival Time	2.279
Data Required Time	0.892
From	pwm16_1/count_6_s0
To	pwm16_1/count_0_s0
Launch Clk	clk10khz:[R]
Latch Clk	clk10khz:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R11C13[0][A]	pwm16_1/count_6_s0/CLK
1.211	0.333	tC2Q	RR	3	R11C13[0][A]	pwm16_1/count_6_s0/Q
1.455	0.244	tNET	RR	1	R11C13[3][B]	pwm16_1/tc_s1/I2
2.011	0.556	tINS	RR	8	R11C13[3][B]	pwm16_1/tc_s1/F
2.279	0.269	tNET	RR	1	R12C13[0][A]	pwm16_1/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk10khz
0.000	0.000	tCL	RR	9	R9C10[2][A]	toggle_1/out_s0/Q
0.877	0.877	tNET	RR	1	R12C13[0][A]	pwm16_1/count_0_s0/CLK
0.892	0.015	tHld		1	R12C13[0][A]	pwm16_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay	cell: 0.556, 39.668%; route: 0.512, 36.550%; tC2Q: 0.333, 23.782%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.877, 100.000%

Path23

Path Summary:

Slack	1.489
Data Arrival Time	3.155
Data Required Time	1.666
From	clkdiv_1/count_8_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][A]	clkdiv_1/count_8_s0/Q
2.254	0.270	tNET	RR	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I0
2.639	0.385	tINS	RR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
3.155	0.516	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_0_s0/CLK
1.666	0.015	tHld		1	R11C10[2][A]	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.385, 25.593%; route: 0.786, 52.249%; tC2Q: 0.333, 22.158%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path24

Path Summary:

Slack	1.489
Data Arrival Time	3.155
Data Required Time	1.666
From	clkdiv_1/count_8_s0
To	clkdiv_1/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][A]	clkdiv_1/count_8_s0/Q
2.254	0.270	tNET	RR	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I0
2.639	0.385	tINS	RR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
3.155	0.516	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
1.666	0.015	tHld		1	R11C10[0][A]	clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.385, 25.593%; route: 0.786, 52.249%; tC2Q: 0.333, 22.158%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path25

Path Summary:

Slack	1.489
Data Arrival Time	3.155
Data Required Time	1.666
From	clkdiv_1/count_8_s0
To	clkdiv_1/count_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[1][A]	clkdiv_1/count_8_s0/Q
2.254	0.270	tNET	RR	1	R9C10[0][A]	clkdiv_1/tc20khz_s/I0
2.639	0.385	tINS	RR	11	R9C10[0][A]	clkdiv_1/tc20khz_s/F
3.155	0.516	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	17	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
1.666	0.015	tHld		1	R11C10[0][B]	clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.385, 25.593%; route: 0.786, 52.249%; tC2Q: 0.333, 22.158%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	compare_4_s16

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	compare_4_s16/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	compare_4_s16/CLK

MPW2

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	compare_2_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	compare_2_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	compare_2_s2/CLK

MPW3

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_8_s0/CLK

MPW4

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_0_s0/CLK

MPW5

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_1_s0/CLK

MPW6

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_9_s0/CLK

MPW7

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_2_s0/CLK

MPW8

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_3_s0/CLK

MPW9

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	compare_3_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	compare_3_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	compare_3_s2/CLK

MPW10

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	compare_0_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	compare_0_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	compare_0_s2/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
17	clk_d	2.711	1.505
11	tc20khz	4.306	0.851
9	compare[2]	4.221	0.842
9	clk10khz	5.386	1.491
8	tc	5.386	1.784
6	compare[4]	3.171	0.832
6	compare[1]	3.179	1.304
6	compare[3]	3.380	0.431
6	compare[0]	2.711	0.815
5	compare_3_8	2.711	0.826

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C15	34.72%
R11C13	22.22%
R11C12	20.83%
R12C16	16.67%
R11C10	16.67%
R11C16	15.28%
R12C17	13.89%
R11C9	13.89%
R11C17	12.50%
R11C14	12.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command