Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Gowin\Workspace\rgb_led\src\rgb_test.v C:\Gowin\Workspace\rgb_led\src\pwm.v
GowinSynthesis Constraints File	---
GowinSynthesis Version	GowinSynthesis V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 18:34:44 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	rgb_test
Synthesis Process	Running parser:     CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 156.910MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.910MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 156.910MB     Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 156.910MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.910MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.910MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.910MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.910MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 156.910MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.910MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.910MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.313s, Peak memory usage = 156.910MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 156.910MB Generate output files:     CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.910MB
Total Time and Memory Usage	CPU time = 0h 0m 0.45s, Elapsed time = 0h 0m 0.466s, Peak memory usage = 156.910MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	29
I/O Buf	29
IBUF	9
OBUF	20
Register	14
DFFC	14
LUT	35
LUT2	2
LUT3	15
LUT4	18
INV	8
INV	8

Resource Utilization Summary

Resource	Usage	Utilization
Logic	43(43 LUTs, 0 ALUs) / 4608	1%
Register	14 / 3756	1%
--Register as Latch	0 / 3756	0%
--Register as FF	14 / 3756	1%
BSRAM	0 / 10	0%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
clk	Base	10.000	100.0	0.000	5.000			clk_ibuf/I

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.0(MHz)	168.3(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	4.059
Data Arrival Time	6.886
Data Required Time	10.945
From	pwm_r/count_3_s0
To	pwm_r/count_1_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	14	clk_ibuf/O
1.345	0.363	tNET	RR	1	pwm_r/count_3_s0/CLK
1.803	0.458	tC2Q	RF	5	pwm_r/count_3_s0/Q
2.283	0.480	tNET	FF	1	pwm_r/n39_s3/I1
3.382	1.099	tINS	FF	2	pwm_r/n39_s3/F
3.862	0.480	tNET	FF	1	pwm_r/n39_s2/I0
4.894	1.032	tINS	FF	6	pwm_r/n39_s2/F
5.374	0.480	tNET	FF	1	pwm_r/n38_s1/I0
6.406	1.032	tINS	FF	1	pwm_r/n38_s1/F
6.886	0.480	tNET	FF	1	pwm_r/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	14	clk_ibuf/O
11.345	0.363	tNET	RR	1	pwm_r/count_1_s0/CLK
10.945	-0.400	tSu		1	pwm_r/count_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:

Slack	4.059
Data Arrival Time	6.886
Data Required Time	10.945
From	pwm_r/count_3_s0
To	pwm_r/count_2_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	14	clk_ibuf/O
1.345	0.363	tNET	RR	1	pwm_r/count_3_s0/CLK
1.803	0.458	tC2Q	RF	5	pwm_r/count_3_s0/Q
2.283	0.480	tNET	FF	1	pwm_r/n39_s3/I1
3.382	1.099	tINS	FF	2	pwm_r/n39_s3/F
3.862	0.480	tNET	FF	1	pwm_r/n39_s2/I0
4.894	1.032	tINS	FF	6	pwm_r/n39_s2/F
5.374	0.480	tNET	FF	1	pwm_r/n37_s2/I0
6.406	1.032	tINS	FF	1	pwm_r/n37_s2/F
6.886	0.480	tNET	FF	1	pwm_r/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	14	clk_ibuf/O
11.345	0.363	tNET	RR	1	pwm_r/count_2_s0/CLK
10.945	-0.400	tSu		1	pwm_r/count_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:

Slack	4.059
Data Arrival Time	6.886
Data Required Time	10.945
From	pwm_r/count_3_s0
To	pwm_r/count_4_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	14	clk_ibuf/O
1.345	0.363	tNET	RR	1	pwm_r/count_3_s0/CLK
1.803	0.458	tC2Q	RF	5	pwm_r/count_3_s0/Q
2.283	0.480	tNET	FF	1	pwm_r/n39_s3/I1
3.382	1.099	tINS	FF	2	pwm_r/n39_s3/F
3.862	0.480	tNET	FF	1	pwm_r/n39_s2/I0
4.894	1.032	tINS	FF	6	pwm_r/n39_s2/F
5.374	0.480	tNET	FF	1	pwm_r/n35_s1/I0
6.406	1.032	tINS	FF	1	pwm_r/n35_s1/F
6.886	0.480	tNET	FF	1	pwm_r/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	14	clk_ibuf/O
11.345	0.363	tNET	RR	1	pwm_r/count_4_s0/CLK
10.945	-0.400	tSu		1	pwm_r/count_4_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:

Slack	4.059
Data Arrival Time	6.886
Data Required Time	10.945
From	pwm_r/count_3_s0
To	pwm_r/count_5_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	14	clk_ibuf/O
1.345	0.363	tNET	RR	1	pwm_r/count_3_s0/CLK
1.803	0.458	tC2Q	RF	5	pwm_r/count_3_s0/Q
2.283	0.480	tNET	FF	1	pwm_r/n39_s3/I1
3.382	1.099	tINS	FF	2	pwm_r/n39_s3/F
3.862	0.480	tNET	FF	1	pwm_r/n39_s2/I0
4.894	1.032	tINS	FF	6	pwm_r/n39_s2/F
5.374	0.480	tNET	FF	1	pwm_r/n34_s1/I0
6.406	1.032	tINS	FF	1	pwm_r/n34_s1/F
6.886	0.480	tNET	FF	1	pwm_r/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	14	clk_ibuf/O
11.345	0.363	tNET	RR	1	pwm_r/count_5_s0/CLK
10.945	-0.400	tSu		1	pwm_r/count_5_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:

Slack	4.059
Data Arrival Time	6.886
Data Required Time	10.945
From	pwm_g/count_3_s0
To	pwm_g/count_1_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	14	clk_ibuf/O
1.345	0.363	tNET	RR	1	pwm_g/count_3_s0/CLK
1.803	0.458	tC2Q	RF	5	pwm_g/count_3_s0/Q
2.283	0.480	tNET	FF	1	pwm_g/n39_s3/I1
3.382	1.099	tINS	FF	2	pwm_g/n39_s3/F
3.862	0.480	tNET	FF	1	pwm_g/n39_s2/I0
4.894	1.032	tINS	FF	6	pwm_g/n39_s2/F
5.374	0.480	tNET	FF	1	pwm_g/n38_s1/I0
6.406	1.032	tINS	FF	1	pwm_g/n38_s1/F
6.886	0.480	tNET	FF	1	pwm_g/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	14	clk_ibuf/O
11.345	0.363	tNET	RR	1	pwm_g/count_1_s0/CLK
10.945	-0.400	tSu		1	pwm_g/count_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%