Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Gowin\Workspace\rgb_led\impl\gwsynthesis\rgb_led.vg
Physical Constraints File	C:\Gowin\Workspace\rgb_led\src\rgb_led.cst
Timing Constraint File	---
GOWIN version	V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 18:34:53 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 2.375V 85C
Hold Delay Model	Fast 2.625V 0C
Numbers of Paths Analyzed	61
Numbers of Endpoints Analyzed	48
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	186.593(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.641	pwm_g/count_1_s0/Q	pwm_g/count_5_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.959
2	4.641	pwm_g/count_1_s0/Q	pwm_g/count_6_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.959
3	4.739	pwm_r/count_0_s0/Q	pwm_r/count_5_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.861
4	4.915	pwm_r/count_0_s0/Q	pwm_r/count_6_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.685
5	4.957	pwm_g/count_3_s0/Q	pwm_g/count_2_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.643
6	4.957	pwm_g/count_3_s0/Q	pwm_g/count_4_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.643
7	5.340	pwm_r/count_2_s0/Q	pwm_r/count_3_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.260
8	5.581	pwm_g/count_3_s0/Q	pwm_g/count_1_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.019
9	5.581	pwm_g/count_3_s0/Q	pwm_g/count_3_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.019
10	5.613	pwm_r/count_2_s0/Q	pwm_r/count_1_s0/D	clk:[R]	clk:[R]	10.000	0.000	3.987
11	5.613	pwm_r/count_2_s0/Q	pwm_r/count_2_s0/D	clk:[R]	clk:[R]	10.000	0.000	3.987
12	5.613	pwm_r/count_2_s0/Q	pwm_r/count_4_s0/D	clk:[R]	clk:[R]	10.000	0.000	3.987
13	6.430	pwm_g/count_3_s0/Q	pwm_g/count_0_s0/D	clk:[R]	clk:[R]	10.000	0.000	3.170
14	6.846	pwm_r/count_2_s0/Q	pwm_r/count_0_s0/D	clk:[R]	clk:[R]	10.000	0.000	2.754

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	pwm_r/count_0_s0/Q	pwm_r/count_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
2	0.708	pwm_g/count_1_s0/Q	pwm_g/count_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
3	0.710	pwm_r/count_2_s0/Q	pwm_r/count_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
4	0.710	pwm_g/count_6_s0/Q	pwm_g/count_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
5	0.893	pwm_r/count_5_s0/Q	pwm_r/count_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.893
6	0.943	pwm_r/count_5_s0/Q	pwm_r/count_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.943
7	0.946	pwm_r/count_2_s0/Q	pwm_r/count_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.946
8	0.946	pwm_g/count_6_s0/Q	pwm_g/count_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.946
9	1.060	pwm_r/count_4_s0/Q	pwm_r/count_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.060
10	1.061	pwm_r/count_1_s0/Q	pwm_r/count_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
11	1.061	pwm_g/count_4_s0/Q	pwm_g/count_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
12	1.062	pwm_g/count_2_s0/Q	pwm_g/count_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.062
13	1.062	pwm_g/count_3_s0/Q	pwm_g/count_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.062
14	1.298	pwm_g/count_5_s0/Q	pwm_g/count_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.298

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_6_s0
2	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_4_s0
3	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_0_s0
4	2.911	4.161	1.250	Low Pulse Width	clk	pwm_r/count_0_s0
5	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_1_s0
6	2.911	4.161	1.250	Low Pulse Width	clk	pwm_r/count_1_s0
7	2.911	4.161	1.250	Low Pulse Width	clk	pwm_r/count_2_s0
8	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_5_s0
9	2.911	4.161	1.250	Low Pulse Width	clk	pwm_g/count_2_s0
10	2.911	4.161	1.250	Low Pulse Width	clk	pwm_r/count_3_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.641
Data Arrival Time	7.089
Data Required Time	11.730
From	pwm_g/count_1_s0
To	pwm_g/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][A]	pwm_g/count_1_s0/CLK
2.588	0.458	tC2Q	RF	4	R9C9[1][A]	pwm_g/count_1_s0/Q
3.432	0.843	tNET	FF	1	R9C10[2][A]	pwm_g/n36_s2/I1
4.458	1.026	tINS	FR	3	R9C10[2][A]	pwm_g/n36_s2/F
4.880	0.423	tNET	RR	1	R9C9[0][B]	pwm_g/n34_s2/I2
5.979	1.099	tINS	RF	2	R9C9[0][B]	pwm_g/n34_s2/F
5.990	0.011	tNET	FF	1	R9C9[2][A]	pwm_g/n34_s1/I2
7.089	1.099	tINS	FF	1	R9C9[2][A]	pwm_g/n34_s1/F
7.089	0.000	tNET	FF	1	R9C9[2][A]	pwm_g/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C9[2][A]	pwm_g/count_5_s0/CLK
11.730	-0.400	tSu		1	R9C9[2][A]	pwm_g/count_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.224, 65.010%; route: 1.277, 25.748%; tC2Q: 0.458, 9.242%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack	4.641
Data Arrival Time	7.089
Data Required Time	11.730
From	pwm_g/count_1_s0
To	pwm_g/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][A]	pwm_g/count_1_s0/CLK
2.588	0.458	tC2Q	RF	4	R9C9[1][A]	pwm_g/count_1_s0/Q
3.432	0.843	tNET	FF	1	R9C10[2][A]	pwm_g/n36_s2/I1
4.458	1.026	tINS	FR	3	R9C10[2][A]	pwm_g/n36_s2/F
4.880	0.423	tNET	RR	1	R9C9[0][B]	pwm_g/n34_s2/I2
5.979	1.099	tINS	RF	2	R9C9[0][B]	pwm_g/n34_s2/F
5.990	0.011	tNET	FF	1	R9C9[0][A]	pwm_g/n33_s1/I1
7.089	1.099	tINS	FF	1	R9C9[0][A]	pwm_g/n33_s1/F
7.089	0.000	tNET	FF	1	R9C9[0][A]	pwm_g/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C9[0][A]	pwm_g/count_6_s0/CLK
11.730	-0.400	tSu		1	R9C9[0][A]	pwm_g/count_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.224, 65.010%; route: 1.277, 25.748%; tC2Q: 0.458, 9.242%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack	4.739
Data Arrival Time	6.991
Data Required Time	11.730
From	pwm_r/count_0_s0
To	pwm_r/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C19[0][A]	pwm_r/count_0_s0/CLK
2.588	0.458	tC2Q	RR	5	R9C19[0][A]	pwm_r/count_0_s0/Q
3.020	0.432	tNET	RR	1	R9C18[3][A]	pwm_r/r_s0/I1
4.052	1.032	tINS	RF	3	R9C18[3][A]	pwm_r/r_s0/F
4.883	0.831	tNET	FF	1	R9C19[3][A]	pwm_r/n34_s2/I3
5.944	1.061	tINS	FR	2	R9C19[3][A]	pwm_r/n34_s2/F
6.365	0.421	tNET	RR	1	R9C18[2][A]	pwm_r/n34_s1/I2
6.991	0.626	tINS	RF	1	R9C18[2][A]	pwm_r/n34_s1/F
6.991	0.000	tNET	FF	1	R9C18[2][A]	pwm_r/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C18[2][A]	pwm_r/count_5_s0/CLK
11.730	-0.400	tSu		1	R9C18[2][A]	pwm_r/count_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.719, 55.935%; route: 1.684, 34.636%; tC2Q: 0.458, 9.429%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack	4.915
Data Arrival Time	6.815
Data Required Time	11.730
From	pwm_r/count_0_s0
To	pwm_r/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C19[0][A]	pwm_r/count_0_s0/CLK
2.588	0.458	tC2Q	RR	5	R9C19[0][A]	pwm_r/count_0_s0/Q
3.020	0.432	tNET	RR	1	R9C18[3][A]	pwm_r/r_s0/I1
4.052	1.032	tINS	RF	3	R9C18[3][A]	pwm_r/r_s0/F
4.883	0.831	tNET	FF	1	R9C19[3][A]	pwm_r/n34_s2/I3
5.982	1.099	tINS	FF	2	R9C19[3][A]	pwm_r/n34_s2/F
5.993	0.011	tNET	FF	1	R9C19[0][B]	pwm_r/n33_s1/I1
6.815	0.822	tINS	FF	1	R9C19[0][B]	pwm_r/n33_s1/F
6.815	0.000	tNET	FF	1	R9C19[0][B]	pwm_r/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C19[0][B]	pwm_r/count_6_s0/CLK
11.730	-0.400	tSu		1	R9C19[0][B]	pwm_r/count_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.953, 63.029%; route: 1.274, 27.188%; tC2Q: 0.458, 9.783%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack	4.957
Data Arrival Time	6.773
Data Required Time	11.730
From	pwm_g/count_3_s0
To	pwm_g/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
2.588	0.458	tC2Q	RF	5	R9C9[1][B]	pwm_g/count_3_s0/Q
3.430	0.842	tNET	FF	1	R9C10[0][A]	pwm_g/n39_s3/I1
4.055	0.625	tINS	FR	2	R9C10[0][A]	pwm_g/n39_s3/F
4.478	0.423	tNET	RR	1	R9C9[3][A]	pwm_g/n39_s2/I0
5.300	0.822	tINS	RF	6	R9C9[3][A]	pwm_g/n39_s2/F
6.147	0.847	tNET	FF	1	R9C10[2][B]	pwm_g/n37_s1/I2
6.773	0.626	tINS	FF	1	R9C10[2][B]	pwm_g/n37_s1/F
6.773	0.000	tNET	FF	1	R9C10[2][B]	pwm_g/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C10[2][B]	pwm_g/count_2_s0/CLK
11.730	-0.400	tSu		1	R9C10[2][B]	pwm_g/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.073, 44.647%; route: 2.112, 45.482%; tC2Q: 0.458, 9.871%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack	4.957
Data Arrival Time	6.773
Data Required Time	11.730
From	pwm_g/count_3_s0
To	pwm_g/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
2.588	0.458	tC2Q	RF	5	R9C9[1][B]	pwm_g/count_3_s0/Q
3.430	0.842	tNET	FF	1	R9C10[0][A]	pwm_g/n39_s3/I1
4.055	0.625	tINS	FR	2	R9C10[0][A]	pwm_g/n39_s3/F
4.478	0.423	tNET	RR	1	R9C9[3][A]	pwm_g/n39_s2/I0
5.300	0.822	tINS	RF	6	R9C9[3][A]	pwm_g/n39_s2/F
6.147	0.847	tNET	FF	1	R9C10[0][B]	pwm_g/n35_s1/I2
6.773	0.626	tINS	FF	1	R9C10[0][B]	pwm_g/n35_s1/F
6.773	0.000	tNET	FF	1	R9C10[0][B]	pwm_g/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C10[0][B]	pwm_g/count_4_s0/CLK
11.730	-0.400	tSu		1	R9C10[0][B]	pwm_g/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.073, 44.647%; route: 2.112, 45.482%; tC2Q: 0.458, 9.871%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack	5.340
Data Arrival Time	6.390
Data Required Time	11.730
From	pwm_r/count_2_s0
To	pwm_r/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
2.588	0.458	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
3.020	0.431	tNET	RR	1	R9C19[2][A]	pwm_r/n39_s3/I0
4.052	1.032	tINS	RF	2	R9C19[2][A]	pwm_r/n39_s3/F
4.063	0.011	tNET	FF	1	R9C19[2][B]	pwm_r/n39_s2/I0
4.865	0.802	tINS	FR	6	R9C19[2][B]	pwm_r/n39_s2/F
5.291	0.427	tNET	RR	1	R9C18[2][B]	pwm_r/n36_s1/I2
6.390	1.099	tINS	RF	1	R9C18[2][B]	pwm_r/n36_s1/F
6.390	0.000	tNET	FF	1	R9C18[2][B]	pwm_r/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C18[2][B]	pwm_r/count_3_s0/CLK
11.730	-0.400	tSu		1	R9C18[2][B]	pwm_r/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.933, 68.847%; route: 0.869, 20.394%; tC2Q: 0.458, 10.759%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack	5.581
Data Arrival Time	6.149
Data Required Time	11.730
From	pwm_g/count_3_s0
To	pwm_g/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
2.588	0.458	tC2Q	RF	5	R9C9[1][B]	pwm_g/count_3_s0/Q
3.430	0.842	tNET	FF	1	R9C10[0][A]	pwm_g/n39_s3/I1
4.055	0.625	tINS	FR	2	R9C10[0][A]	pwm_g/n39_s3/F
4.478	0.423	tNET	RR	1	R9C9[3][A]	pwm_g/n39_s2/I0
5.300	0.822	tINS	RF	6	R9C9[3][A]	pwm_g/n39_s2/F
5.327	0.027	tNET	FF	1	R9C9[1][A]	pwm_g/n38_s1/I0
6.149	0.822	tINS	FF	1	R9C9[1][A]	pwm_g/n38_s1/F
6.149	0.000	tNET	FF	1	R9C9[1][A]	pwm_g/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C9[1][A]	pwm_g/count_1_s0/CLK
11.730	-0.400	tSu		1	R9C9[1][A]	pwm_g/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.269, 56.454%; route: 1.292, 32.142%; tC2Q: 0.458, 11.404%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack	5.581
Data Arrival Time	6.149
Data Required Time	11.730
From	pwm_g/count_3_s0
To	pwm_g/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
2.588	0.458	tC2Q	RF	5	R9C9[1][B]	pwm_g/count_3_s0/Q
3.430	0.842	tNET	FF	1	R9C10[0][A]	pwm_g/n39_s3/I1
4.055	0.625	tINS	FR	2	R9C10[0][A]	pwm_g/n39_s3/F
4.478	0.423	tNET	RR	1	R9C9[3][A]	pwm_g/n39_s2/I0
5.300	0.822	tINS	RF	6	R9C9[3][A]	pwm_g/n39_s2/F
5.327	0.027	tNET	FF	1	R9C9[1][B]	pwm_g/n36_s1/I0
6.149	0.822	tINS	FF	1	R9C9[1][B]	pwm_g/n36_s1/F
6.149	0.000	tNET	FF	1	R9C9[1][B]	pwm_g/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
11.730	-0.400	tSu		1	R9C9[1][B]	pwm_g/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.269, 56.454%; route: 1.292, 32.142%; tC2Q: 0.458, 11.404%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack	5.613
Data Arrival Time	6.117
Data Required Time	11.730
From	pwm_r/count_2_s0
To	pwm_r/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
2.588	0.458	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
3.020	0.431	tNET	RR	1	R9C19[2][A]	pwm_r/n39_s3/I0
4.052	1.032	tINS	RF	2	R9C19[2][A]	pwm_r/n39_s3/F
4.063	0.011	tNET	FF	1	R9C19[2][B]	pwm_r/n39_s2/I0
4.865	0.802	tINS	FR	6	R9C19[2][B]	pwm_r/n39_s2/F
5.295	0.431	tNET	RR	1	R9C18[0][B]	pwm_r/n38_s1/I0
6.117	0.822	tINS	RF	1	R9C18[0][B]	pwm_r/n38_s1/F
6.117	0.000	tNET	FF	1	R9C18[0][B]	pwm_r/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C18[0][B]	pwm_r/count_1_s0/CLK
11.730	-0.400	tSu		1	R9C18[0][B]	pwm_r/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.656, 66.615%; route: 0.873, 21.890%; tC2Q: 0.458, 11.495%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path11

Path Summary:

Slack	5.613
Data Arrival Time	6.117
Data Required Time	11.730
From	pwm_r/count_2_s0
To	pwm_r/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
2.588	0.458	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
3.020	0.431	tNET	RR	1	R9C19[2][A]	pwm_r/n39_s3/I0
4.052	1.032	tINS	RF	2	R9C19[2][A]	pwm_r/n39_s3/F
4.063	0.011	tNET	FF	1	R9C19[2][B]	pwm_r/n39_s2/I0
4.865	0.802	tINS	FR	6	R9C19[2][B]	pwm_r/n39_s2/F
5.295	0.431	tNET	RR	1	R9C18[1][A]	pwm_r/n37_s2/I0
6.117	0.822	tINS	RF	1	R9C18[1][A]	pwm_r/n37_s2/F
6.117	0.000	tNET	FF	1	R9C18[1][A]	pwm_r/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
11.730	-0.400	tSu		1	R9C18[1][A]	pwm_r/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.656, 66.615%; route: 0.873, 21.890%; tC2Q: 0.458, 11.495%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path12

Path Summary:

Slack	5.613
Data Arrival Time	6.117
Data Required Time	11.730
From	pwm_r/count_2_s0
To	pwm_r/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
2.588	0.458	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
3.020	0.431	tNET	RR	1	R9C19[2][A]	pwm_r/n39_s3/I0
4.052	1.032	tINS	RF	2	R9C19[2][A]	pwm_r/n39_s3/F
4.063	0.011	tNET	FF	1	R9C19[2][B]	pwm_r/n39_s2/I0
4.865	0.802	tINS	FR	6	R9C19[2][B]	pwm_r/n39_s2/F
5.295	0.431	tNET	RR	1	R9C18[1][B]	pwm_r/n35_s1/I0
6.117	0.822	tINS	RF	1	R9C18[1][B]	pwm_r/n35_s1/F
6.117	0.000	tNET	FF	1	R9C18[1][B]	pwm_r/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C18[1][B]	pwm_r/count_4_s0/CLK
11.730	-0.400	tSu		1	R9C18[1][B]	pwm_r/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 2.656, 66.615%; route: 0.873, 21.890%; tC2Q: 0.458, 11.495%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack	6.430
Data Arrival Time	5.300
Data Required Time	11.730
From	pwm_g/count_3_s0
To	pwm_g/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
2.588	0.458	tC2Q	RF	5	R9C9[1][B]	pwm_g/count_3_s0/Q
3.430	0.842	tNET	FF	1	R9C10[0][A]	pwm_g/n39_s3/I1
4.055	0.625	tINS	FR	2	R9C10[0][A]	pwm_g/n39_s3/F
4.478	0.423	tNET	RR	1	R9C9[2][B]	pwm_g/n39_s4/I1
5.300	0.822	tINS	RF	1	R9C9[2][B]	pwm_g/n39_s4/F
5.300	0.000	tNET	FF	1	R9C9[2][B]	pwm_g/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C9[2][B]	pwm_g/count_0_s0/CLK
11.730	-0.400	tSu		1	R9C9[2][B]	pwm_g/count_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 1.447, 45.650%; route: 1.264, 39.890%; tC2Q: 0.458, 14.460%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path14

Path Summary:

Slack	6.846
Data Arrival Time	4.885
Data Required Time	11.730
From	pwm_r/count_2_s0
To	pwm_r/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
2.588	0.458	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
3.020	0.431	tNET	RR	1	R9C19[2][A]	pwm_r/n39_s3/I0
4.052	1.032	tINS	RF	2	R9C19[2][A]	pwm_r/n39_s3/F
4.063	0.011	tNET	FF	1	R9C19[0][A]	pwm_r/n39_s4/I1
4.885	0.822	tINS	FF	1	R9C19[0][A]	pwm_r/n39_s4/F
4.885	0.000	tNET	FF	1	R9C19[0][A]	pwm_r/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	14	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C19[0][A]	pwm_r/count_0_s0/CLK
11.730	-0.400	tSu		1	R9C19[0][A]	pwm_r/count_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 1.854, 67.310%; route: 0.442, 16.050%; tC2Q: 0.458, 16.640%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	2.358
Data Required Time	1.651
From	pwm_r/count_0_s0
To	pwm_r/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C19[0][A]	pwm_r/count_0_s0/CLK
1.984	0.333	tC2Q	RR	5	R9C19[0][A]	pwm_r/count_0_s0/Q
1.986	0.002	tNET	RR	1	R9C19[0][A]	pwm_r/n39_s4/I0
2.358	0.372	tINS	RF	1	R9C19[0][A]	pwm_r/n39_s4/F
2.358	0.000	tNET	FF	1	R9C19[0][A]	pwm_r/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C19[0][A]	pwm_r/count_0_s0/CLK
1.651	0.000	tHld		1	R9C19[0][A]	pwm_r/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	2.358
Data Required Time	1.651
From	pwm_g/count_1_s0
To	pwm_g/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[1][A]	pwm_g/count_1_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C9[1][A]	pwm_g/count_1_s0/Q
1.986	0.002	tNET	RR	1	R9C9[1][A]	pwm_g/n38_s1/I2
2.358	0.372	tINS	RF	1	R9C9[1][A]	pwm_g/n38_s1/F
2.358	0.000	tNET	FF	1	R9C9[1][A]	pwm_g/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[1][A]	pwm_g/count_1_s0/CLK
1.651	0.000	tHld		1	R9C9[1][A]	pwm_g/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack	0.710
Data Arrival Time	2.361
Data Required Time	1.651
From	pwm_r/count_2_s0
To	pwm_r/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
1.984	0.333	tC2Q	RR	6	R9C18[1][A]	pwm_r/count_2_s0/Q
1.989	0.005	tNET	RR	1	R9C18[1][A]	pwm_r/n37_s2/I1
2.361	0.372	tINS	RF	1	R9C18[1][A]	pwm_r/n37_s2/F
2.361	0.000	tNET	FF	1	R9C18[1][A]	pwm_r/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
1.651	0.000	tHld		1	R9C18[1][A]	pwm_r/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack	0.710
Data Arrival Time	2.361
Data Required Time	1.651
From	pwm_g/count_6_s0
To	pwm_g/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[0][A]	pwm_g/count_6_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C9[0][A]	pwm_g/count_6_s0/Q
1.989	0.005	tNET	RR	1	R9C9[0][A]	pwm_g/n33_s1/I2
2.361	0.372	tINS	RF	1	R9C9[0][A]	pwm_g/n33_s1/F
2.361	0.000	tNET	FF	1	R9C9[0][A]	pwm_g/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[0][A]	pwm_g/count_6_s0/CLK
1.651	0.000	tHld		1	R9C9[0][A]	pwm_g/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack	0.893
Data Arrival Time	2.544
Data Required Time	1.651
From	pwm_r/count_5_s0
To	pwm_r/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[2][A]	pwm_r/count_5_s0/CLK
1.984	0.333	tC2Q	RR	5	R9C18[2][A]	pwm_r/count_5_s0/Q
1.988	0.004	tNET	RR	1	R9C18[2][A]	pwm_r/n34_s1/I1
2.544	0.556	tINS	RR	1	R9C18[2][A]	pwm_r/n34_s1/F
2.544	0.000	tNET	RR	1	R9C18[2][A]	pwm_r/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[2][A]	pwm_r/count_5_s0/CLK
1.651	0.000	tHld		1	R9C18[2][A]	pwm_r/count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack	0.943
Data Arrival Time	2.594
Data Required Time	1.651
From	pwm_r/count_5_s0
To	pwm_r/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[2][A]	pwm_r/count_5_s0/CLK
1.984	0.333	tC2Q	RF	5	R9C18[2][A]	pwm_r/count_5_s0/Q
2.222	0.238	tNET	FF	1	R9C19[0][B]	pwm_r/n33_s1/I0
2.594	0.372	tINS	FF	1	R9C19[0][B]	pwm_r/n33_s1/F
2.594	0.000	tNET	FF	1	R9C19[0][B]	pwm_r/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C19[0][B]	pwm_r/count_6_s0/CLK
1.651	0.000	tHld		1	R9C19[0][B]	pwm_r/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack	0.946
Data Arrival Time	2.597
Data Required Time	1.651
From	pwm_r/count_2_s0
To	pwm_r/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[1][A]	pwm_r/count_2_s0/CLK
1.984	0.333	tC2Q	RF	6	R9C18[1][A]	pwm_r/count_2_s0/Q
2.225	0.241	tNET	FF	1	R9C18[2][B]	pwm_r/n36_s1/I0
2.597	0.372	tINS	FF	1	R9C18[2][B]	pwm_r/n36_s1/F
2.597	0.000	tNET	FF	1	R9C18[2][B]	pwm_r/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[2][B]	pwm_r/count_3_s0/CLK
1.651	0.000	tHld		1	R9C18[2][B]	pwm_r/count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 39.312%; route: 0.241, 25.462%; tC2Q: 0.333, 35.226%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack	0.946
Data Arrival Time	2.597
Data Required Time	1.651
From	pwm_g/count_6_s0
To	pwm_g/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[0][A]	pwm_g/count_6_s0/CLK
1.984	0.333	tC2Q	RF	4	R9C9[0][A]	pwm_g/count_6_s0/Q
2.225	0.241	tNET	FF	1	R9C9[2][B]	pwm_g/n39_s4/I3
2.597	0.372	tINS	FF	1	R9C9[2][B]	pwm_g/n39_s4/F
2.597	0.000	tNET	FF	1	R9C9[2][B]	pwm_g/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[2][B]	pwm_g/count_0_s0/CLK
1.651	0.000	tHld		1	R9C9[2][B]	pwm_g/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 39.312%; route: 0.241, 25.462%; tC2Q: 0.333, 35.226%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack	1.060
Data Arrival Time	2.710
Data Required Time	1.651
From	pwm_r/count_4_s0
To	pwm_r/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[1][B]	pwm_r/count_4_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C18[1][B]	pwm_r/count_4_s0/Q
1.986	0.002	tNET	RR	1	R9C18[1][B]	pwm_r/n35_s1/I2
2.710	0.724	tINS	RR	1	R9C18[1][B]	pwm_r/n35_s1/F
2.710	0.000	tNET	RR	1	R9C18[1][B]	pwm_r/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[1][B]	pwm_r/count_4_s0/CLK
1.651	0.000	tHld		1	R9C18[1][B]	pwm_r/count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack	1.061
Data Arrival Time	2.712
Data Required Time	1.651
From	pwm_r/count_1_s0
To	pwm_r/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[0][B]	pwm_r/count_1_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C18[0][B]	pwm_r/count_1_s0/Q
1.988	0.004	tNET	RR	1	R9C18[0][B]	pwm_r/n38_s1/I1
2.712	0.724	tINS	RR	1	R9C18[0][B]	pwm_r/n38_s1/F
2.712	0.000	tNET	RR	1	R9C18[0][B]	pwm_r/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C18[0][B]	pwm_r/count_1_s0/CLK
1.651	0.000	tHld		1	R9C18[0][B]	pwm_r/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack	1.061
Data Arrival Time	2.712
Data Required Time	1.651
From	pwm_g/count_4_s0
To	pwm_g/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[0][B]	pwm_g/count_4_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C10[0][B]	pwm_g/count_4_s0/Q
1.988	0.004	tNET	RR	1	R9C10[0][B]	pwm_g/n35_s1/I3
2.712	0.724	tINS	RR	1	R9C10[0][B]	pwm_g/n35_s1/F
2.712	0.000	tNET	RR	1	R9C10[0][B]	pwm_g/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[0][B]	pwm_g/count_4_s0/CLK
1.651	0.000	tHld		1	R9C10[0][B]	pwm_g/count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack	1.062
Data Arrival Time	2.712
Data Required Time	1.651
From	pwm_g/count_2_s0
To	pwm_g/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[2][B]	pwm_g/count_2_s0/CLK
1.984	0.333	tC2Q	RR	4	R9C10[2][B]	pwm_g/count_2_s0/Q
1.986	0.002	tNET	RR	1	R9C10[2][B]	pwm_g/n37_s1/I3
2.712	0.726	tINS	RR	1	R9C10[2][B]	pwm_g/n37_s1/F
2.712	0.000	tNET	RR	1	R9C10[2][B]	pwm_g/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C10[2][B]	pwm_g/count_2_s0/CLK
1.651	0.000	tHld		1	R9C10[2][B]	pwm_g/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.726, 68.381%; route: 0.002, 0.222%; tC2Q: 0.333, 31.396%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack	1.062
Data Arrival Time	2.713
Data Required Time	1.651
From	pwm_g/count_3_s0
To	pwm_g/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
1.984	0.333	tC2Q	RR	5	R9C9[1][B]	pwm_g/count_3_s0/Q
1.989	0.005	tNET	RR	1	R9C9[1][B]	pwm_g/n36_s1/I1
2.713	0.724	tINS	RR	1	R9C9[1][B]	pwm_g/n36_s1/F
2.713	0.000	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[1][B]	pwm_g/count_3_s0/CLK
1.651	0.000	tHld		1	R9C9[1][B]	pwm_g/count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path14

Path Summary:

Slack	1.298
Data Arrival Time	2.949
Data Required Time	1.651
From	pwm_g/count_5_s0
To	pwm_g/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[2][A]	pwm_g/count_5_s0/CLK
1.984	0.333	tC2Q	RR	5	R9C9[2][A]	pwm_g/count_5_s0/Q
2.223	0.239	tNET	RR	1	R9C9[2][A]	pwm_g/n34_s1/I1
2.949	0.726	tINS	RR	1	R9C9[2][A]	pwm_g/n34_s1/F
2.949	0.000	tNET	RR	1	R9C9[2][A]	pwm_g/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	14	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C9[2][A]	pwm_g/count_5_s0/CLK
1.651	0.000	tHld		1	R9C9[2][A]	pwm_g/count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.726, 55.928%; route: 0.239, 18.393%; tC2Q: 0.333, 25.679%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_6_s0/CLK

MPW2

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_4_s0/CLK

MPW3

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_0_s0/CLK

MPW4

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_r/count_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_r/count_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_r/count_0_s0/CLK

MPW5

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_1_s0/CLK

MPW6

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_r/count_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_r/count_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_r/count_1_s0/CLK

MPW7

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_r/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_r/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_r/count_2_s0/CLK

MPW8

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_5_s0/CLK

MPW9

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_g/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_g/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_g/count_2_s0/CLK

MPW10

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	pwm_r/count_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	pwm_r/count_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	pwm_r/count_3_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
14	clk_d	4.641	1.505
6	n39_6	5.340	0.431
6	count[2]	5.340	0.431
6	n39_6	4.957	0.847
5	count[3]	5.551	0.430
5	count[5]	6.125	0.430
5	count[0]	4.739	0.432
5	count[3]	4.957	0.842
5	count[5]	6.274	0.422
5	count[0]	5.019	0.430

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C9	18.06%
R9C18	18.06%
R9C10	16.67%
R9C19	12.50%
R11C20	8.33%
R20C20	6.94%
R20C21	6.94%
R11C9	6.94%
R9C22	5.56%
R11C1	5.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command