Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\gw_jtag.v
C:\Gowin\Workspace\stopwatch\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.03Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Tue Jun 01 09:28:06 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 27.535MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 27.535MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 27.535MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 27.535MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 27.535MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 27.535MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 27.535MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 27.535MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 27.535MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 27.535MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 27.535MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 27.535MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.702s, Peak memory usage = 41.691MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 41.691MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 41.691MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 41.691MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 7
I/O Buf 7
    IBUF 6
    OBUF 1
Register 118
    DFFP 1
    DFFC 17
    DFFCE 94
    DFFNP 2
    DFFNC 4
LUT 130
    LUT2 19
    LUT3 27
    LUT4 84
INV 2
    INV 2
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 132(132 LUTs, 0 ALUs) / 4608 3%
Register 118 / 3756 3%
  --Register as Latch 0 / 3756 0%
  --Register as FF 118 / 3756 3%
BSRAM 1 / 10 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk1m Base 10.000 100.0 0.000 5.000 clk1m_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk1m 100.0(MHz) 135.6(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.623
Data Arrival Time 8.322
Data Required Time 10.945
From u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3
To u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s4
Launch Clk clk1m[R]
Latch Clk clk1m[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk1m
0.000 0.000 tCL RR 1 clk1m_ibuf/I
0.982 0.982 tINS RR 24 clk1m_ibuf/O
1.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/Q
2.283 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n91_s2/I1
3.382 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/n91_s2/F
3.862 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n89_s2/I2
4.684 0.822 tINS FF 4 u_ao_top/u_ao_mem_ctrl/n89_s2/F
5.164 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/I1
6.263 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
6.743 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n86_s3/I1
7.842 1.099 tINS FF 1 u_ao_top/u_ao_mem_ctrl/n86_s3/F
8.322 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk1m
10.000 0.000 tCL RR 1 clk1m_ibuf/I
10.982 0.982 tINS RR 24 clk1m_ibuf/O
11.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s4/CLK
10.945 -0.400 tSu 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 3.169
Data Arrival Time 8.132
Data Required Time 11.302
From u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3
To u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk1m[R]
Latch Clk clk1m[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk1m
0.000 0.000 tCL RR 1 clk1m_ibuf/I
0.982 0.982 tINS RR 24 clk1m_ibuf/O
1.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/Q
2.283 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n91_s2/I1
3.382 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/n91_s2/F
3.862 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n89_s2/I2
4.684 0.822 tINS FF 4 u_ao_top/u_ao_mem_ctrl/n89_s2/F
5.164 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/I1
6.263 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
6.743 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s3/I0
7.769 1.026 tINS FR 1 u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s3/F
8.132 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk1m
10.000 0.000 tCL RR 1 clk1m_ibuf/I
10.982 0.982 tINS RR 24 clk1m_ibuf/O
11.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.302 -0.043 tSu 1 u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.046, 59.611%; route: 2.283, 33.636%; tC2Q: 0.458, 6.753%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 3.393
Data Arrival Time 7.908
Data Required Time 11.302
From u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3
To u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk1m[R]
Latch Clk clk1m[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk1m
0.000 0.000 tCL RR 1 clk1m_ibuf/I
0.982 0.982 tINS RR 24 clk1m_ibuf/O
1.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/Q
2.283 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n91_s2/I1
3.382 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/n91_s2/F
3.862 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n89_s2/I2
4.684 0.822 tINS FF 4 u_ao_top/u_ao_mem_ctrl/n89_s2/F
5.164 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/I1
6.263 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
6.743 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
7.545 0.802 tINS FR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
7.908 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk1m
10.000 0.000 tCL RR 1 clk1m_ibuf/I
10.982 0.982 tINS RR 24 clk1m_ibuf/O
11.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
11.302 -0.043 tSu 1 u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.822, 58.233%; route: 2.283, 34.784%; tC2Q: 0.458, 6.983%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 4.202
Data Arrival Time 6.743
Data Required Time 10.945
From u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3
To u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk1m[R]
Latch Clk clk1m[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk1m
0.000 0.000 tCL RR 1 clk1m_ibuf/I
0.982 0.982 tINS RR 24 clk1m_ibuf/O
1.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/Q
2.283 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n91_s2/I1
3.382 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/n91_s2/F
3.862 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n89_s2/I2
4.684 0.822 tINS FF 4 u_ao_top/u_ao_mem_ctrl/n89_s2/F
5.164 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n88_s1/I1
6.263 1.099 tINS FF 1 u_ao_top/u_ao_mem_ctrl/n88_s1/F
6.743 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk1m
10.000 0.000 tCL RR 1 clk1m_ibuf/I
10.982 0.982 tINS RR 24 clk1m_ibuf/O
11.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.945 -0.400 tSu 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.020, 55.943%; route: 1.920, 35.567%; tC2Q: 0.458, 8.490%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 4.269
Data Arrival Time 6.676
Data Required Time 10.945
From u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3
To u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk1m[R]
Latch Clk clk1m[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk1m
0.000 0.000 tCL RR 1 clk1m_ibuf/I
0.982 0.982 tINS RR 24 clk1m_ibuf/O
1.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s3/Q
2.283 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n91_s2/I1
3.382 1.099 tINS FF 3 u_ao_top/u_ao_mem_ctrl/n91_s2/F
3.862 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n89_s2/I2
4.684 0.822 tINS FF 4 u_ao_top/u_ao_mem_ctrl/n89_s2/F
5.164 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/n87_s1/I0
6.196 1.032 tINS FF 1 u_ao_top/u_ao_mem_ctrl/n87_s1/F
6.676 0.480 tNET FF 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk1m
10.000 0.000 tCL RR 1 clk1m_ibuf/I
10.982 0.982 tINS RR 24 clk1m_ibuf/O
11.345 0.363 tNET RR 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.945 -0.400 tSu 1 u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 2.953, 55.389%; route: 1.920, 36.014%; tC2Q: 0.458, 8.597%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%