Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Gowin\Workspace\stopwatch\src\clkdiv.v C:\Gowin\Workspace\stopwatch\src\cntr4max.v C:\Gowin\Workspace\stopwatch\src\cntr4maxe.v C:\Gowin\Workspace\stopwatch\src\debounce.v C:\Gowin\Workspace\stopwatch\src\dec_led.v C:\Gowin\Workspace\stopwatch\src\drv7seg.v C:\Gowin\Workspace\stopwatch\src\mux7seg.v C:\Gowin\Workspace\stopwatch\src\stopwatch.v C:\Gowin\Workspace\stopwatch\src\toggle.v
GowinSynthesis Constraints File	---
GowinSynthesis Version	GowinSynthesis V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 14:35:28 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	stopwatch
Synthesis Process	Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 70.008MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 70.008MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 70.008MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 70.008MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 70.008MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.008MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.008MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.008MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 70.008MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 70.008MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 70.008MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.751s, Peak memory usage = 85.121MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 85.121MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 85.121MB
Total Time and Memory Usage	CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 85.121MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	23
I/O Buf	23
IBUF	3
OBUF	20
Register	71
DFF	3
DFFR	11
DFFC	40
DFFCE	17
LUT	143
LUT2	17
LUT3	46
LUT4	80
ALU	10
ALU	10
INV	3
INV	3

Resource Utilization Summary

Resource	Usage	Utilization
Logic	156(146 LUTs, 10 ALUs) / 4608	3%
Register	71 / 3756	2%
--Register as Latch	0 / 3756	0%
--Register as FF	71 / 3756	2%
BSRAM	0 / 10	0%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Object
clk	Base	10.000	100.0	5.000	clk_ibuf/I
clk400Hz	Base	10.000	100.0	5.000	inst2/clkdiv_1/clk400Hz_s/F
clk10KHz	Base	10.000	100.0	5.000	inst20/i4/clk10KHz_s/F

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.0(MHz)	131.8(MHz)	5	TOP
2	clk400Hz	100.0(MHz)	747.2(MHz)	1	TOP
3	clk10KHz	100.0(MHz)	342.8(MHz)	2	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	2.413
Data Arrival Time	8.532
Data Required Time	10.945
From	inst1/count_6_s0
To	inst8/cnt_1_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	64	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_6_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_6_s0/Q
2.283	0.480	tNET	FF	1	inst4/clk10hz_s4/I1
3.382	1.099	tINS	FF	1	inst4/clk10hz_s4/F
3.862	0.480	tNET	FF	1	inst4/clk10hz_s2/I1
4.961	1.099	tINS	FF	4	inst4/clk10hz_s2/F
5.441	0.480	tNET	FF	1	inst8/n16_s2/I0
6.473	1.032	tINS	FF	7	inst8/n16_s2/F
6.953	0.480	tNET	FF	1	inst8/n15_s1/I1
8.052	1.099	tINS	FF	1	inst8/n15_s1/F
8.532	0.480	tNET	FF	1	inst8/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	64	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst8/cnt_1_s0/CLK
10.945	-0.400	tSu		1	inst8/cnt_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:

Slack	2.413
Data Arrival Time	8.532
Data Required Time	10.945
From	inst1/count_6_s0
To	inst8/cnt_2_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	64	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_6_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_6_s0/Q
2.283	0.480	tNET	FF	1	inst4/clk10hz_s4/I1
3.382	1.099	tINS	FF	1	inst4/clk10hz_s4/F
3.862	0.480	tNET	FF	1	inst4/clk10hz_s2/I1
4.961	1.099	tINS	FF	4	inst4/clk10hz_s2/F
5.441	0.480	tNET	FF	1	inst8/n16_s2/I0
6.473	1.032	tINS	FF	7	inst8/n16_s2/F
6.953	0.480	tNET	FF	1	inst8/n14_s1/I1
8.052	1.099	tINS	FF	1	inst8/n14_s1/F
8.532	0.480	tNET	FF	1	inst8/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	64	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst8/cnt_2_s0/CLK
10.945	-0.400	tSu		1	inst8/cnt_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:

Slack	2.413
Data Arrival Time	8.532
Data Required Time	10.945
From	inst1/count_6_s0
To	inst7/cnt_0_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	64	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_6_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_6_s0/Q
2.283	0.480	tNET	FF	1	inst4/clk10hz_s4/I1
3.382	1.099	tINS	FF	1	inst4/clk10hz_s4/F
3.862	0.480	tNET	FF	1	inst4/clk10hz_s2/I1
4.961	1.099	tINS	FF	4	inst4/clk10hz_s2/F
5.441	0.480	tNET	FF	1	inst8/n16_s2/I0
6.473	1.032	tINS	FF	7	inst8/n16_s2/F
6.953	0.480	tNET	FF	1	inst7/n16_s1/I1
8.052	1.099	tINS	FF	1	inst7/n16_s1/F
8.532	0.480	tNET	FF	1	inst7/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	64	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst7/cnt_0_s0/CLK
10.945	-0.400	tSu		1	inst7/cnt_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:

Slack	2.413
Data Arrival Time	8.532
Data Required Time	10.945
From	inst1/count_5_s0
To	inst6/cnt_3_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	64	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_5_s0/CLK
1.803	0.458	tC2Q	RF	3	inst1/count_5_s0/Q
2.283	0.480	tNET	FF	1	inst4/clk10hz_s0/I1
3.382	1.099	tINS	FF	4	inst4/clk10hz_s0/F
3.862	0.480	tNET	FF	1	inst6/clk10s_s0/I1
4.961	1.099	tINS	FF	3	inst6/clk10s_s0/F
5.441	0.480	tNET	FF	1	inst6/clk10s_s/I1
6.540	1.099	tINS	FF	7	inst6/clk10s_s/F
7.020	0.480	tNET	FF	1	inst6/n13_s1/I0
8.052	1.032	tINS	FF	1	inst6/n13_s1/F
8.532	0.480	tNET	FF	1	inst6/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	64	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst6/cnt_3_s0/CLK
10.945	-0.400	tSu		1	inst6/cnt_3_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:

Slack	2.413
Data Arrival Time	8.532
Data Required Time	10.945
From	inst1/count_5_s0
To	inst6/cnt_1_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	64	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_5_s0/CLK
1.803	0.458	tC2Q	RF	3	inst1/count_5_s0/Q
2.283	0.480	tNET	FF	1	inst4/clk10hz_s0/I1
3.382	1.099	tINS	FF	4	inst4/clk10hz_s0/F
3.862	0.480	tNET	FF	1	inst6/clk10s_s0/I1
4.961	1.099	tINS	FF	3	inst6/clk10s_s0/F
5.441	0.480	tNET	FF	1	inst6/clk10s_s/I1
6.540	1.099	tINS	FF	7	inst6/clk10s_s/F
7.020	0.480	tNET	FF	1	inst6/n15_s1/I0
8.052	1.032	tINS	FF	1	inst6/n15_s1/F
8.532	0.480	tNET	FF	1	inst6/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	64	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst6/cnt_1_s0/CLK
10.945	-0.400	tSu		1	inst6/cnt_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%