Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Gowin\Workspace\stopwatch\impl\gwsynthesis\stopwatch.vg
Physical Constraints File	C:\Gowin\Workspace\stopwatch\src\counter.cst
Timing Constraint File	---
GOWIN version	V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 14:35:36 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 2.375V 85C
Hold Delay Model	Fast 2.625V 0C
Numbers of Paths Analyzed	459
Numbers of Endpoints Analyzed	544
Numbers of Falling Endpoints	2
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	18

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Objects
clk	Base	10.000	100.000	5.000	clk_ibuf/I
u_gw_jtag/tck_pad_i	Base	20.000	50.000	10.000	u_gw_jtag/tck_pad_i
inst2/clk400Hz	Base	10.000	100.000	5.000	inst2/clkdiv_1/clk400Hz_s/F
inst20/clk10KHz	Base	10.000	100.000	5.000	inst20/i4/clk10KHz_s/F

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	122.291(MHz)	5	TOP
2	u_gw_jtag/tck_pad_i	50.000(MHz)	84.816(MHz)	5	TOP
3	inst2/clk400Hz	100.000(MHz)	278.546(MHz)	1	TOP
4	inst20/clk10KHz	100.000(MHz)	446.598(MHz)	2	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
u_gw_jtag/tck_pad_i	Setup	0.000	0
u_gw_jtag/tck_pad_i	Hold	0.000	0
inst2/clk400Hz	Setup	0.000	0
inst2/clk400Hz	Hold	0.000	0
inst20/clk10KHz	Setup	0.000	0
inst20/clk10KHz	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	1.823	inst1/count_7_s0/Q	inst1/count_4_s0/D	clk:[R]	clk:[R]	10.000	7.777
2	1.824	inst1/count_13_s0/Q	inst7/cnt_1_s0/D	clk:[R]	clk:[R]	10.000	7.776
3	1.824	inst1/count_13_s0/Q	inst7/cnt_2_s0/D	clk:[R]	clk:[R]	10.000	7.776
4	1.919	inst1/count_7_s0/Q	inst1/count_12_s0/D	clk:[R]	clk:[R]	10.000	7.681
5	1.930	inst1/count_7_s0/Q	inst1/count_1_s0/D	clk:[R]	clk:[R]	10.000	7.670
6	1.930	inst1/count_7_s0/Q	inst1/count_2_s0/D	clk:[R]	clk:[R]	10.000	7.670
7	2.100	inst1/count_7_s0/Q	inst1/count_3_s0/D	clk:[R]	clk:[R]	10.000	7.500
8	2.264	inst2/clkdiv_1/count_1_s0/Q	inst2/clkdiv_1/count_13_s0/D	clk:[R]	clk:[R]	10.000	7.336
9	2.296	inst1/count_7_s0/Q	inst1/count_5_s0/D	clk:[R]	clk:[R]	10.000	7.304
10	2.330	inst1/count_7_s0/Q	inst1/count_16_s0/D	clk:[R]	clk:[R]	10.000	7.270
11	2.374	inst1/count_13_s0/Q	inst7/cnt_0_s0/D	clk:[R]	clk:[R]	10.000	7.226
12	2.397	inst1/count_7_s0/Q	inst1/count_10_s0/D	clk:[R]	clk:[R]	10.000	7.203
13	2.438	inst1/count_13_s0/Q	inst6/cnt_1_s0/CE	clk:[R]	clk:[R]	10.000	7.519
14	2.438	inst1/count_13_s0/Q	inst6/cnt_2_s0/CE	clk:[R]	clk:[R]	10.000	7.519
15	2.443	inst1/count_13_s0/Q	inst5/cnt_2_s0/D	clk:[R]	clk:[R]	10.000	7.157
16	2.459	inst1/count_13_s0/Q	inst5/cnt_3_s0/D	clk:[R]	clk:[R]	10.000	7.141
17	2.485	inst1/count_13_s0/Q	inst5/cnt_1_s0/D	clk:[R]	clk:[R]	10.000	7.115
18	2.485	inst1/count_13_s0/Q	inst4/cnt_0_s1/D	clk:[R]	clk:[R]	10.000	7.115
19	2.489	inst1/count_13_s0/Q	inst4/cnt_3_s0/D	clk:[R]	clk:[R]	10.000	7.111
20	2.602	inst1/count_7_s0/Q	inst1/count_13_s0/D	clk:[R]	clk:[R]	10.000	6.998
21	2.602	inst1/count_7_s0/Q	inst1/count_14_s0/D	clk:[R]	clk:[R]	10.000	6.998
22	2.614	inst1/count_7_s0/Q	inst1/count_11_s0/D	clk:[R]	clk:[R]	10.000	6.986
23	2.635	inst2/clkdiv_1/count_1_s0/Q	inst2/clkdiv_1/count_14_s0/D	clk:[R]	clk:[R]	10.000	6.965
24	2.644	inst1/count_7_s0/Q	inst8/cnt_3_s0/CE	clk:[R]	clk:[R]	10.000	7.313
25	2.644	inst1/count_7_s0/Q	inst8/cnt_0_s0/CE	clk:[R]	clk:[R]	10.000	7.313

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	-0.952	inst2/clkdiv_1/n49_s1/I0	inst2/clkdiv_1/count_6_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	0.729
2	-0.952	inst2/clkdiv_1/n48_s1/I2	inst2/clkdiv_1/count_7_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	0.729
3	-0.555	inst20/i4/count_0_s0/RESET	inst20/i4/count_0_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.140
4	-0.552	inst20/i4/count_7_s0/RESET	inst20/i4/count_7_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.144
5	-0.552	inst20/i4/count_8_s0/RESET	inst20/i4/count_8_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.144
6	-0.552	inst20/i4/count_9_s0/RESET	inst20/i4/count_9_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.144
7	-0.552	inst20/i4/count_10_s0/RESET	inst20/i4/count_10_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.144
8	-0.548	inst20/i4/count_1_s0/RESET	inst20/i4/count_1_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
9	-0.548	inst20/i4/count_2_s0/RESET	inst20/i4/count_2_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
10	-0.548	inst20/i4/count_3_s0/RESET	inst20/i4/count_3_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
11	-0.548	inst20/i4/count_4_s0/RESET	inst20/i4/count_4_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
12	-0.548	inst20/i4/count_5_s0/RESET	inst20/i4/count_5_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
13	-0.548	inst20/i4/count_6_s0/RESET	inst20/i4/count_6_s0/RESET	inst20/clk10KHz:[R]	clk:[R]	-1.651	1.148
14	-0.143	inst2/clkdiv_1/n53_s1/I2	inst2/clkdiv_1/count_2_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.538
15	-0.141	inst2/clkdiv_1/n55_s1/I1	inst2/clkdiv_1/count_0_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.540
16	-0.141	inst2/clkdiv_1/n46_s1/I2	inst2/clkdiv_1/count_9_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.540
17	-0.141	inst2/clkdiv_1/n43_s1/I0	inst2/clkdiv_1/count_12_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.540
18	-0.140	inst2/clkdiv_1/n41_s1/I3	inst2/clkdiv_1/count_14_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.541
19	0.209	inst2/clkdiv_1/n47_s1/I0	inst2/clkdiv_1/count_8_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.890
20	0.209	inst2/clkdiv_1/n42_s1/I2	inst2/clkdiv_1/count_13_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.890
21	0.211	inst2/clkdiv_1/n52_s1/I0	inst2/clkdiv_1/count_3_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.892
22	0.212	inst2/clkdiv_1/n54_s1/I0	inst2/clkdiv_1/count_1_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.893
23	0.212	inst2/clkdiv_1/n45_s1/I0	inst2/clkdiv_1/count_10_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.893
24	0.214	inst2/clkdiv_1/n51_s1/I0	inst2/clkdiv_1/count_4_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.895
25	0.214	inst2/clkdiv_1/n50_s1/I2	inst2/clkdiv_1/count_5_s0/D	inst2/clk400Hz:[R]	clk:[R]	-1.651	1.895

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.911	4.161	1.250	Low Pulse Width	clk	inst1/count_16_s0
2	2.911	4.161	1.250	Low Pulse Width	clk	inst1/count_14_s0
3	2.911	4.161	1.250	Low Pulse Width	clk	inst1/count_10_s0
4	2.911	4.161	1.250	Low Pulse Width	clk	inst1/count_2_s0
5	2.911	4.161	1.250	Low Pulse Width	clk	inst2/clkdiv_1/count_1_s0
6	2.911	4.161	1.250	Low Pulse Width	clk	inst20/i4/count_1_s0
7	2.911	4.161	1.250	Low Pulse Width	clk	inst20/i4/count_2_s0
8	2.911	4.161	1.250	Low Pulse Width	clk	inst2/clkdiv_1/count_2_s0
9	2.911	4.161	1.250	Low Pulse Width	clk	inst20/i4/count_3_s0
10	2.911	4.161	1.250	Low Pulse Width	clk	inst20/i4/count_4_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.823
Data Arrival Time	9.907
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.808	1.362	tNET	FF	1	R9C14[1][A]	inst1/n51_s1/I0
9.907	1.099	tINS	FF	1	R9C14[1][A]	inst1/n51_s1/F
9.907	0.000	tNET	FF	1	R9C14[1][A]	inst1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C14[1][A]	inst1/count_4_s0/CLK
11.730	-0.400	tSu		1	R9C14[1][A]	inst1/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.119, 52.962%; route: 3.200, 41.144%; tC2Q: 0.458, 5.893%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack	1.824
Data Arrival Time	9.906
Data Required Time	11.730
From	inst1/count_13_s0
To	inst7/cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
7.390	1.470	tNET	FF	1	R11C11[3][A]	inst8/n16_s2/I1
8.016	0.626	tINS	FF	7	R11C11[3][A]	inst8/n16_s2/F
8.874	0.858	tNET	FF	1	R12C11[0][B]	inst7/n15_s1/I0
9.906	1.032	tINS	FF	1	R12C11[0][B]	inst7/n15_s1/F
9.906	0.000	tNET	FF	1	R12C11[0][B]	inst7/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R12C11[0][B]	inst7/cnt_1_s0/CLK
11.730	-0.400	tSu		1	R12C11[0][B]	inst7/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 42.643%; route: 4.002, 51.463%; tC2Q: 0.458, 5.894%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack	1.824
Data Arrival Time	9.906
Data Required Time	11.730
From	inst1/count_13_s0
To	inst7/cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
7.390	1.470	tNET	FF	1	R11C11[3][A]	inst8/n16_s2/I1
8.016	0.626	tINS	FF	7	R11C11[3][A]	inst8/n16_s2/F
8.874	0.858	tNET	FF	1	R12C11[0][A]	inst7/n14_s1/I2
9.906	1.032	tINS	FF	1	R12C11[0][A]	inst7/n14_s1/F
9.906	0.000	tNET	FF	1	R12C11[0][A]	inst7/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R12C11[0][A]	inst7/cnt_2_s0/CLK
11.730	-0.400	tSu		1	R12C11[0][A]	inst7/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 42.643%; route: 4.002, 51.463%; tC2Q: 0.458, 5.894%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack	1.919
Data Arrival Time	9.811
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.779	1.332	tNET	FF	1	R12C15[0][A]	inst1/n43_s1/I0
9.811	1.032	tINS	FF	1	R12C15[0][A]	inst1/n43_s1/F
9.811	0.000	tNET	FF	1	R12C15[0][A]	inst1/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R12C15[0][A]	inst1/count_12_s0/CLK
11.730	-0.400	tSu		1	R12C15[0][A]	inst1/count_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.052, 52.755%; route: 3.171, 41.278%; tC2Q: 0.458, 5.967%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack	1.930
Data Arrival Time	9.800
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.768	1.321	tNET	FF	1	R8C14[0][B]	inst1/n54_s1/I0
9.800	1.032	tINS	FF	1	R8C14[0][B]	inst1/n54_s1/F
9.800	0.000	tNET	FF	1	R8C14[0][B]	inst1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R8C14[0][B]	inst1/count_1_s0/CLK
11.730	-0.400	tSu		1	R8C14[0][B]	inst1/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.052, 52.832%; route: 3.159, 41.192%; tC2Q: 0.458, 5.976%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack	1.930
Data Arrival Time	9.800
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.768	1.321	tNET	FF	1	R8C14[0][A]	inst1/n53_s1/I2
9.800	1.032	tINS	FF	1	R8C14[0][A]	inst1/n53_s1/F
9.800	0.000	tNET	FF	1	R8C14[0][A]	inst1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R8C14[0][A]	inst1/count_2_s0/CLK
11.730	-0.400	tSu		1	R8C14[0][A]	inst1/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.052, 52.832%; route: 3.159, 41.192%; tC2Q: 0.458, 5.976%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack	2.100
Data Arrival Time	9.630
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.808	1.362	tNET	FF	1	R9C14[0][B]	inst1/n52_s1/I0
9.630	0.822	tINS	FF	1	R9C14[0][B]	inst1/n52_s1/F
9.630	0.000	tNET	FF	1	R9C14[0][B]	inst1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C14[0][B]	inst1/count_3_s0/CLK
11.730	-0.400	tSu		1	R9C14[0][B]	inst1/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.842, 51.225%; route: 3.200, 42.664%; tC2Q: 0.458, 6.111%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack	2.264
Data Arrival Time	9.466
Data Required Time	11.730
From	inst2/clkdiv_1/count_1_s0
To	inst2/clkdiv_1/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RR	4	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/Q
3.016	0.428	tNET	RR	1	R12C17[1][B]	inst2/clkdiv_1/n51_s2/I0
4.048	1.032	tINS	RF	5	R12C17[1][B]	inst2/clkdiv_1/n51_s2/F
4.871	0.823	tNET	FF	1	R12C16[2][A]	inst2/clkdiv_1/n47_s2/I3
5.693	0.822	tINS	FF	5	R12C16[2][A]	inst2/clkdiv_1/n47_s2/F
6.514	0.821	tNET	FF	1	R11C16[3][A]	inst2/clkdiv_1/n43_s2/I1
7.613	1.099	tINS	FF	3	R11C16[3][A]	inst2/clkdiv_1/n43_s2/F
8.434	0.821	tNET	FF	1	R9C17[0][A]	inst2/clkdiv_1/n42_s1/I1
9.466	1.032	tINS	FF	1	R9C17[0][A]	inst2/clkdiv_1/n42_s1/F
9.466	0.000	tNET	FF	1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0/CLK
11.730	-0.400	tSu		1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.985, 54.322%; route: 2.893, 39.430%; tC2Q: 0.458, 6.248%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack	2.296
Data Arrival Time	9.434
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.808	1.362	tNET	FF	1	R9C14[2][A]	inst1/n50_s1/I2
9.434	0.626	tINS	FF	1	R9C14[2][A]	inst1/n50_s1/F
9.434	0.000	tNET	FF	1	R9C14[2][A]	inst1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C14[2][A]	inst1/count_5_s0/CLK
11.730	-0.400	tSu		1	R9C14[2][A]	inst1/count_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.646, 49.916%; route: 3.200, 43.809%; tC2Q: 0.458, 6.275%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack	2.330
Data Arrival Time	9.400
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.301	0.854	tNET	FF	1	R11C15[2][A]	inst1/n39_s1/I2
9.400	1.099	tINS	FF	1	R11C15[2][A]	inst1/n39_s1/F
9.400	0.000	tNET	FF	1	R11C15[2][A]	inst1/count_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[2][A]	inst1/count_16_s0/CLK
11.730	-0.400	tSu		1	R11C15[2][A]	inst1/count_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.119, 56.657%; route: 2.693, 37.039%; tC2Q: 0.458, 6.304%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path11

Path Summary:

Slack	2.374
Data Arrival Time	9.356
Data Required Time	11.730
From	inst1/count_13_s0
To	inst7/cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
7.390	1.470	tNET	FF	1	R11C11[3][A]	inst8/n16_s2/I1
8.016	0.626	tINS	FF	7	R11C11[3][A]	inst8/n16_s2/F
8.534	0.517	tNET	FF	1	R9C11[0][A]	inst7/n16_s1/I1
9.356	0.822	tINS	FF	1	R9C11[0][A]	inst7/n16_s1/F
9.356	0.000	tNET	FF	1	R9C11[0][A]	inst7/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C11[0][A]	inst7/cnt_0_s0/CLK
11.730	-0.400	tSu		1	R9C11[0][A]	inst7/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.106, 42.986%; route: 3.661, 50.670%; tC2Q: 0.458, 6.343%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path12

Path Summary:

Slack	2.397
Data Arrival Time	9.333
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.301	0.854	tNET	FF	1	R11C13[1][A]	inst1/n45_s1/I2
9.333	1.032	tINS	FF	1	R11C13[1][A]	inst1/n45_s1/F
9.333	0.000	tNET	FF	1	R11C13[1][A]	inst1/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C13[1][A]	inst1/count_10_s0/CLK
11.730	-0.400	tSu		1	R11C13[1][A]	inst1/count_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.052, 56.254%; route: 2.693, 37.383%; tC2Q: 0.458, 6.363%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack	2.438
Data Arrival Time	9.649
Data Required Time	12.087
From	inst1/count_13_s0
To	inst6/cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
7.908	0.526	tNET	FF	1	R8C12[3][A]	inst5/clk1s_s1/I0
8.934	1.026	tINS	FR	4	R8C12[3][A]	inst5/clk1s_s1/F
9.649	0.715	tNET	RR	1	R9C12[1][A]	inst6/cnt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C12[1][A]	inst6/cnt_1_s0/CLK
12.087	-0.043	tSu		1	R9C12[1][A]	inst6/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.310, 44.021%; route: 3.751, 49.883%; tC2Q: 0.458, 6.096%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path14

Path Summary:

Slack	2.438
Data Arrival Time	9.649
Data Required Time	12.087
From	inst1/count_13_s0
To	inst6/cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
7.908	0.526	tNET	FF	1	R8C12[3][A]	inst5/clk1s_s1/I0
8.934	1.026	tINS	FR	4	R8C12[3][A]	inst5/clk1s_s1/F
9.649	0.715	tNET	RR	1	R9C12[0][A]	inst6/cnt_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C12[0][A]	inst6/cnt_2_s0/CLK
12.087	-0.043	tSu		1	R9C12[0][A]	inst6/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.310, 44.021%; route: 3.751, 49.883%; tC2Q: 0.458, 6.096%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack	2.443
Data Arrival Time	9.287
Data Required Time	11.730
From	inst1/count_13_s0
To	inst5/cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
8.255	0.872	tNET	FF	1	R9C13[2][A]	inst5/n14_s1/I1
9.287	1.032	tINS	FF	1	R9C13[2][A]	inst5/n14_s1/F
9.287	0.000	tNET	FF	1	R9C13[2][A]	inst5/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C13[2][A]	inst5/cnt_2_s0/CLK
11.730	-0.400	tSu		1	R9C13[2][A]	inst5/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 46.335%; route: 3.382, 47.260%; tC2Q: 0.458, 6.404%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path16

Path Summary:

Slack	2.459
Data Arrival Time	9.271
Data Required Time	11.730
From	inst1/count_13_s0
To	inst5/cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
8.239	0.856	tNET	FF	1	R8C12[0][A]	inst5/n13_s1/I0
9.271	1.032	tINS	FF	1	R8C12[0][A]	inst5/n13_s1/F
9.271	0.000	tNET	FF	1	R8C12[0][A]	inst5/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R8C12[0][A]	inst5/cnt_3_s0/CLK
11.730	-0.400	tSu		1	R8C12[0][A]	inst5/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 46.437%; route: 3.366, 47.144%; tC2Q: 0.458, 6.419%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack	2.485
Data Arrival Time	9.245
Data Required Time	11.730
From	inst1/count_13_s0
To	inst5/cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
8.213	0.831	tNET	FF	1	R9C13[0][A]	inst5/n15_s1/I1
9.245	1.032	tINS	FF	1	R9C13[0][A]	inst5/n15_s1/F
9.245	0.000	tNET	FF	1	R9C13[0][A]	inst5/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C13[0][A]	inst5/cnt_1_s0/CLK
11.730	-0.400	tSu		1	R9C13[0][A]	inst5/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 46.605%; route: 3.341, 46.954%; tC2Q: 0.458, 6.442%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack	2.485
Data Arrival Time	9.245
Data Required Time	11.730
From	inst1/count_13_s0
To	inst4/cnt_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
8.213	0.831	tNET	FF	1	R9C13[1][A]	inst4/n16_s3/I1
9.245	1.032	tINS	FF	1	R9C13[1][A]	inst4/n16_s3/F
9.245	0.000	tNET	FF	1	R9C13[1][A]	inst4/cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C13[1][A]	inst4/cnt_0_s1/CLK
11.730	-0.400	tSu		1	R9C13[1][A]	inst4/cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 46.605%; route: 3.341, 46.954%; tC2Q: 0.458, 6.442%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack	2.489
Data Arrival Time	9.241
Data Required Time	11.730
From	inst1/count_13_s0
To	inst4/cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
2.588	0.458	tC2Q	RF	4	R11C15[1][A]	inst1/count_13_s0/Q
3.426	0.837	tNET	FF	1	R11C14[1][B]	inst1/n39_s2/I0
4.458	1.032	tINS	FF	3	R11C14[1][B]	inst1/n39_s2/F
5.294	0.836	tNET	FF	1	R11C12[2][A]	inst4/clk10hz_s3/I3
5.920	0.626	tINS	FF	4	R11C12[2][A]	inst4/clk10hz_s3/F
6.756	0.836	tNET	FF	1	R9C12[1][B]	inst4/clk10hz_s/I3
7.382	0.626	tINS	FF	15	R9C12[1][B]	inst4/clk10hz_s/F
8.209	0.826	tNET	FF	1	R11C13[0][A]	inst4/n13_s1/I0
9.241	1.032	tINS	FF	1	R11C13[0][A]	inst4/n13_s1/F
9.241	0.000	tNET	FF	1	R11C13[0][A]	inst4/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C13[0][A]	inst4/cnt_3_s0/CLK
11.730	-0.400	tSu		1	R11C13[0][A]	inst4/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.316, 46.635%; route: 3.336, 46.920%; tC2Q: 0.458, 6.446%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path20

Path Summary:

Slack	2.602
Data Arrival Time	9.128
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.306	0.859	tNET	FF	1	R11C15[1][A]	inst1/n42_s1/I2
9.128	0.822	tINS	FF	1	R11C15[1][A]	inst1/n42_s1/F
9.128	0.000	tNET	FF	1	R11C15[1][A]	inst1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[1][A]	inst1/count_13_s0/CLK
11.730	-0.400	tSu		1	R11C15[1][A]	inst1/count_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.842, 54.904%; route: 2.697, 38.546%; tC2Q: 0.458, 6.550%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path21

Path Summary:

Slack	2.602
Data Arrival Time	9.128
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.306	0.859	tNET	FF	1	R11C15[0][A]	inst1/n41_s1/I0
9.128	0.822	tINS	FF	1	R11C15[0][A]	inst1/n41_s1/F
9.128	0.000	tNET	FF	1	R11C15[0][A]	inst1/count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C15[0][A]	inst1/count_14_s0/CLK
11.730	-0.400	tSu		1	R11C15[0][A]	inst1/count_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.842, 54.904%; route: 2.697, 38.546%; tC2Q: 0.458, 6.550%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path22

Path Summary:

Slack	2.614
Data Arrival Time	9.116
Data Required Time	11.730
From	inst1/count_7_s0
To	inst1/count_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.294	0.848	tNET	FF	1	R12C14[0][A]	inst1/n44_s1/I0
9.116	0.822	tINS	FF	1	R12C14[0][A]	inst1/n44_s1/F
9.116	0.000	tNET	FF	1	R12C14[0][A]	inst1/count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R12C14[0][A]	inst1/count_11_s0/CLK
11.730	-0.400	tSu		1	R12C14[0][A]	inst1/count_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.842, 54.993%; route: 2.686, 38.446%; tC2Q: 0.458, 6.560%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path23

Path Summary:

Slack	2.635
Data Arrival Time	9.095
Data Required Time	11.730
From	inst2/clkdiv_1/count_1_s0
To	inst2/clkdiv_1/count_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/CLK
2.588	0.458	tC2Q	RR	4	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/Q
3.016	0.428	tNET	RR	1	R12C17[1][B]	inst2/clkdiv_1/n51_s2/I0
4.048	1.032	tINS	RF	5	R12C17[1][B]	inst2/clkdiv_1/n51_s2/F
4.871	0.823	tNET	FF	1	R12C16[2][A]	inst2/clkdiv_1/n47_s2/I3
5.693	0.822	tINS	FF	5	R12C16[2][A]	inst2/clkdiv_1/n47_s2/F
6.514	0.821	tNET	FF	1	R11C16[3][A]	inst2/clkdiv_1/n43_s2/I1
7.575	1.061	tINS	FR	3	R11C16[3][A]	inst2/clkdiv_1/n43_s2/F
7.996	0.421	tNET	RR	1	R11C17[2][A]	inst2/clkdiv_1/n41_s1/I1
9.095	1.099	tINS	RF	1	R11C17[2][A]	inst2/clkdiv_1/n41_s1/F
9.095	0.000	tNET	FF	1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0/CLK
11.730	-0.400	tSu		1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.014, 57.635%; route: 2.492, 35.784%; tC2Q: 0.458, 6.581%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path24

Path Summary:

Slack	2.644
Data Arrival Time	9.443
Data Required Time	12.087
From	inst1/count_7_s0
To	inst8/cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.290	0.843	tNET	FF	1	R11C11[1][B]	inst7/clk1m_s/I0
9.092	0.802	tINS	FR	28	R11C11[1][B]	inst7/clk1m_s/F
9.443	0.351	tNET	RR	1	R11C11[0][A]	inst8/cnt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[0][A]	inst8/cnt_3_s0/CLK
12.087	-0.043	tSu		1	R11C11[0][A]	inst8/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.822, 52.262%; route: 3.033, 41.470%; tC2Q: 0.458, 6.267%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path25

Path Summary:

Slack	2.644
Data Arrival Time	9.443
Data Required Time	12.087
From	inst1/count_7_s0
To	inst8/cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C14[0][B]	inst1/count_7_s0/CLK
2.588	0.458	tC2Q	RF	5	R11C14[0][B]	inst1/count_7_s0/Q
3.420	0.832	tNET	FF	1	R9C14[1][B]	inst4/clk10hz_s0/I2
4.242	0.822	tINS	FF	4	R9C14[1][B]	inst4/clk10hz_s0/F
4.748	0.506	tNET	FF	1	R9C12[2][B]	inst6/clk10s_s0/I1
5.847	1.099	tINS	FF	3	R9C12[2][B]	inst6/clk10s_s0/F
6.348	0.501	tNET	FF	1	R11C12[3][B]	inst4/active_s1/I3
7.447	1.099	tINS	FF	20	R11C12[3][B]	inst4/active_s1/F
8.290	0.843	tNET	FF	1	R11C11[1][B]	inst7/clk1m_s/I0
9.092	0.802	tINS	FR	28	R11C11[1][B]	inst7/clk1m_s/F
9.443	0.351	tNET	RR	1	R11C11[0][B]	inst8/cnt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	64	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[0][B]	inst8/cnt_0_s0/CLK
12.087	-0.043	tSu		1	R11C11[0][B]	inst8/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 3.822, 52.262%; route: 3.033, 41.470%; tC2Q: 0.458, 6.267%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.952
Data Arrival Time	0.729
Data Required Time	1.681
From	inst2/clkdiv_1/n49_s1
To	inst2/clkdiv_1/count_6_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
0.005	0.005	tNET	RR	1	R11C16[0][A]	inst2/clkdiv_1/n49_s1/I0
0.729	0.724	tINS	RR	1	R11C16[0][A]	inst2/clkdiv_1/n49_s1/F
0.729	0.000	tNET	RR	1	R11C16[0][A]	inst2/clkdiv_1/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C16[0][A]	inst2/clkdiv_1/count_6_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_6_s0
1.681	0.000	tHld		1	R11C16[0][A]	inst2/clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 99.347%; route: 0.000, 0.000%; tC2Q: 0.005, 0.653%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack	-0.952
Data Arrival Time	0.729
Data Required Time	1.681
From	inst2/clkdiv_1/n48_s1
To	inst2/clkdiv_1/count_7_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
0.005	0.005	tNET	RR	1	R11C16[0][B]	inst2/clkdiv_1/n48_s1/I2
0.729	0.724	tINS	RR	1	R11C16[0][B]	inst2/clkdiv_1/n48_s1/F
0.729	0.000	tNET	RR	1	R11C16[0][B]	inst2/clkdiv_1/count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C16[0][B]	inst2/clkdiv_1/count_7_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_7_s0
1.681	0.000	tHld		1	R11C16[0][B]	inst2/clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 99.347%; route: 0.000, 0.000%; tC2Q: 0.005, 0.653%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack	-0.555
Data Arrival Time	1.140
Data Required Time	1.696
From	inst20/i4/count_0_s0
To	inst20/i4/count_0_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.140	1.140	tNET	RR	1	R12C9[0][A]	inst20/i4/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C9[0][A]	inst20/i4/count_0_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_0_s0
1.696	0.015	tHld		1	R12C9[0][A]	inst20/i4/count_0_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.140, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack	-0.552
Data Arrival Time	1.144
Data Required Time	1.696
From	inst20/i4/count_7_s0
To	inst20/i4/count_7_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.144	1.144	tNET	RR	1	R8C9[0][A]	inst20/i4/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C9[0][A]	inst20/i4/count_7_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_7_s0
1.696	0.015	tHld		1	R8C9[0][A]	inst20/i4/count_7_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.144, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack	-0.552
Data Arrival Time	1.144
Data Required Time	1.696
From	inst20/i4/count_8_s0
To	inst20/i4/count_8_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.144	1.144	tNET	RR	1	R8C9[0][B]	inst20/i4/count_8_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C9[0][B]	inst20/i4/count_8_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_8_s0
1.696	0.015	tHld		1	R8C9[0][B]	inst20/i4/count_8_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.144, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack	-0.552
Data Arrival Time	1.144
Data Required Time	1.696
From	inst20/i4/count_9_s0
To	inst20/i4/count_9_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.144	1.144	tNET	RR	1	R8C9[1][A]	inst20/i4/count_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C9[1][A]	inst20/i4/count_9_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_9_s0
1.696	0.015	tHld		1	R8C9[1][A]	inst20/i4/count_9_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.144, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack	-0.552
Data Arrival Time	1.144
Data Required Time	1.696
From	inst20/i4/count_10_s0
To	inst20/i4/count_10_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.144	1.144	tNET	RR	1	R8C9[1][B]	inst20/i4/count_10_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C9[1][B]	inst20/i4/count_10_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_10_s0
1.696	0.015	tHld		1	R8C9[1][B]	inst20/i4/count_10_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.144, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_1_s0
To	inst20/i4/count_1_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[0][A]	inst20/i4/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[0][A]	inst20/i4/count_1_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_1_s0
1.696	0.015	tHld		1	R8C8[0][A]	inst20/i4/count_1_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_2_s0
To	inst20/i4/count_2_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[0][B]	inst20/i4/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[0][B]	inst20/i4/count_2_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_2_s0
1.696	0.015	tHld		1	R8C8[0][B]	inst20/i4/count_2_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_3_s0
To	inst20/i4/count_3_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[1][A]	inst20/i4/count_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[1][A]	inst20/i4/count_3_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_3_s0
1.696	0.015	tHld		1	R8C8[1][A]	inst20/i4/count_3_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_4_s0
To	inst20/i4/count_4_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[1][B]	inst20/i4/count_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[1][B]	inst20/i4/count_4_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_4_s0
1.696	0.015	tHld		1	R8C8[1][B]	inst20/i4/count_4_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_5_s0
To	inst20/i4/count_5_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[2][A]	inst20/i4/count_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[2][A]	inst20/i4/count_5_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_5_s0
1.696	0.015	tHld		1	R8C8[2][A]	inst20/i4/count_5_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack	-0.548
Data Arrival Time	1.148
Data Required Time	1.696
From	inst20/i4/count_6_s0
To	inst20/i4/count_6_s0
Launch Clk	inst20/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst20/clk10KHz
0.000	0.000	tCL	RR	14	R8C8[3][B]	inst20/i4/clk10KHz_s/F
1.148	1.148	tNET	RR	1	R8C8[2][B]	inst20/i4/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R8C8[2][B]	inst20/i4/count_6_s0/CLK
1.681	0.030	tUnc				inst20/i4/count_6_s0
1.696	0.015	tHld		1	R8C8[2][B]	inst20/i4/count_6_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.148, 100.000%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path14

Path Summary:

Slack	-0.143
Data Arrival Time	1.538
Data Required Time	1.681
From	inst2/clkdiv_1/n53_s1
To	inst2/clkdiv_1/count_2_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.166	1.166	tNET	RR	1	R12C17[0][B]	inst2/clkdiv_1/n53_s1/I2
1.538	0.372	tINS	RF	1	R12C17[0][B]	inst2/clkdiv_1/n53_s1/F
1.538	0.000	tNET	FF	1	R12C17[0][B]	inst2/clkdiv_1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C17[0][B]	inst2/clkdiv_1/count_2_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_2_s0
1.681	0.000	tHld		1	R12C17[0][B]	inst2/clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 24.185%; route: 0.000, 0.000%; tC2Q: 1.166, 75.815%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path15

Path Summary:

Slack	-0.141
Data Arrival Time	1.540
Data Required Time	1.681
From	inst2/clkdiv_1/n55_s1
To	inst2/clkdiv_1/count_0_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.168	1.168	tNET	RR	1	R11C17[0][B]	inst2/clkdiv_1/n55_s1/I1
1.540	0.372	tINS	RF	1	R11C17[0][B]	inst2/clkdiv_1/n55_s1/F
1.540	0.000	tNET	FF	1	R11C17[0][B]	inst2/clkdiv_1/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C17[0][B]	inst2/clkdiv_1/count_0_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_0_s0
1.681	0.000	tHld		1	R11C17[0][B]	inst2/clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 24.162%; route: 0.000, 0.000%; tC2Q: 1.168, 75.838%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path16

Path Summary:

Slack	-0.141
Data Arrival Time	1.540
Data Required Time	1.681
From	inst2/clkdiv_1/n46_s1
To	inst2/clkdiv_1/count_9_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.168	1.168	tNET	RR	1	R12C17[2][A]	inst2/clkdiv_1/n46_s1/I2
1.540	0.372	tINS	RF	1	R12C17[2][A]	inst2/clkdiv_1/n46_s1/F
1.540	0.000	tNET	FF	1	R12C17[2][A]	inst2/clkdiv_1/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C17[2][A]	inst2/clkdiv_1/count_9_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_9_s0
1.681	0.000	tHld		1	R12C17[2][A]	inst2/clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 24.162%; route: 0.000, 0.000%; tC2Q: 1.168, 75.838%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path17

Path Summary:

Slack	-0.141
Data Arrival Time	1.540
Data Required Time	1.681
From	inst2/clkdiv_1/n43_s1
To	inst2/clkdiv_1/count_12_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.168	1.168	tNET	RR	1	R11C17[1][B]	inst2/clkdiv_1/n43_s1/I0
1.540	0.372	tINS	RF	1	R11C17[1][B]	inst2/clkdiv_1/n43_s1/F
1.540	0.000	tNET	FF	1	R11C17[1][B]	inst2/clkdiv_1/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C17[1][B]	inst2/clkdiv_1/count_12_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_12_s0
1.681	0.000	tHld		1	R11C17[1][B]	inst2/clkdiv_1/count_12_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 24.162%; route: 0.000, 0.000%; tC2Q: 1.168, 75.838%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack	-0.140
Data Arrival Time	1.541
Data Required Time	1.681
From	inst2/clkdiv_1/n41_s1
To	inst2/clkdiv_1/count_14_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.169	1.169	tNET	RR	1	R11C17[2][A]	inst2/clkdiv_1/n41_s1/I3
1.541	0.372	tINS	RF	1	R11C17[2][A]	inst2/clkdiv_1/n41_s1/F
1.541	0.000	tNET	FF	1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_14_s0
1.681	0.000	tHld		1	R11C17[2][A]	inst2/clkdiv_1/count_14_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 24.139%; route: 0.000, 0.000%; tC2Q: 1.169, 75.861%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack	0.209
Data Arrival Time	1.890
Data Required Time	1.681
From	inst2/clkdiv_1/n47_s1
To	inst2/clkdiv_1/count_8_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.166	1.166	tNET	RR	1	R9C16[0][A]	inst2/clkdiv_1/n47_s1/I0
1.890	0.724	tINS	RR	1	R9C16[0][A]	inst2/clkdiv_1/n47_s1/F
1.890	0.000	tNET	RR	1	R9C16[0][A]	inst2/clkdiv_1/count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C16[0][A]	inst2/clkdiv_1/count_8_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_8_s0
1.681	0.000	tHld		1	R9C16[0][A]	inst2/clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 38.303%; route: 0.000, 0.000%; tC2Q: 1.166, 61.697%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path20

Path Summary:

Slack	0.209
Data Arrival Time	1.890
Data Required Time	1.681
From	inst2/clkdiv_1/n42_s1
To	inst2/clkdiv_1/count_13_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.166	1.166	tNET	RR	1	R9C17[0][A]	inst2/clkdiv_1/n42_s1/I2
1.890	0.724	tINS	RR	1	R9C17[0][A]	inst2/clkdiv_1/n42_s1/F
1.890	0.000	tNET	RR	1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_13_s0
1.681	0.000	tHld		1	R9C17[0][A]	inst2/clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 38.303%; route: 0.000, 0.000%; tC2Q: 1.166, 61.697%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path21

Path Summary:

Slack	0.211
Data Arrival Time	1.892
Data Required Time	1.681
From	inst2/clkdiv_1/n52_s1
To	inst2/clkdiv_1/count_3_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.168	1.168	tNET	RR	1	R12C17[0][A]	inst2/clkdiv_1/n52_s1/I0
1.892	0.724	tINS	RR	1	R12C17[0][A]	inst2/clkdiv_1/n52_s1/F
1.892	0.000	tNET	RR	1	R12C17[0][A]	inst2/clkdiv_1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C17[0][A]	inst2/clkdiv_1/count_3_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_3_s0
1.681	0.000	tHld		1	R12C17[0][A]	inst2/clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 38.274%; route: 0.000, 0.000%; tC2Q: 1.168, 61.726%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path22

Path Summary:

Slack	0.212
Data Arrival Time	1.893
Data Required Time	1.681
From	inst2/clkdiv_1/n54_s1
To	inst2/clkdiv_1/count_1_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.169	1.169	tNET	RR	1	R11C17[0][A]	inst2/clkdiv_1/n54_s1/I0
1.893	0.724	tINS	RR	1	R11C17[0][A]	inst2/clkdiv_1/n54_s1/F
1.893	0.000	tNET	RR	1	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C17[0][A]	inst2/clkdiv_1/count_1_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_1_s0
1.681	0.000	tHld		1	R11C17[0][A]	inst2/clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 38.244%; route: 0.000, 0.000%; tC2Q: 1.169, 61.756%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path23

Path Summary:

Slack	0.212
Data Arrival Time	1.893
Data Required Time	1.681
From	inst2/clkdiv_1/n45_s1
To	inst2/clkdiv_1/count_10_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.169	1.169	tNET	RR	1	R11C17[1][A]	inst2/clkdiv_1/n45_s1/I0
1.893	0.724	tINS	RR	1	R11C17[1][A]	inst2/clkdiv_1/n45_s1/F
1.893	0.000	tNET	RR	1	R11C17[1][A]	inst2/clkdiv_1/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C17[1][A]	inst2/clkdiv_1/count_10_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_10_s0
1.681	0.000	tHld		1	R11C17[1][A]	inst2/clkdiv_1/count_10_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 38.244%; route: 0.000, 0.000%; tC2Q: 1.169, 61.756%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path24

Path Summary:

Slack	0.214
Data Arrival Time	1.895
Data Required Time	1.681
From	inst2/clkdiv_1/n51_s1
To	inst2/clkdiv_1/count_4_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.169	1.169	tNET	RR	1	R12C16[1][B]	inst2/clkdiv_1/n51_s1/I0
1.895	0.726	tINS	RR	1	R12C16[1][B]	inst2/clkdiv_1/n51_s1/F
1.895	0.000	tNET	RR	1	R12C16[1][B]	inst2/clkdiv_1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C16[1][B]	inst2/clkdiv_1/count_4_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_4_s0
1.681	0.000	tHld		1	R12C16[1][B]	inst2/clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.726, 38.309%; route: 0.000, 0.000%; tC2Q: 1.169, 61.691%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path25

Path Summary:

Slack	0.214
Data Arrival Time	1.895
Data Required Time	1.681
From	inst2/clkdiv_1/n50_s1
To	inst2/clkdiv_1/count_5_s0
Launch Clk	inst2/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst2/clk400Hz
0.000	0.000	tCL	RR	19	R11C16[1][B]	inst2/clkdiv_1/clk400Hz_s/F
1.169	1.169	tNET	RR	1	R12C16[0][A]	inst2/clkdiv_1/n50_s1/I2
1.895	0.726	tINS	RR	1	R12C16[0][A]	inst2/clkdiv_1/n50_s1/F
1.895	0.000	tNET	RR	1	R12C16[0][A]	inst2/clkdiv_1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	64	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C16[0][A]	inst2/clkdiv_1/count_5_s0/CLK
1.681	0.030	tUnc				inst2/clkdiv_1/count_5_s0
1.681	0.000	tHld		1	R12C16[0][A]	inst2/clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	1.651
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.726, 38.309%; route: 0.000, 0.000%; tC2Q: 1.169, 61.691%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/count_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst1/count_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst1/count_16_s0/CLK

MPW2

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/count_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst1/count_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst1/count_14_s0/CLK

MPW3

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/count_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst1/count_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst1/count_10_s0/CLK

MPW4

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst1/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst1/count_2_s0/CLK

MPW5

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst2/clkdiv_1/count_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst2/clkdiv_1/count_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst2/clkdiv_1/count_1_s0/CLK

MPW6

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst20/i4/count_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst20/i4/count_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst20/i4/count_1_s0/CLK

MPW7

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst20/i4/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst20/i4/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst20/i4/count_2_s0/CLK

MPW8

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst2/clkdiv_1/count_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst2/clkdiv_1/count_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst2/clkdiv_1/count_2_s0/CLK

MPW9

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst20/i4/count_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst20/i4/count_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst20/i4/count_3_s0/CLK

MPW10

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst20/i4/count_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	inst20/i4/count_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	inst20/i4/count_4_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
64	clk_d	1.823	1.505
28	clk1m	2.644	0.368
20	active_4	1.823	1.362
20	seg_no[1]	7.815	0.870
19	clk400Hz	3.929	1.672
15	clk10hz	2.438	0.872
14	clk10KHz	7.761	1.982
14	cnt10hz[0]	3.196	1.971
12	cnt100hz[0]	2.394	1.645
12	cnt1m[3]	7.656	1.464

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C12	50.00%
R11C12	37.50%
R8C12	36.11%
R9C13	34.72%
R8C9	29.17%
R9C9	29.17%
R11C14	29.17%
R9C14	27.78%
R9C11	25.00%
R11C11	23.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command