Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Workspace\uart\src\clkdiv.v
C:\Gowin\Workspace\uart\src\debounce.v
C:\Gowin\Workspace\uart\src\drv7seg.v
C:\Gowin\Workspace\uart\src\mux7seg.v
C:\Gowin\Workspace\uart\src\rx.v
C:\Gowin\Workspace\uart\src\test_uart.v
C:\Gowin\Workspace\uart\src\toggle.v
C:\Gowin\Workspace\uart\src\tx.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 15:15:04 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_uart
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.209s, Peak memory usage = 63.840MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 63.840MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 63.840MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 63.840MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 63.840MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 63.840MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.840MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 63.840MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 63.840MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 63.840MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 63.840MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.646s, Peak memory usage = 78.871MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 78.871MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 78.871MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 78.871MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 33
I/O Buf 33
    IBUF 12
    OBUF 21
Register 110
    DFF 3
    DFFE 13
    DFFR 11
    DFFP 2
    DFFPE 1
    DFFC 45
    DFFCE 35
LUT 184
    LUT2 35
    LUT3 68
    LUT4 81
ALU 10
    ALU 10
INV 6
    INV 6

Resource Utilization Summary

Resource Usage Utilization
Logic 200(190 LUTs, 10 ALUs) / 4608 4%
Register 110 / 3756 3%
  --Register as Latch 0 / 3756 0%
  --Register as FF 110 / 3756 3%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
clk400Hz Base 10.000 100.0 0.000 5.000 debounce_1/clkdiv_1/clk400Hz_s/F
clk9600hz Base 10.000 100.0 0.000 5.000 toggle_1/out_s0/Q
clk9600x2hz Base 10.000 100.0 0.000 5.000 toggle_2/out_s0/Q
clk10KHz Base 10.000 100.0 0.000 5.000 mux7seg_1/i4/clk10KHz_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 164.6(MHz) 4 TOP
2 clk400Hz 100.0(MHz) 747.2(MHz) 1 TOP
3 clk9600hz 100.0(MHz) 164.6(MHz) 4 TOP
4 clk9600x2hz 100.0(MHz) 172.5(MHz) 4 TOP
5 clk10KHz 100.0(MHz) 342.8(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.925
Data Arrival Time 6.038
Data Required Time 9.963
From tx_1/mask_5_s0
To tx_1/txd_s0
Launch Clk clk9600hz[R]
Latch Clk clk9600hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk9600hz
0.000 0.000 tCL RR 22 toggle_1/out_s0/Q
0.363 0.363 tNET RR 1 tx_1/mask_5_s0/CLK
0.821 0.458 tC2Q RF 3 tx_1/mask_5_s0/Q
1.301 0.480 tNET FF 1 tx_1/state_0_s4/I1
2.400 1.099 tINS FF 2 tx_1/state_0_s4/F
2.880 0.480 tNET FF 1 tx_1/mask_7_s4/I1
3.979 1.099 tINS FF 2 tx_1/mask_7_s4/F
4.459 0.480 tNET FF 1 tx_1/n50_s4/I1
5.558 1.099 tINS FF 1 tx_1/n50_s4/F
6.038 0.480 tNET FF 1 tx_1/txd_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk9600hz
10.000 0.000 tCL RR 22 toggle_1/out_s0/Q
10.363 0.363 tNET RR 1 tx_1/txd_s0/CLK
9.963 -0.400 tSu 1 tx_1/txd_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 3.297, 58.093%; route: 1.920, 33.831%; tC2Q: 0.458, 8.076%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 2

Path Summary:
Slack 3.925
Data Arrival Time 7.020
Data Required Time 10.945
From debounce_1/clkdiv_1/count_0_s0
To debounce_1/clkdiv_1/count_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 49 clk_ibuf/O
1.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 5 debounce_1/clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 debounce_1/clkdiv_1/n51_s2/I1
3.382 1.099 tINS FF 10 debounce_1/clkdiv_1/n51_s2/F
3.862 0.480 tNET FF 1 debounce_1/clkdiv_1/n48_s2/I1
4.961 1.099 tINS FF 1 debounce_1/clkdiv_1/n48_s2/F
5.441 0.480 tNET FF 1 debounce_1/clkdiv_1/n48_s1/I1
6.540 1.099 tINS FF 1 debounce_1/clkdiv_1/n48_s1/F
7.020 0.480 tNET FF 1 debounce_1/clkdiv_1/count_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 49 clk_ibuf/O
11.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_7_s0/CLK
10.945 -0.400 tSu 1 debounce_1/clkdiv_1/count_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.297, 58.093%; route: 1.920, 33.831%; tC2Q: 0.458, 8.076%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 3.925
Data Arrival Time 7.020
Data Required Time 10.945
From clkdiv_2/count_3_s0
To clkdiv_2/count_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 49 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_2/count_3_s0/CLK
1.803 0.458 tC2Q RF 4 clkdiv_2/count_3_s0/Q
2.283 0.480 tNET FF 1 clkdiv_2/tc9600x2hz_s0/I1
3.382 1.099 tINS FF 3 clkdiv_2/tc9600x2hz_s0/F
3.862 0.480 tNET FF 1 clkdiv_2/n48_s2/I1
4.961 1.099 tINS FF 2 clkdiv_2/n48_s2/F
5.441 0.480 tNET FF 1 clkdiv_2/n47_s1/I1
6.540 1.099 tINS FF 1 clkdiv_2/n47_s1/F
7.020 0.480 tNET FF 1 clkdiv_2/count_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 49 clk_ibuf/O
11.345 0.363 tNET RR 1 clkdiv_2/count_8_s0/CLK
10.945 -0.400 tSu 1 clkdiv_2/count_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.297, 58.093%; route: 1.920, 33.831%; tC2Q: 0.458, 8.076%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 3.992
Data Arrival Time 6.953
Data Required Time 10.945
From debounce_1/clkdiv_1/count_8_s0
To debounce_1/clkdiv_1/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 49 clk_ibuf/O
1.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_8_s0/CLK
1.803 0.458 tC2Q RF 6 debounce_1/clkdiv_1/count_8_s0/Q
2.283 0.480 tNET FF 1 debounce_1/clkdiv_1/clk400Hz_s3/I1
3.382 1.099 tINS FF 1 debounce_1/clkdiv_1/clk400Hz_s3/F
3.862 0.480 tNET FF 1 debounce_1/clkdiv_1/clk400Hz_s5/I0
4.894 1.032 tINS FF 16 debounce_1/clkdiv_1/clk400Hz_s5/F
5.374 0.480 tNET FF 1 debounce_1/clkdiv_1/n55_s1/I1
6.473 1.099 tINS FF 1 debounce_1/clkdiv_1/n55_s1/F
6.953 0.480 tNET FF 1 debounce_1/clkdiv_1/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 49 clk_ibuf/O
11.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_0_s0/CLK
10.945 -0.400 tSu 1 debounce_1/clkdiv_1/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.230, 57.593%; route: 1.920, 34.235%; tC2Q: 0.458, 8.172%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 3.992
Data Arrival Time 6.953
Data Required Time 10.945
From debounce_1/clkdiv_1/count_8_s0
To debounce_1/clkdiv_1/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 49 clk_ibuf/O
1.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_8_s0/CLK
1.803 0.458 tC2Q RF 6 debounce_1/clkdiv_1/count_8_s0/Q
2.283 0.480 tNET FF 1 debounce_1/clkdiv_1/clk400Hz_s3/I1
3.382 1.099 tINS FF 1 debounce_1/clkdiv_1/clk400Hz_s3/F
3.862 0.480 tNET FF 1 debounce_1/clkdiv_1/clk400Hz_s5/I0
4.894 1.032 tINS FF 16 debounce_1/clkdiv_1/clk400Hz_s5/F
5.374 0.480 tNET FF 1 debounce_1/clkdiv_1/n54_s1/I1
6.473 1.099 tINS FF 1 debounce_1/clkdiv_1/n54_s1/F
6.953 0.480 tNET FF 1 debounce_1/clkdiv_1/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 49 clk_ibuf/O
11.345 0.363 tNET RR 1 debounce_1/clkdiv_1/count_1_s0/CLK
10.945 -0.400 tSu 1 debounce_1/clkdiv_1/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.230, 57.593%; route: 1.920, 34.235%; tC2Q: 0.458, 8.172%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%