Timing Messages

Report Title Gowin Timing Analysis Report
Design File C:\Gowin\Workspace\uart\impl\gwsynthesis\uart.vg
Physical Constraints File C:\Gowin\Workspace\uart\src\uart.cst
Timing Constraint File ---
GOWIN version V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 15:20:17 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 2.375V 85C
Hold Delay Model Fast 2.625V 0C
Numbers of Paths Analyzed 400
Numbers of Endpoints Analyzed 274
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 13

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
debounce_1/clk400Hz Base 10.000 100.000 0.000 5.000 debounce_1/clkdiv_1/clk400Hz_s/F
clk9600hz Base 10.000 100.000 0.000 5.000 toggle_1/out_s0/Q
clk9600x2hz Base 10.000 100.000 0.000 5.000 toggle_2/out_s0/Q
mux7seg_1/clk10KHz Base 10.000 100.000 0.000 5.000 mux7seg_1/i4/clk10KHz_s/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 160.883(MHz) 4 TOP
2 debounce_1/clk400Hz 100.000(MHz) 321.309(MHz) 1 TOP
3 clk9600hz 100.000(MHz) 151.619(MHz) 4 TOP
4 clk9600x2hz 100.000(MHz) 124.505(MHz) 3 TOP
5 mux7seg_1/clk10KHz 100.000(MHz) 446.598(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
debounce_1/clk400Hz Setup 0.000 0
debounce_1/clk400Hz Hold 0.000 0
clk9600hz Setup 0.000 0
clk9600hz Hold 0.000 0
clk9600x2hz Setup 0.000 0
clk9600x2hz Hold 0.000 0
mux7seg_1/clk10KHz Setup 0.000 0
mux7seg_1/clk10KHz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.968 rx_1/state_0_s9/Q rx_1/ready_s1/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 7.988
2 2.686 rx_1/state_0_s9/Q rx_1/state_1_s3/D clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.914
3 2.686 rx_1/state_0_s9/Q rx_1/state_0_s9/D clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.914
4 3.405 tx_1/buffer_6_s0/Q tx_1/txd_s0/D clk9600hz:[R] clk9600hz:[R] 10.000 0.709 5.486
5 3.501 rx_1/count_0_s0/Q rx_1/ready_s1/D clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.099
6 3.695 rx_1/state_0_s9/Q rx_1/mask_1_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.262
7 3.695 rx_1/state_0_s9/Q rx_1/mask_2_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.262
8 3.695 rx_1/state_0_s9/Q rx_1/mask_3_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.262
9 3.695 rx_1/state_0_s9/Q rx_1/mask_4_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.262
10 3.699 rx_1/state_0_s9/Q rx_1/mask_5_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.257
11 3.699 rx_1/state_0_s9/Q rx_1/mask_6_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.257
12 3.726 rx_1/state_0_s9/Q rx_1/count_0_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.230
13 3.726 rx_1/state_0_s9/Q rx_1/count_1_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.230
14 3.784 debounce_1/clkdiv_1/count_1_s0/Q debounce_1/clkdiv_1/count_2_s0/D clk:[R] clk:[R] 10.000 0.000 5.816
15 3.841 debounce_1/key_n_0_s0/Q tx_1/state_1_s1/CE debounce_1/clk400Hz:[R] clk9600hz:[R] 10.000 -0.910 6.996
16 3.864 debounce_1/clkdiv_1/count_8_s0/Q debounce_1/clkdiv_1/count_11_s0/D clk:[R] clk:[R] 10.000 0.000 5.736
17 3.874 debounce_1/clkdiv_1/count_1_s0/Q debounce_1/clkdiv_1/count_12_s0/D clk:[R] clk:[R] 10.000 0.000 5.726
18 3.874 debounce_1/clkdiv_1/count_1_s0/Q debounce_1/clkdiv_1/count_13_s0/D clk:[R] clk:[R] 10.000 0.000 5.726
19 3.876 debounce_1/clkdiv_1/count_8_s0/Q debounce_1/clkdiv_1/count_4_s0/D clk:[R] clk:[R] 10.000 0.000 5.724
20 3.876 debounce_1/clkdiv_1/count_8_s0/Q debounce_1/clkdiv_1/count_5_s0/D clk:[R] clk:[R] 10.000 0.000 5.724
21 3.881 rx_1/state_0_s9/Q rx_1/work_3_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.076
22 3.881 rx_1/state_0_s9/Q rx_1/work_7_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.076
23 3.916 rx_1/state_0_s9/Q rx_1/work_5_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.041
24 3.916 rx_1/state_0_s9/Q rx_1/work_6_s0/CE clk9600x2hz:[R] clk9600x2hz:[R] 10.000 0.000 6.041
25 4.003 debounce_1/key_n_0_s0/Q tx_1/busy_s1/CE debounce_1/clk400Hz:[R] clk9600hz:[R] 10.000 -0.910 6.834

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -1.306 toggle_2/n9_s0/I2 toggle_2/out_s0/D clk9600x2hz:[R] clk:[R] 0.000 -1.651 0.374
2 -1.306 toggle_1/n9_s0/I2 toggle_1/out_s0/D clk9600hz:[R] clk:[R] 0.000 -1.651 0.374
3 -0.250 mux7seg_1/i4/count_0_s0/RESET mux7seg_1/i4/count_0_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.446
4 -0.246 mux7seg_1/i4/count_7_s0/RESET mux7seg_1/i4/count_7_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.450
5 -0.246 mux7seg_1/i4/count_8_s0/RESET mux7seg_1/i4/count_8_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.450
6 -0.246 mux7seg_1/i4/count_9_s0/RESET mux7seg_1/i4/count_9_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.450
7 -0.246 mux7seg_1/i4/count_10_s0/RESET mux7seg_1/i4/count_10_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.450
8 -0.242 mux7seg_1/i4/count_1_s0/RESET mux7seg_1/i4/count_1_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
9 -0.242 mux7seg_1/i4/count_2_s0/RESET mux7seg_1/i4/count_2_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
10 -0.242 mux7seg_1/i4/count_3_s0/RESET mux7seg_1/i4/count_3_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
11 -0.242 mux7seg_1/i4/count_4_s0/RESET mux7seg_1/i4/count_4_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
12 -0.242 mux7seg_1/i4/count_5_s0/RESET mux7seg_1/i4/count_5_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
13 -0.242 mux7seg_1/i4/count_6_s0/RESET mux7seg_1/i4/count_6_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.453
14 0.708 mux7seg_1/i4/count_0_s0/Q mux7seg_1/i4/count_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
15 0.708 rx_1/count_1_s0/Q rx_1/count_1_s0/D clk9600x2hz:[R] clk9600x2hz:[R] 0.000 0.000 0.708
16 0.708 rx_1/count_2_s0/Q rx_1/count_2_s0/D clk9600x2hz:[R] clk9600x2hz:[R] 0.000 0.000 0.708
17 0.708 debounce_1/clkdiv_1/count_2_s0/Q debounce_1/clkdiv_1/count_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
18 0.708 debounce_1/clkdiv_1/count_12_s0/Q debounce_1/clkdiv_1/count_12_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
19 0.708 clkdiv_2/count_1_s0/Q clkdiv_2/count_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
20 0.708 clkdiv_2/count_5_s0/Q clkdiv_2/count_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
21 0.708 clkdiv_1/count_3_s0/Q clkdiv_1/count_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
22 0.709 mux7seg_1/seg_no_1_s0/Q mux7seg_1/seg_no_1_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 0.000 0.000 0.709
23 0.709 debounce_1/clkdiv_1/count_4_s0/Q debounce_1/clkdiv_1/count_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
24 0.709 clkdiv_2/count_3_s0/Q clkdiv_2/count_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
25 0.709 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.675 3.925 1.250 Low Pulse Width clk9600hz tx_1/buffer_6_s0
2 2.675 3.925 1.250 Low Pulse Width clk9600hz tx_1/buffer_5_s0
3 2.911 4.161 1.250 Low Pulse Width clk clkdiv_1/count_3_s0
4 2.911 4.161 1.250 Low Pulse Width clk clkdiv_2/count_6_s0
5 2.911 4.161 1.250 Low Pulse Width clk debounce_1/clkdiv_1/count_7_s0
6 2.911 4.161 1.250 Low Pulse Width clk debounce_1/clkdiv_1/count_8_s0
7 2.911 4.161 1.250 Low Pulse Width clk clkdiv_2/count_7_s0
8 2.911 4.161 1.250 Low Pulse Width clk debounce_1/clkdiv_1/count_9_s0
9 2.911 4.161 1.250 Low Pulse Width clk debounce_1/clkdiv_1/count_10_s0
10 2.911 4.161 1.250 Low Pulse Width clk clkdiv_1/count_9_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.968
Data Arrival Time 8.723
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/ready_s1
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.711 1.464 tNET FF 1 R9C22[1][A] rx_1/ready_s3/I2
6.772 1.061 tINS FR 1 R9C22[1][A] rx_1/ready_s3/F
8.723 1.950 tNET RR 1 R8C2[0][A] rx_1/ready_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R8C2[0][A] rx_1/ready_s1/CLK
10.691 -0.043 tSu 1 R8C2[0][A] rx_1/ready_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.093, 26.200%; route: 5.437, 68.062%; tC2Q: 0.458, 5.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path2

Path Summary:

Slack 2.686
Data Arrival Time 7.648
Data Required Time 10.334
From rx_1/state_0_s9
To rx_1/state_1_s3
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.716 1.469 tNET FF 1 R11C22[3][A] rx_1/state_0_s5/I3
6.815 1.099 tINS FF 2 R11C22[3][A] rx_1/state_0_s5/F
6.826 0.011 tNET FF 1 R11C22[1][A] rx_1/n129_s11/I3
7.648 0.822 tINS FF 1 R11C22[1][A] rx_1/n129_s11/F
7.648 0.000 tNET FF 1 R11C22[1][A] rx_1/state_1_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C22[1][A] rx_1/state_1_s3/CLK
10.334 -0.400 tSu 1 R11C22[1][A] rx_1/state_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.953, 42.711%; route: 3.503, 50.660%; tC2Q: 0.458, 6.629%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path3

Path Summary:

Slack 2.686
Data Arrival Time 7.648
Data Required Time 10.334
From rx_1/state_0_s9
To rx_1/state_0_s9
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.716 1.469 tNET FF 1 R11C22[3][A] rx_1/state_0_s5/I3
6.815 1.099 tINS FF 2 R11C22[3][A] rx_1/state_0_s5/F
6.826 0.011 tNET FF 1 R11C22[1][B] rx_1/n130_s11/I2
7.648 0.822 tINS FF 1 R11C22[1][B] rx_1/n130_s11/F
7.648 0.000 tNET FF 1 R11C22[1][B] rx_1/state_0_s9/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
10.334 -0.400 tSu 1 R11C22[1][B] rx_1/state_0_s9

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.953, 42.711%; route: 3.503, 50.660%; tC2Q: 0.458, 6.629%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path4

Path Summary:

Slack 3.405
Data Arrival Time 8.337
Data Required Time 11.741
From tx_1/buffer_6_s0
To tx_1/txd_s0
Launch Clk clk9600hz:[R]
Latch Clk clk9600hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600hz
0.000 0.000 tCL RR 22 R12C24[1][A] toggle_1/out_s0/Q
2.851 2.851 tNET RR 1 IOB36[B] tx_1/buffer_6_s0/CLK
3.309 0.458 tC2Q RF 1 IOB36[B] tx_1/buffer_6_s0/Q
5.096 1.787 tNET FF 1 R12C30[0][B] tx_1/n50_s6/I1
6.195 1.099 tINS FF 1 R12C30[0][B] tx_1/n50_s6/F
6.200 0.005 tNET FF 1 R12C30[2][B] tx_1/n50_s5/I0
7.299 1.099 tINS FF 1 R12C30[2][B] tx_1/n50_s5/F
7.305 0.005 tNET FF 1 R12C30[0][A] tx_1/n50_s4/I0
8.337 1.032 tINS FF 1 R12C30[0][A] tx_1/n50_s4/F
8.337 0.000 tNET FF 1 R12C30[0][A] tx_1/txd_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600hz
10.000 0.000 tCL RR 22 R12C24[1][A] toggle_1/out_s0/Q
12.141 2.141 tNET RR 1 R12C30[0][A] tx_1/txd_s0/CLK
11.741 -0.400 tSu 1 R12C30[0][A] tx_1/txd_s0

Path Statistics:

Clock Skew -0.709
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.851, 100.000%
Arrival Data Path Delay cell: 3.230, 58.875%; route: 1.798, 32.770%; tC2Q: 0.458, 8.354%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.141, 100.000%

Path5

Path Summary:

Slack 3.501
Data Arrival Time 6.833
Data Required Time 10.334
From rx_1/count_0_s0
To rx_1/ready_s1
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C26[0][B] rx_1/count_0_s0/CLK
1.192 0.458 tC2Q RF 10 R11C26[0][B] rx_1/count_0_s0/Q
2.671 1.479 tNET FF 1 R9C22[0][A] rx_1/n139_s7/I0
3.770 1.099 tINS FF 1 R9C22[0][A] rx_1/n139_s7/F
6.833 3.063 tNET FF 1 R8C2[0][A] rx_1/ready_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R8C2[0][A] rx_1/ready_s1/CLK
10.334 -0.400 tSu 1 R8C2[0][A] rx_1/ready_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.099, 18.018%; route: 4.542, 74.468%; tC2Q: 0.458, 7.514%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path6

Path Summary:

Slack 3.695
Data Arrival Time 6.996
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_1_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.996 0.797 tNET RR 1 R11C24[0][A] rx_1/mask_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C24[0][A] rx_1/mask_1_s0/CLK
10.691 -0.043 tSu 1 R11C24[0][A] rx_1/mask_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.288%; route: 3.970, 63.393%; tC2Q: 0.458, 7.319%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path7

Path Summary:

Slack 3.695
Data Arrival Time 6.996
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_2_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.996 0.797 tNET RR 1 R11C24[0][B] rx_1/mask_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C24[0][B] rx_1/mask_2_s0/CLK
10.691 -0.043 tSu 1 R11C24[0][B] rx_1/mask_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.288%; route: 3.970, 63.393%; tC2Q: 0.458, 7.319%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path8

Path Summary:

Slack 3.695
Data Arrival Time 6.996
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_3_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.996 0.797 tNET RR 1 R11C24[1][A] rx_1/mask_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C24[1][A] rx_1/mask_3_s0/CLK
10.691 -0.043 tSu 1 R11C24[1][A] rx_1/mask_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.288%; route: 3.970, 63.393%; tC2Q: 0.458, 7.319%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path9

Path Summary:

Slack 3.695
Data Arrival Time 6.996
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_4_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.996 0.797 tNET RR 1 R11C24[1][B] rx_1/mask_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C24[1][B] rx_1/mask_4_s0/CLK
10.691 -0.043 tSu 1 R11C24[1][B] rx_1/mask_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.288%; route: 3.970, 63.393%; tC2Q: 0.458, 7.319%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path10

Path Summary:

Slack 3.699
Data Arrival Time 6.991
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_5_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.991 0.792 tNET RR 1 R11C22[0][A] rx_1/mask_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C22[0][A] rx_1/mask_5_s0/CLK
10.691 -0.043 tSu 1 R11C22[0][A] rx_1/mask_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.309%; route: 3.965, 63.366%; tC2Q: 0.458, 7.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path11

Path Summary:

Slack 3.699
Data Arrival Time 6.991
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/mask_6_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.397 1.150 tNET FF 1 R11C23[1][B] rx_1/mask_7_s3/I2
6.199 0.802 tINS FR 8 R11C23[1][B] rx_1/mask_7_s3/F
6.991 0.792 tNET RR 1 R11C22[0][B] rx_1/mask_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C22[0][B] rx_1/mask_6_s0/CLK
10.691 -0.043 tSu 1 R11C22[0][B] rx_1/mask_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 1.834, 29.309%; route: 3.965, 63.366%; tC2Q: 0.458, 7.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path12

Path Summary:

Slack 3.726
Data Arrival Time 6.964
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/count_0_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.233 0.986 tNET FF 1 R11C25[2][A] rx_1/count_4_s4/I2
6.259 1.026 tINS FR 5 R11C25[2][A] rx_1/count_4_s4/F
6.964 0.706 tNET RR 1 R11C26[0][B] rx_1/count_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C26[0][B] rx_1/count_0_s0/CLK
10.691 -0.043 tSu 1 R11C26[0][B] rx_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.058, 33.032%; route: 3.714, 59.611%; tC2Q: 0.458, 7.357%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path13

Path Summary:

Slack 3.726
Data Arrival Time 6.964
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/count_1_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][B] rx_1/mask_7_s4/I0
4.247 1.032 tINS FF 4 R9C27[3][B] rx_1/mask_7_s4/F
5.233 0.986 tNET FF 1 R11C25[2][A] rx_1/count_4_s4/I2
6.259 1.026 tINS FR 5 R11C25[2][A] rx_1/count_4_s4/F
6.964 0.706 tNET RR 1 R11C26[0][A] rx_1/count_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C26[0][A] rx_1/count_1_s0/CLK
10.691 -0.043 tSu 1 R11C26[0][A] rx_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.058, 33.032%; route: 3.714, 59.611%; tC2Q: 0.458, 7.357%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path14

Path Summary:

Slack 3.784
Data Arrival Time 7.946
Data Required Time 11.730
From debounce_1/clkdiv_1/count_1_s0
To debounce_1/clkdiv_1/count_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/Q
3.405 0.816 tNET FF 1 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/I0
4.431 1.026 tINS FR 10 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/F
4.863 0.433 tNET RR 1 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/I1
5.962 1.099 tINS RF 12 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/F
7.124 1.162 tNET FF 1 R12C10[0][A] debounce_1/clkdiv_1/n53_s1/I0
7.946 0.822 tINS FF 1 R12C10[0][A] debounce_1/clkdiv_1/n53_s1/F
7.946 0.000 tNET FF 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/CLK
11.730 -0.400 tSu 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.947, 50.673%; route: 2.410, 41.446%; tC2Q: 0.458, 7.881%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack 3.841
Data Arrival Time 8.226
Data Required Time 12.068
From debounce_1/key_n_0_s0
To tx_1/state_1_s1
Launch Clk debounce_1/clk400Hz:[R]
Latch Clk clk9600hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 debounce_1/clk400Hz
0.000 0.000 tCL RR 4 R12C14[0][A] debounce_1/clkdiv_1/clk400Hz_s/F
1.231 1.231 tNET RR 1 IOB24[B] debounce_1/key_n_0_s0/CLK
1.689 0.458 tC2Q RF 2 IOB24[B] debounce_1/key_n_0_s0/Q
3.317 1.628 tNET FF 1 R12C17[1][B] debounce_1/tx_send_s/I0
3.943 0.626 tINS FF 3 R12C17[1][B] debounce_1/tx_send_s/F
5.406 1.463 tNET FF 1 R12C26[1][B] tx_1/busy_s3/I2
6.032 0.626 tINS FF 2 R12C26[1][B] tx_1/busy_s3/F
6.043 0.011 tNET FF 1 R12C26[3][A] tx_1/state_0_s3/I3
7.104 1.061 tINS FR 2 R12C26[3][A] tx_1/state_0_s3/F
8.226 1.123 tNET RR 1 R12C24[2][A] tx_1/state_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600hz
10.000 0.000 tCL RR 22 R12C24[1][A] toggle_1/out_s0/Q
12.141 2.141 tNET RR 1 R12C24[2][A] tx_1/state_1_s1/CLK
12.111 -0.030 tUnc tx_1/state_1_s1
12.068 -0.043 tSu 1 R12C24[2][A] tx_1/state_1_s1

Path Statistics:

Clock Skew 0.910
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay cell: 2.313, 33.064%; route: 4.224, 60.384%; tC2Q: 0.458, 6.552%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.141, 100.000%

Path16

Path Summary:

Slack 3.864
Data Arrival Time 7.866
Data Required Time 11.730
From debounce_1/clkdiv_1/count_8_s0
To debounce_1/clkdiv_1/count_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/CLK
2.588 0.458 tC2Q RF 6 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/Q
2.951 0.363 tNET FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/I1
4.050 1.099 tINS FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/F
4.871 0.821 tNET FF 1 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/I0
5.970 1.099 tINS FF 16 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/F
6.834 0.864 tNET FF 1 R12C13[0][B] debounce_1/clkdiv_1/n44_s1/I2
7.866 1.032 tINS FF 1 R12C13[0][B] debounce_1/clkdiv_1/n44_s1/F
7.866 0.000 tNET FF 1 R12C13[0][B] debounce_1/clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C13[0][B] debounce_1/clkdiv_1/count_11_s0/CLK
11.730 -0.400 tSu 1 R12C13[0][B] debounce_1/clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.230, 56.314%; route: 2.047, 35.695%; tC2Q: 0.458, 7.991%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack 3.874
Data Arrival Time 7.856
Data Required Time 11.730
From debounce_1/clkdiv_1/count_1_s0
To debounce_1/clkdiv_1/count_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/Q
3.405 0.816 tNET FF 1 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/I0
4.431 1.026 tINS FR 10 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/F
4.863 0.433 tNET RR 1 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/I1
5.962 1.099 tINS RF 12 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/F
6.824 0.862 tNET FF 1 R12C11[1][A] debounce_1/clkdiv_1/n43_s1/I0
7.856 1.032 tINS FF 1 R12C11[1][A] debounce_1/clkdiv_1/n43_s1/F
7.856 0.000 tNET FF 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/CLK
11.730 -0.400 tSu 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.157, 55.137%; route: 2.110, 36.858%; tC2Q: 0.458, 8.005%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack 3.874
Data Arrival Time 7.856
Data Required Time 11.730
From debounce_1/clkdiv_1/count_1_s0
To debounce_1/clkdiv_1/count_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R12C10[1][B] debounce_1/clkdiv_1/count_1_s0/Q
3.405 0.816 tNET FF 1 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/I0
4.431 1.026 tINS FR 10 R12C12[1][A] debounce_1/clkdiv_1/n51_s2/F
4.863 0.433 tNET RR 1 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/I1
5.962 1.099 tINS RF 12 R12C13[0][A] debounce_1/clkdiv_1/clk400Hz_s0/F
6.824 0.862 tNET FF 1 R12C11[1][B] debounce_1/clkdiv_1/n42_s1/I0
7.856 1.032 tINS FF 1 R12C11[1][B] debounce_1/clkdiv_1/n42_s1/F
7.856 0.000 tNET FF 1 R12C11[1][B] debounce_1/clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C11[1][B] debounce_1/clkdiv_1/count_13_s0/CLK
11.730 -0.400 tSu 1 R12C11[1][B] debounce_1/clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.157, 55.137%; route: 2.110, 36.858%; tC2Q: 0.458, 8.005%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack 3.876
Data Arrival Time 7.854
Data Required Time 11.730
From debounce_1/clkdiv_1/count_8_s0
To debounce_1/clkdiv_1/count_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/CLK
2.588 0.458 tC2Q RF 6 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/Q
2.951 0.363 tNET FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/I1
4.050 1.099 tINS FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/F
4.871 0.821 tNET FF 1 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/I0
5.970 1.099 tINS FF 16 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/F
6.822 0.852 tNET FF 1 R12C14[1][A] debounce_1/clkdiv_1/n51_s1/I1
7.854 1.032 tINS FF 1 R12C14[1][A] debounce_1/clkdiv_1/n51_s1/F
7.854 0.000 tNET FF 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/CLK
11.730 -0.400 tSu 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.230, 56.431%; route: 2.035, 35.561%; tC2Q: 0.458, 8.008%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path20

Path Summary:

Slack 3.876
Data Arrival Time 7.854
Data Required Time 11.730
From debounce_1/clkdiv_1/count_8_s0
To debounce_1/clkdiv_1/count_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/CLK
2.588 0.458 tC2Q RF 6 R12C12[2][A] debounce_1/clkdiv_1/count_8_s0/Q
2.951 0.363 tNET FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/I1
4.050 1.099 tINS FF 1 R12C12[2][B] debounce_1/clkdiv_1/clk400Hz_s3/F
4.871 0.821 tNET FF 1 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/I0
5.970 1.099 tINS FF 16 R12C11[3][A] debounce_1/clkdiv_1/clk400Hz_s5/F
6.822 0.852 tNET FF 1 R12C14[0][B] debounce_1/clkdiv_1/n50_s1/I1
7.854 1.032 tINS FF 1 R12C14[0][B] debounce_1/clkdiv_1/n50_s1/F
7.854 0.000 tNET FF 1 R12C14[0][B] debounce_1/clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 49 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C14[0][B] debounce_1/clkdiv_1/count_5_s0/CLK
11.730 -0.400 tSu 1 R12C14[0][B] debounce_1/clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.230, 56.431%; route: 2.035, 35.561%; tC2Q: 0.458, 8.008%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path21

Path Summary:

Slack 3.881
Data Arrival Time 6.810
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/work_3_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][A] rx_1/work_7_s6/I2
4.247 1.032 tINS FF 8 R9C27[3][A] rx_1/work_7_s6/F
5.413 1.166 tNET FF 1 R11C23[3][A] rx_1/work_3_s5/I3
6.474 1.061 tINS FR 1 R11C23[3][A] rx_1/work_3_s5/F
6.810 0.336 tNET RR 1 R11C23[2][A] rx_1/work_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C23[2][A] rx_1/work_3_s0/CLK
10.691 -0.043 tSu 1 R11C23[2][A] rx_1/work_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.093, 34.448%; route: 3.525, 58.009%; tC2Q: 0.458, 7.544%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path22

Path Summary:

Slack 3.881
Data Arrival Time 6.810
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/work_7_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][A] rx_1/work_7_s6/I2
4.247 1.032 tINS FF 8 R9C27[3][A] rx_1/work_7_s6/F
5.413 1.166 tNET FF 1 R11C23[2][B] rx_1/work_7_s7/I3
6.474 1.061 tINS FR 1 R11C23[2][B] rx_1/work_7_s7/F
6.810 0.336 tNET RR 1 R11C23[1][A] rx_1/work_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R11C23[1][A] rx_1/work_7_s0/CLK
10.691 -0.043 tSu 1 R11C23[1][A] rx_1/work_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.093, 34.448%; route: 3.525, 58.009%; tC2Q: 0.458, 7.544%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path23

Path Summary:

Slack 3.916
Data Arrival Time 6.775
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/work_5_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][A] rx_1/work_7_s6/I2
4.247 1.032 tINS FF 8 R9C27[3][A] rx_1/work_7_s6/F
5.413 1.166 tNET FF 1 R9C21[1][A] rx_1/work_5_s5/I3
6.439 1.026 tINS FR 1 R9C21[1][A] rx_1/work_5_s5/F
6.775 0.336 tNET RR 1 R9C21[1][B] rx_1/work_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R9C21[1][B] rx_1/work_5_s0/CLK
10.691 -0.043 tSu 1 R9C21[1][B] rx_1/work_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.058, 34.068%; route: 3.525, 58.345%; tC2Q: 0.458, 7.587%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path24

Path Summary:

Slack 3.916
Data Arrival Time 6.775
Data Required Time 10.691
From rx_1/state_0_s9
To rx_1/work_6_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.734 0.734 tNET RR 1 R11C22[1][B] rx_1/state_0_s9/CLK
1.192 0.458 tC2Q RF 37 R11C22[1][B] rx_1/state_0_s9/Q
3.215 2.023 tNET FF 1 R9C27[3][A] rx_1/work_7_s6/I2
4.247 1.032 tINS FF 8 R9C27[3][A] rx_1/work_7_s6/F
5.413 1.166 tNET FF 1 R9C21[0][B] rx_1/work_6_s5/I3
6.439 1.026 tINS FR 1 R9C21[0][B] rx_1/work_6_s5/F
6.775 0.336 tNET RR 1 R9C21[0][A] rx_1/work_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600x2hz
10.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
10.734 0.734 tNET RR 1 R9C21[0][A] rx_1/work_6_s0/CLK
10.691 -0.043 tSu 1 R9C21[0][A] rx_1/work_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay cell: 2.058, 34.068%; route: 3.525, 58.345%; tC2Q: 0.458, 7.587%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.734, 100.000%

Path25

Path Summary:

Slack 4.003
Data Arrival Time 8.065
Data Required Time 12.068
From debounce_1/key_n_0_s0
To tx_1/busy_s1
Launch Clk debounce_1/clk400Hz:[R]
Latch Clk clk9600hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 debounce_1/clk400Hz
0.000 0.000 tCL RR 4 R12C14[0][A] debounce_1/clkdiv_1/clk400Hz_s/F
1.231 1.231 tNET RR 1 IOB24[B] debounce_1/key_n_0_s0/CLK
1.689 0.458 tC2Q RF 2 IOB24[B] debounce_1/key_n_0_s0/Q
3.317 1.628 tNET FF 1 R12C17[1][B] debounce_1/tx_send_s/I0
3.943 0.626 tINS FF 3 R12C17[1][B] debounce_1/tx_send_s/F
5.406 1.463 tNET FF 1 R12C26[1][B] tx_1/busy_s3/I2
6.031 0.625 tINS FR 2 R12C26[1][B] tx_1/busy_s3/F
8.065 2.035 tNET RR 1 IOL13[B] tx_1/busy_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk9600hz
10.000 0.000 tCL RR 22 R12C24[1][A] toggle_1/out_s0/Q
12.141 2.141 tNET RR 1 IOL13[B] tx_1/busy_s1/CLK
12.111 -0.030 tUnc tx_1/busy_s1
12.068 -0.043 tSu 1 IOL13[B] tx_1/busy_s1

Path Statistics:

Clock Skew 0.910
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay cell: 1.251, 18.304%; route: 5.125, 74.990%; tC2Q: 0.458, 6.706%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.141, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -1.306
Data Arrival Time 0.374
Data Required Time 1.681
From toggle_2/n9_s0
To toggle_2/out_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.002 0.002 tNET RR 1 R12C20[1][A] toggle_2/n9_s0/I2
0.374 0.372 tINS RF 1 R12C20[1][A] toggle_2/n9_s0/F
0.374 0.000 tNET FF 1 R12C20[1][A] toggle_2/out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C20[1][A] toggle_2/out_s0/CLK
1.681 0.030 tUnc toggle_2/out_s0
1.681 0.000 tHld 1 R12C20[1][A] toggle_2/out_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 99.369%; route: 0.000, 0.000%; tC2Q: 0.002, 0.631%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack -1.306
Data Arrival Time 0.374
Data Required Time 1.681
From toggle_1/n9_s0
To toggle_1/out_s0
Launch Clk clk9600hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600hz
0.000 0.000 tCL RR 22 R12C24[1][A] toggle_1/out_s0/Q
0.002 0.002 tNET RR 1 R12C24[1][A] toggle_1/n9_s0/I2
0.374 0.372 tINS RF 1 R12C24[1][A] toggle_1/n9_s0/F
0.374 0.000 tNET FF 1 R12C24[1][A] toggle_1/out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C24[1][A] toggle_1/out_s0/CLK
1.681 0.030 tUnc toggle_1/out_s0
1.681 0.000 tHld 1 R12C24[1][A] toggle_1/out_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 99.369%; route: 0.000, 0.000%; tC2Q: 0.002, 0.631%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack -0.250
Data Arrival Time 1.446
Data Required Time 1.696
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.446 1.446 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_0_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_0_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_0_s0
1.696 0.015 tHld 1 R11C10[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.446, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack -0.246
Data Arrival Time 1.450
Data Required Time 1.696
From mux7seg_1/i4/count_7_s0
To mux7seg_1/i4/count_7_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.450 1.450 tNET RR 1 R9C10[0][A] mux7seg_1/i4/count_7_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C10[0][A] mux7seg_1/i4/count_7_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_7_s0
1.696 0.015 tHld 1 R9C10[0][A] mux7seg_1/i4/count_7_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack -0.246
Data Arrival Time 1.450
Data Required Time 1.696
From mux7seg_1/i4/count_8_s0
To mux7seg_1/i4/count_8_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.450 1.450 tNET RR 1 R9C10[0][B] mux7seg_1/i4/count_8_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C10[0][B] mux7seg_1/i4/count_8_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_8_s0
1.696 0.015 tHld 1 R9C10[0][B] mux7seg_1/i4/count_8_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack -0.246
Data Arrival Time 1.450
Data Required Time 1.696
From mux7seg_1/i4/count_9_s0
To mux7seg_1/i4/count_9_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.450 1.450 tNET RR 1 R9C10[1][A] mux7seg_1/i4/count_9_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C10[1][A] mux7seg_1/i4/count_9_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_9_s0
1.696 0.015 tHld 1 R9C10[1][A] mux7seg_1/i4/count_9_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack -0.246
Data Arrival Time 1.450
Data Required Time 1.696
From mux7seg_1/i4/count_10_s0
To mux7seg_1/i4/count_10_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.450 1.450 tNET RR 1 R9C10[1][B] mux7seg_1/i4/count_10_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C10[1][B] mux7seg_1/i4/count_10_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_10_s0
1.696 0.015 tHld 1 R9C10[1][B] mux7seg_1/i4/count_10_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[0][A] mux7seg_1/i4/count_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[0][A] mux7seg_1/i4/count_1_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_1_s0
1.696 0.015 tHld 1 R9C9[0][A] mux7seg_1/i4/count_1_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_2_s0
To mux7seg_1/i4/count_2_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[0][B] mux7seg_1/i4/count_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[0][B] mux7seg_1/i4/count_2_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_2_s0
1.696 0.015 tHld 1 R9C9[0][B] mux7seg_1/i4/count_2_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_3_s0
To mux7seg_1/i4/count_3_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[1][A] mux7seg_1/i4/count_3_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[1][A] mux7seg_1/i4/count_3_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_3_s0
1.696 0.015 tHld 1 R9C9[1][A] mux7seg_1/i4/count_3_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_4_s0
To mux7seg_1/i4/count_4_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[1][B] mux7seg_1/i4/count_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[1][B] mux7seg_1/i4/count_4_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_4_s0
1.696 0.015 tHld 1 R9C9[1][B] mux7seg_1/i4/count_4_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_5_s0
To mux7seg_1/i4/count_5_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[2][A] mux7seg_1/i4/count_5_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[2][A] mux7seg_1/i4/count_5_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_5_s0
1.696 0.015 tHld 1 R9C9[2][A] mux7seg_1/i4/count_5_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack -0.242
Data Arrival Time 1.453
Data Required Time 1.696
From mux7seg_1/i4/count_6_s0
To mux7seg_1/i4/count_6_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
1.453 1.453 tNET RR 1 R9C9[2][B] mux7seg_1/i4/count_6_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C9[2][B] mux7seg_1/i4/count_6_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_6_s0
1.696 0.015 tHld 1 R9C9[2][B] mux7seg_1/i4/count_6_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path14

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_0_s0/CLK
1.984 0.333 tC2Q RR 2 R11C10[0][A] mux7seg_1/i4/count_0_s0/Q
1.986 0.002 tNET RR 1 R11C10[0][A] mux7seg_1/i4/n31_s2/I
2.358 0.372 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n31_s2/O
2.358 0.000 tNET FF 1 R11C10[0][A] mux7seg_1/i4/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_0_s0/CLK
1.651 0.000 tHld 1 R11C10[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path15

Path Summary:

Slack 0.708
Data Arrival Time 1.232
Data Required Time 0.524
From rx_1/count_1_s0
To rx_1/count_1_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.524 0.524 tNET RR 1 R11C26[0][A] rx_1/count_1_s0/CLK
0.858 0.333 tC2Q RR 3 R11C26[0][A] rx_1/count_1_s0/Q
0.860 0.002 tNET RR 1 R11C26[0][A] rx_1/n143_s7/I3
1.232 0.372 tINS RF 1 R11C26[0][A] rx_1/n143_s7/F
1.232 0.000 tNET FF 1 R11C26[0][A] rx_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.524 0.524 tNET RR 1 R11C26[0][A] rx_1/count_1_s0/CLK
0.524 0.000 tHld 1 R11C26[0][A] rx_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.524, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.524, 100.000%

Path16

Path Summary:

Slack 0.708
Data Arrival Time 1.232
Data Required Time 0.524
From rx_1/count_2_s0
To rx_1/count_2_s0
Launch Clk clk9600x2hz:[R]
Latch Clk clk9600x2hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.524 0.524 tNET RR 1 R11C25[1][A] rx_1/count_2_s0/CLK
0.858 0.333 tC2Q RR 3 R11C25[1][A] rx_1/count_2_s0/Q
0.860 0.002 tNET RR 1 R11C25[1][A] rx_1/n142_s6/I3
1.232 0.372 tINS RF 1 R11C25[1][A] rx_1/n142_s6/F
1.232 0.000 tNET FF 1 R11C25[1][A] rx_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk9600x2hz
0.000 0.000 tCL RR 34 R12C20[1][A] toggle_2/out_s0/Q
0.524 0.524 tNET RR 1 R11C25[1][A] rx_1/count_2_s0/CLK
0.524 0.000 tHld 1 R11C25[1][A] rx_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.524, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.524, 100.000%

Path17

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From debounce_1/clkdiv_1/count_2_s0
To debounce_1/clkdiv_1/count_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/CLK
1.984 0.333 tC2Q RR 3 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/Q
1.986 0.002 tNET RR 1 R12C10[0][A] debounce_1/clkdiv_1/n53_s1/I3
2.358 0.372 tINS RF 1 R12C10[0][A] debounce_1/clkdiv_1/n53_s1/F
2.358 0.000 tNET FF 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0/CLK
1.651 0.000 tHld 1 R12C10[0][A] debounce_1/clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From debounce_1/clkdiv_1/count_12_s0
To debounce_1/clkdiv_1/count_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/CLK
1.984 0.333 tC2Q RR 4 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/Q
1.986 0.002 tNET RR 1 R12C11[1][A] debounce_1/clkdiv_1/n43_s1/I2
2.358 0.372 tINS RF 1 R12C11[1][A] debounce_1/clkdiv_1/n43_s1/F
2.358 0.000 tNET FF 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0/CLK
1.651 0.000 tHld 1 R12C11[1][A] debounce_1/clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From clkdiv_2/count_1_s0
To clkdiv_2/count_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C22[1][A] clkdiv_2/count_1_s0/CLK
1.984 0.333 tC2Q RR 3 R12C22[1][A] clkdiv_2/count_1_s0/Q
1.986 0.002 tNET RR 1 R12C22[1][A] clkdiv_2/n54_s1/I1
2.358 0.372 tINS RF 1 R12C22[1][A] clkdiv_2/n54_s1/F
2.358 0.000 tNET FF 1 R12C22[1][A] clkdiv_2/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C22[1][A] clkdiv_2/count_1_s0/CLK
1.651 0.000 tHld 1 R12C22[1][A] clkdiv_2/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path20

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From clkdiv_2/count_5_s0
To clkdiv_2/count_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C21[0][A] clkdiv_2/count_5_s0/CLK
1.984 0.333 tC2Q RR 2 R12C21[0][A] clkdiv_2/count_5_s0/Q
1.986 0.002 tNET RR 1 R12C21[0][A] clkdiv_2/n50_s1/I3
2.358 0.372 tINS RF 1 R12C21[0][A] clkdiv_2/n50_s1/F
2.358 0.000 tNET FF 1 R12C21[0][A] clkdiv_2/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C21[0][A] clkdiv_2/count_5_s0/CLK
1.651 0.000 tHld 1 R12C21[0][A] clkdiv_2/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path21

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From clkdiv_1/count_3_s0
To clkdiv_1/count_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C29[1][A] clkdiv_1/count_3_s0/CLK
1.984 0.333 tC2Q RR 2 R11C29[1][A] clkdiv_1/count_3_s0/Q
1.986 0.002 tNET RR 1 R11C29[1][A] clkdiv_1/n52_s1/I1
2.358 0.372 tINS RF 1 R11C29[1][A] clkdiv_1/n52_s1/F
2.358 0.000 tNET FF 1 R11C29[1][A] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C29[1][A] clkdiv_1/count_3_s0/CLK
1.651 0.000 tHld 1 R11C29[1][A] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path22

Path Summary:

Slack 0.709
Data Arrival Time 1.585
Data Required Time 0.877
From mux7seg_1/seg_no_1_s0
To mux7seg_1/seg_no_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
0.877 0.877 tNET RR 1 R11C19[1][A] mux7seg_1/seg_no_1_s0/CLK
1.210 0.333 tC2Q RR 20 R11C19[1][A] mux7seg_1/seg_no_1_s0/Q
1.213 0.004 tNET RR 1 R11C19[1][A] mux7seg_1/n8_s0/I0
1.585 0.372 tINS RF 1 R11C19[1][A] mux7seg_1/n8_s0/F
1.585 0.000 tNET FF 1 R11C19[1][A] mux7seg_1/seg_no_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R9C10[2][A] mux7seg_1/i4/clk10KHz_s/F
0.877 0.877 tNET RR 1 R11C19[1][A] mux7seg_1/seg_no_1_s0/CLK
0.877 0.000 tHld 1 R11C19[1][A] mux7seg_1/seg_no_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.877, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.877, 100.000%

Path23

Path Summary:

Slack 0.709
Data Arrival Time 2.360
Data Required Time 1.651
From debounce_1/clkdiv_1/count_4_s0
To debounce_1/clkdiv_1/count_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/CLK
1.984 0.333 tC2Q RR 5 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/Q
1.988 0.004 tNET RR 1 R12C14[1][A] debounce_1/clkdiv_1/n51_s1/I3
2.360 0.372 tINS RF 1 R12C14[1][A] debounce_1/clkdiv_1/n51_s1/F
2.360 0.000 tNET FF 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0/CLK
1.651 0.000 tHld 1 R12C14[1][A] debounce_1/clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path24

Path Summary:

Slack 0.709
Data Arrival Time 2.360
Data Required Time 1.651
From clkdiv_2/count_3_s0
To clkdiv_2/count_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C20[0][A] clkdiv_2/count_3_s0/CLK
1.984 0.333 tC2Q RR 4 R12C20[0][A] clkdiv_2/count_3_s0/Q
1.988 0.004 tNET RR 1 R12C20[0][A] clkdiv_2/n52_s1/I1
2.360 0.372 tINS RF 1 R12C20[0][A] clkdiv_2/n52_s1/F
2.360 0.000 tNET FF 1 R12C20[0][A] clkdiv_2/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C20[0][A] clkdiv_2/count_3_s0/CLK
1.651 0.000 tHld 1 R12C20[0][A] clkdiv_2/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path25

Path Summary:

Slack 0.709
Data Arrival Time 2.360
Data Required Time 1.651
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C28[0][A] clkdiv_1/count_0_s0/CLK
1.984 0.333 tC2Q RR 5 R9C28[0][A] clkdiv_1/count_0_s0/Q
1.988 0.004 tNET RR 1 R9C28[0][A] clkdiv_1/n55_s1/I0
2.360 0.372 tINS RF 1 R9C28[0][A] clkdiv_1/n55_s1/F
2.360 0.000 tNET FF 1 R9C28[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 49 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C28[0][A] clkdiv_1/count_0_s0/CLK
1.651 0.000 tHld 1 R9C28[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.675
Actual Width: 3.925
Required Width: 1.250
Type: Low Pulse Width
Clock: clk9600hz
Objects: tx_1/buffer_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk9600hz
5.000 0.000 tCL FF toggle_1/out_s0/Q
8.126 3.126 tNET FF tx_1/buffer_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk9600hz
10.000 0.000 tCL RR toggle_1/out_s0/Q
12.050 2.050 tNET RR tx_1/buffer_6_s0/CLK

MPW2

MPW Summary:

Slack: 2.675
Actual Width: 3.925
Required Width: 1.250
Type: Low Pulse Width
Clock: clk9600hz
Objects: tx_1/buffer_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk9600hz
5.000 0.000 tCL FF toggle_1/out_s0/Q
8.126 3.126 tNET FF tx_1/buffer_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk9600hz
10.000 0.000 tCL RR toggle_1/out_s0/Q
12.050 2.050 tNET RR tx_1/buffer_5_s0/CLK

MPW3

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: clkdiv_1/count_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF clkdiv_1/count_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR clkdiv_1/count_3_s0/CLK

MPW4

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: clkdiv_2/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF clkdiv_2/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR clkdiv_2/count_6_s0/CLK

MPW5

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: debounce_1/clkdiv_1/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF debounce_1/clkdiv_1/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR debounce_1/clkdiv_1/count_7_s0/CLK

MPW6

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: debounce_1/clkdiv_1/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF debounce_1/clkdiv_1/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR debounce_1/clkdiv_1/count_8_s0/CLK

MPW7

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: clkdiv_2/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF clkdiv_2/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR clkdiv_2/count_7_s0/CLK

MPW8

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: debounce_1/clkdiv_1/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF debounce_1/clkdiv_1/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR debounce_1/clkdiv_1/count_9_s0/CLK

MPW9

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: debounce_1/clkdiv_1/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF debounce_1/clkdiv_1/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR debounce_1/clkdiv_1/count_10_s0/CLK

MPW10

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: clkdiv_1/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF clkdiv_1/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR clkdiv_1/count_9_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
49 clk_d 3.784 1.505
37 state[0] 1.968 2.298
34 clk9600x2hz 1.968 0.859
22 clk9600hz 3.405 3.126
20 seg_no[1] 7.767 3.434
19 state[1] 4.926 1.512
16 clk400Hz_11 3.864 0.864
14 state[0] 5.814 0.849
14 clk10KHz 7.761 2.296
12 seg_no[2] 8.499 1.986

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R11C22 38.89%
R12C12 30.56%
R11C23 27.78%
R11C24 27.78%
R9C14 26.39%
R12C25 26.39%
R12C26 26.39%
R9C15 25.00%
R9C13 23.61%
R11C28 23.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command