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                         ARM-Mץå¸߷ץ
                                  Last Modified:2015 Nov 23 08:57:56
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ΥɥȤΰ֤Ť

ΥɥȤϡTOPPERS/ASPͥARMvX-Mץå˰ܿ뤿
߷ץǤ롥


ARMVx-MλͤޤȤ(FPUʳ)

ARMvX-MλͤΤͥ߷פ˴طˤĤơޤARMv7-M
ˤĤƤޤȤ롥ARMv6-MϺǸARMv7-MȤκʬȤ롥

ͻ

ARMv7-M Architecture Reference Manual E.b
DDI0403E_B_armv7m_arm.pdf 

쥸

ѥ쥸R0R1516ढꡤR13Τߤ2Х󥯹PSP,MSPˤȤ
äƤ롥R15PC, R14ϥ󥯥쥸LRˤȤʤäƤ롥R0R3,R12
å쥸Ǥ롥

󥰥٥󥷥

R0R4ʾϥåͤϡR0R1˳Ǽ롥(ARM
구ꤵƤ뤿ᡤѥ˰¸Υ롼Ȥʤ롥)

CONTROL쥸

PSP,MSPڤؤPrivilageUser⡼ɤΥ쥸ѹϡ󥹥
饯Хåեեå̿¹ԤɬפisbˡCONTROL
ξܺ٤ϡARMv7-M Architecture Application Level Reference 
Manual  B1-9 򻲾ȤΤȡ

ߥ٥

٥ơ֥뷿ǡ٥ơ֥Υɥ쥹ϡꥻåȻ0x00ǡ
Vector Table Offset Registerʥޥåץɥ쥸 뤳
ǡǤդΥɥ쥹ֲǽǤ롥

ͥ

ͤͥ٤Ȥʤꡤ0ǹͥ٤Ȥʤ롥Ҥץ
åγͥ٤ꤹBASEPRI쥸'0'򥻥åȤȡ
γߤĤ뤿ᡤǹͥ٤ϡͭʥӥåȤLSB'1'Ȥͤ
3bitξ0x20ˡޤߤͥ٤'0'ꤹȡ
BASEPRI쥸ǥޥǤʤߤȤʤ롥

ͥ٤Ϻ8bitǤꡤSoC˼Ƥӥåۤʤ롥
ӥåȤ8bitʲξϡLSB̵ˤʤ롥㤨СƤ
ӥå7bitξϡӥå0̵Ȥʤ롥

ͥ٤ΥӥåȥեɤLSBӥåȤ򥵥ͥ٤ȸƤ֥ե
ꤹ뤳ȤǽǤ롥Ĥξ̥ӥåȤץꥨץͥ٤
Ƥ֡ץꥨץͥ٤Ʊǡͥ٤ۤʤͥ٤Υ롼
פϡߤץꥨץȤ뤳ȤǤʤ

Reset,NMI,Hard Fault ʳ㳰ϳߤƱͤͥ٤ǽǤꡤ
ߥޥǽˤꡤȯػߤ뤳ȤǽǤ롥


CPU⡼

ץåϡThread⡼ɤ⤷Handler⡼ɤΤ줫Υ⡼ɤȤ
롥

ꥻåȻξ

ꥻåȻThread⡼ɡMSPͭȤʤäƤ롥

Handler⡼

㳰/ߤդܤ⡼ɡդ㳰/ߤ㳰
椬IPSR˥åȤ롥㳰ֹϡTRMƤֹǤ롥

        㳰              㳰ֹ
  Reset                      1
  Non-makable Interrupt      2
  Hard Fault                 3
  Memory Management          4
  Bus Fault                  5
  Usage Fault                6
  SVCall                    11
  Debug Monitor             12
  PendSV                    14
  SysTick                   15
  IRQ0                      16
  IRQ1                      17
  ..

㳰/ߤդȡդ㳰/ߤٰͥʲ㳰/
ߤػߤ롥ͥ٥ޥ"NVICͥ٥ޥ"ȸƤ֡ͥ
ϡեȥѹ뤳ȤǤ㳰/ߤΥ꥿ˤ
ͤ˼ưŪ롥

åݥ󥿡PSPMSP

åݥ󥿤ϡPSPMSPꡤ¾Ū˻ѲǽǤ롥Handler
ɤǤMSPΤ߻ѲǽǤꡤThread⡼ɤǤCONTROL쥸
ǽǤ롥CONTROL쥸1ӥåܤ򥻥åȤPSPͭˡꥢ
ȡMSPͭˤʤ롥

Thread⡼ɤHandler⡼ɤ

Thread⡼ɤHandler⡼ɤؤܤϡ㳰/ߤդ뤳Ȥ
ȯ롥Handler⡼ɤThread⡼ɤؤܤϡPC
EXC_RETURN(0xfffffffx)ͤꤹ뤳ȤˤԤ㳰꥿
Ƥ֡ˡEXC_RETURNβ4bitˤꡤΥ⡼ɤѤ륹å
󥿤ѹǽǤ롥㳰꥿ˤꡤPRIMASKBASEPRIͤѲ
ʤFAULTMASKͤ'0'˥ꥢ롥

EXC_RETURN

㳰/߼դlrꤵ͡ӥå314ӥåȤ'1'ǡ
4bitϡդCPU⡼ɤ䥹åȿǤͤȤʤäƤ롥

 0b0001 : Handler⡼
 0b1001 : Thread⡼ with MSP
 0b1101 : Thread⡼ with PSP

Thread⡼ɤHandler⡼ɤȽ

Υ⡼ɤȽꤹˤϡIPSR򸫤ơ'0'ʤThread⡼ɡʳ
ʤ顤Handler⡼ɤȤʤ롥

BASEPRI쥸

ꤷٰͥʲͥ٤γߤμդػߤ롥ͥ٥ޥ
"BASEPRIͥ٥ޥ"ȸƤ֡'0'ꤹȡƤγߤĤ롥
㳰/ߤμդȥ꥿ˤѲʤ㳰/ߤФ
ͥ٥ޥϡNVICͥ٥ޥBASEPRIͤι⤤ͤ
ˤȤʤ롥

FAULTMASK

FAULTMASK'1'򥻥åȤ뤳ȤˤꡤNMIʳƤγߤػߤ롥
FAULTMASKϡ㳰Υ꥿ˤ'0'˥ꥢ롥

PRIMASKWFI

PRIMASK'1'ꤹȡNMI  Hardware Fault ʳ㳰/ߤ
ߤ롥PRIMASKϳߤεĤȳԤ򥢥ȥߥå˹ԤѤ
롥ŪˤϡPRIMASKåȤƤ֤wfi¹Ԥȡ
ԤȤʤꡤ߼դȥϥɥ¹Ԥˡwfi꥿
Ƥ롥

㳰/ߤμ

㳰/ߤդȡդ˥ƥ֤ʥå˰ʲΥ
  ƥȤ¸(㳰ե졼ȸƤ)

   -----------
  |    R0     |  <- new SP
   -----------
  |    R1     |
   -----------
  |    R2     |
   -----------
  |    R3     |
   -----------
  |    R12    |
   -----------
  |    LR     |
   -----------
  |    PC     |
   -----------
  |   xPSR    |
   -----------
  |           | <- old SP

ץåHandler⡼ɤȤ롥MSPͭȤʤ롥
դ㳰/ߤ㳰ֹIPSRꤹ롥
NVICͥ٥ޥդ㳰/ߤͥ٤ꤹ롥
lrEXC_RETURNͤꤵ롥
٥ơ֥ɤ߹ߥϥɥ¹Ԥ롥
åե졼ϡConfigureation and Control Register(CCR)
  STKALIGN'1'ξϡ8byte˥饤󤵤롥

㳰/ߤΥ꥿

pcEXC_RETURNͤꤹ뤳Ȥˤꡤ㳰/ߤ꥿󤹤롥
pcؤ˻Ѳǽ̿ˤ¤ꡤʲ̿᤬ѲǽǤ롥

  POP/LDM, LDR, BX

̤

٥ơ֥ϿؿΥɥ쥹LSB'1'ˤ٤?
NVIC㳰ߤΥͥȲŪ˴Ƥ餷
  (!ե󥹤餫)
    եȥǤϡͥȤĢ碌С꥿󥹥å¤
    Ƥʤ

stmfd

stmfdϥ쥸ꥹȤ1ĤξưȤʤäƤ롥Τᡤ
ꥹȤ1ĤεҤ򥢥֥ˤϡ֥餬str.w 
Ѵ뤬֥ˤäƤϥ˥󥰤Фᡤ쥸ꥹȤ
1Ĥξϡstr.wѤ롥

ʤldmfdˤϤ¤ʤ

ARMv6-M

ͥ߷פФơARMv6-MARMv7-MФ뺹ʬϼ̤Ǥ롥

BASEPRI쥸
  ARMv6-MǤBASEPRI쥸ʤ

FAULTMASK
  ARMv6-MǤFAULTMASK쥸ʤ
  
̿
  ̿᤬ѽʤ
  Ʊ̿Ǥǽʥ쥸¤
  
߿
  32
  

FPUϢλ

ͻ

ARMv7-M Architecture Reference Manual E.b
DDI0403E_B_armv7m_arm.pdf 

ARM CortexR-M4 Processor Technical Reference Manual Revision: r0p1 
arm_cortexm4_processor_trm_100166_0001_00_en.pdf

Cortex-M4(F) Lazy Stacking and Context Switching Application Note 298
DAI0298A_cortex_m4f_lazy_stacking_and_context_switching.pdf



Cortex-M4ARMv7E-M١ȤƤ롥FPUݡȤȥݡȤ
Ƥʤ롥FPU򥵥ݡȤCortex-M4FȸƤ֡
ߤ롥

FPUARMv7E-M Floatng Point Extension(FPv4-SP)򥵥ݡȤƤ롥

FPv4-SPϼλͤȤʤäƤ롥

쥸 : ñ٥쥸 S0S32 / ٥쥸 D0D15 
           D0(S0S1)
̿     : ñ̿򥵥ݡ

쥸

FPSCR : Floating-point Status and Control Register
FPUΥơȥȥեɤ

CPACR : Coprocessor Access Control Register
FPUͭˤ˥åȤɬפ

FPCCR : Floating-point Context Control Register
FPUϢΥƥȤ¸ˡǽ

FPCAR : Floating Point Context Address Register
㳰ե졼FPU쥸¸ɥ쥹(S0Υɥ쥹)ݻ 

FPDSCR : Floating-point Default Status Control Register
FPSCRΥǥեͤ¸
FPUƻѤ[26:22]FPSCR˥ԡ롥

CONTROLγĥ
.FPCA(Bit[2])
  FPUѤ'1'˥åȤ롥

EXC_RETURNγĥ

EXC_RETURN[4]
 '0' : FPUΰ褢(¸Ƥ뤫̤)
       S0S15FPSCRΤΰ补
 '1' : FPUΰʤ

ABI

S0S15,FPSCR  : caller saved registers
S16S17       : callee saved registers

㳰ȯο

ܺ٤ ARMv7-M Architecture Reference Manual E.b B1.5.6 Exception 
entry behavior  B1.5.8 Exception return behavior 򻲾ȤΤȡ
 
ƥȤ¸ѥ
    FPCCR
 LSPEN  ASPEN      ̾(ܥɥȥꥸʥ)
   0      0      :  NoAutomatic
   0      1      :  DisableLazystacking
   1      1      :  Lazystacking
 
NoAutomatic 
ư¸ʤ

DisableLazystacking
ư¸ꡥLazystackingʤ
FPUѤ CONTROL.FPCA '1'åȤ롥
CONTROL.FPCA == 1ξ㳰/ߤȯFPUƥȤ
  å¸롥

Lazystacking
ư¸ꡥLazystacking Ԥ
FPUѤ CONTROL.FPCA '1'åȤ롥
CONTROL.FPCA == '1'ξ㳰/ߤȯFPUƥȤ
  ¸ѤΰΤ߳ݤ졤FPCCR.LSPACT '1'ꤵ롥
FPCCR.LSPACT == '1' ξFPU̿ѤFPUΥƥȤ
  ¸ΰ¸롥

FPU˴ؤ㳰/ߤ

DisableLazystacking or Lazystacking ξ
 CONTROL.FPCA == 1ξ
   㳰ե졼FPU쥸¸Ѥΰ
   DisableLazystacking ξ
     FPU쥸¸ѤΰFPU쥸(S0S15,FPSCR)¸
   Lazystacking
     FPCAR 㳰ե졼FPU쥸¸ɥ쥹(S0Υɥ쥹)ݻ
     FPCCR.LSPACT 1ˡ
CONTROL.FPCA0˥ꥢ

FPU˴ؤ㳰/ߤνи

EXC_RETURN4ӥåܤ'0'ξ(FPUѤƤ)
 FPCCR.LSPACT == '1'ξ(ߥϥɥFPUѤʤä)
   FPCCR.LSPACT'0'
 FPCCR.LSPACT == '0'ξ(ߥϥɥFPUѤ)    
   S0S32FPSCR㳰ե졼फ᤹    
EXC_RETURN4ӥåܤCONTROL.FPCA
 ¼CONTROL.FPCA

ISRǤFPUο

FPCCR.LSPACT==1(LazystackingλˤΤȯ)FPU̿Ѥ
FPCARΥɥ쥹FPU쥸(S0S15,FPSCR)¸
FPCCR.LSPACT 0ˤ롥

OSμ

1.å̾

 1-1 cm3(Cortex-M3)
 1-2 armv7m(ARMv7-M)
 1-3 arm_m

cm3ǤϡARMv6-M򥵥ݡȤȤʤ롥armv7mǤϡarmv8m
꡼줿Ȥʤ롥ARM¸JSPǤϡarmv4ȤʤäƤ
armv5armv7ư뤿ASPǤñarmȤΤᡤarm_m̵
ȹͤ롥


2.Thread⡼ɤHandler⡼ɤλȤʬ

 2-1
  ƥȤThread⡼ɡ󥿥ƥȤHandler⡼
  ɤư롥

 2-2
  ƥȤ󥿥ƥȶHandler⡼ɤư
  롥

ץå߷ˤθ2-1ͭϡ2-1ǤȤƤϡ
ߥϥɥ餫饿ؤΥ꥿˥⡼ɤѹʲͤ¿ȯ뤳
Ȥ󤲤롥

1.ߥϥɥ               : Handler⡼
2.㳰ϥɥθƤӽФ : Thread⡼
3.ؤΥ꥿       : Handler⡼
4.κƳ                 : Thread⡼

3Handler⡼ɤ˰ܹԤɬפΤϡ㳰ե졼Ѥ
ˤϡHandler⡼ɤ㳰꥿Ԥɬפ뤿Ǥ롥ARM
ϡʣ쥸ΥɤCPSRƱ˹Ԥ뤬M3ϹԤʤᡤ
ˡǳΥ˥꥿󤹤ɬפ롥

2-2ξγߥϥɥ餫饿ؤΥ꥿˥⡼ɤѹʲ
˼ޤ2-2Ǥϳͥ٤κͤ򥿥μ¹Իͥ٤Ȥ
ƥꥶ֤ɬפ롥

1.ߥϥɥ               : Handler⡼
2.NVICͥ٥ޥ'0'0     : Thread⡼
3.ͥ٤Handler⡼ɤ  : Handler⡼
4.㳰ϥɥθƤӽФ : Handler⡼
5.ؤΥ꥿   : Thread⡼
3.ؤΥ꥿           : Handler⡼
4.κƳ                 : Handler⡼

ߥϥɥ餫饿Υ꥿˴ؤƤϡ2-2ǤäƤ⡤2¹Ԥ
ˡNVICͥ٥ޥ'0'ˤ뤿ᡤ㳰꥿Ԥɬ
롥ޤNVICΤߤΥͥȲƤ뤿ᡤ34
ؤܤΤˡä㳰/ߤդ֤ˤɬפ뤿
ᡤŪ2-1ʾܤɬפȤʤ롥

2-2ξϡMSPȤʤᡤߤǥͥȲȽǤơ
åؤɬפ롥

HRPǥݸѤ2-1Ȥʤ롥

ʾͳˤꡤ2-1Ѥ롥2-1ϡͥ뵯ưIDLE롼
פΰƤɬפ롥ˤĤƤӵ롥


3.ǥѥåμ¹ԥ⡼

 3-1
  Thread⡼ɤǼ¹Ԥ

 3-2
  Handler⡼ɤǼ¹Ԥ

ǥѥåThread⡼ɤǼ¹ԤȡߤˤץꥨץȤ
ϼΤ褦ʥѥˤʤ롥

 1. ǥѥåƤӽФ : Thread⡼ 
 2. ǥѥå¹     : Thread⡼
 3. 㳰¹         : Thread⡼
 4ؤΥ꥿ : Handler⡼
 5. κƳ           : Thread⡼

ߥϥɥ餫鼫ǥѥåإ꥿󤹤ϼΥ
ˤʤ롥

 1.ߥϥɥ               : Handler⡼
 2.ǥѥå¹           : Thread⡼
 3.㳰ϥɥθƤӽФ : Thread⡼
 4.ؤΥ꥿           : Handler⡼
 5.κƳ                 : Thread⡼

ǥѥåHandler⡼ɤǼ¹Ԥȡߤˤץꥨ
ץȤ줿ϼΤ褦ʥѥˤʤ롥

 1. ǥѥåƤӽФ : Thread⡼ 
 2. ǥѥå¹     : Handler⡼
 3. 㳰¹         : Thread⡼
 4ؤΥ꥿     : Handler⡼
 5. κƳ           : Thread⡼

ߥϥɥνи鼫ǥѥåإ꥿󤹤
Υѥˤʤ롥

 1.ߥϥɥ               : Handler⡼
 2.ǥѥå¹           : Handler⡼
 3.㳰ϥɥθƤӽФ : Thread⡼
 4.ؤΥ꥿           : Handler⡼
 5.κƳ                 : Thread⡼

㳰ϥɥ餬ʤOSξϡHandler⡼ɤǼ¹Ԥ⡼
ܤβ뤬㳰ϥɥ餬ȡThread⡼ɤ
ܲ뤿ᡤThread⡼ɤȤ롥

ݸθȡǥѥåHandler⡼ɤư
Ψ褤ȹͤSVCǥϥɥƤӽФHandler⡼ɤȤʤ뤿
ˡ


4.åλȤʬ

 4-1
  ƥȤPSP, 󥿥ƥȤMSP
 4-2
  ƥȡ󥿥ƥȶMSP

4-2ξ硤ߤǥͥȲȽǤơåؤ
ɬפ롥2ǥƥȤThread⡼ɡ󥿥ƥ
Handler⡼ɤưȤᡤ4-1Ѥȡߤ
ǼưŪ˥åڤؤ롥Thread⡼ɤǤPSPΥ⡤
mrs/msr̿ǹԤ뤿ᡤ4-1Ѥ롥


5.ƥȤȽ

 5-1
  IPSR'0'(Thread⡼)ʤ饿ƥȡ'1'(Handler⡼
  )ʤ󥿥ƥȤȤ롥

 5-2
  ߤΥͥȲݻѿѰա1ʾ󥿥ƥȡ

 5-3
  ƥ֤ʥåˤȽǡMSPʤ󥿥ƥȡPSPʤ
  ƥȤȤ

5-1ϡեȥ¦ǥƥȴΤνԤɬפʤ
åȤ롥ʤ顤ͥεưThread⡼ɤǤ뤿
ᡤHandler⡼ɤذܹԤɬפ롥ASPͥǤϡIDLE롼׼¹
󥿥ƥȤȤưɬפ뤿ᡤIDLE롼פ
Handler⡼ɤưɬפ롥IDLE롼פϥǥѥå㤫
ӽФ롥3᤿褦ˡǥѥåThread⡼ɤư
ᡤIDLE롼פƤӽФݤˤϡHandler⡼ɤܤɬפ롥
Handler⡼ɤؤܤϡSVC/PendSVCѤȼ¸ǽǤ뤬6γ
ߤ˥ץꥨץȤ줿ؤΥ꥿Handler⡼ɤؤΰܹԤ
SVC/PendSVCλѤɬפȤʤ뤿ᡤSVCϥɥǤϡɤŪǸƤӽ
줿ȽꤹɬפФƤ뤿ᡤХإåɤ礹롥

5-2Ǥϡͥ뵯ưIDLE롼׻ѿ'1'ꤹФ褤Ȥ
ʤ롥ξ硤ͥ뵯ưIDLE롼׻Thread⡼ɤǼ¹ԤƤ
ư꤬ʤ褦ä˳ߤν߷פդɬפ롥

ͥ뵯ư˴ؤƤϡߤػߤƤꡤߤʤΤ
äϤʤIDLE롼׻ϡThread⡼ɤMSPPSP򤬲ǽǤ
뤳ȤѤơ󥿥ƥȤΥåǤMSPѹ롥
㳰/ߤǤϡ¿ųߤǤ뤫EXC_RETURNΥ⡼Ƚ
ӥåȤǤϤʤåȽӥåȤǹԤʤ㳰/ߤ
Υ꥿˴ؤƤϡ¿ųߤȽϡƱͤEXC_RETURNΥ
åȽӥåȤǹԤФ褤㳰꥿pc
EXC_RETURNͤΧ0xfffffffd (Thread⡼ with MSP)ȤΤǤϤʤ
㳰/߼դLRꤵEXC_RETURNѤ뤳ȤˤꡤIDLE
롼פ˳Ǥʤ꥿󤹤롥

ͥ뵯ưϡMSPƥ֤Ǥꡤߥϥɥ¹ԻHandler
⡼ɤǤ뤳ȤMSPƥ֤ǤꡤIDLE롼׻MSP򥢥ƥ
ꤹȡ󥿥ƥȤơMSP򥢥ƥ֤ˤư
뤳Ȥˤʤ롥ޤ߻ϳ˥ƥ֤ʥåξ󤬡
EXC_RETURNꤵ롥ΤᡤƥȤȽϡߥͥȲ
ݻѿʤȤ⡤ƥ֤ʥå򸫤Ф褤Ȥˤʤ롥
ޤexc_sense_context()˴ؤƤϡ㳰ե졼EXC_RETURNɲ
ƤˤȽǤФ褤ʾͳˤꡤ5-3Ѥ롥


6.ߤ˥ץꥨץȤ줿ؤΥ꥿Handler⡼ɤؤΰ
  ˡ

 6-1
  SVCѤ
 6-2
  PendSVCѤ

PendSVCSVCΰ㤤ϡPendSVC׵᤬塼󥰤졤SVC׵᤬
󥰤ʤȤǤ롥ߤ˥ץꥨץȤ줿ؤΥ꥿
Handler⡼ɤؤΰܹԤϡ塼󥰤줺¨¤˽ɬ
פ뤿ᡤɤǼ¸Ƥʤɤ򥫡ͥΥ꥽
ƻѤ뤫Ǥ롥

ɤȤȤƤ⡤ͥ٤꤬Ȥʤ롥ǥѥå㤫
ߤ˥ץꥨץȤ줿ؤΥ꥿ޤǤνϡʤȤCPU
å֤Ǽ¹ԤʤФʤʤSVCPendSVCϤɤͥ
ĤᡤNVICͥ٥ޥBASEPRIͥ٥ޥ⤤硤
ʤ

CPUå֤BASEPRIǼ¸硤ͤSVCPendSVC
ꤷͤ㤯ɬפ롥ȡSVCPendSVCͥ٤
CPUåͥ٥ޥͤ⤤͡¾γߤ⤤ͥ١ˤ
ɬפ롥

CPUå֤FAULTMASKPRIMASKǼ¸ϡ餬ꤵ
ȡSVCPendSVCդʤᡤäBASEPRIˤߤ
褦ꤹɬפ롥ξ⡤SVCPendSVC¾γ
⤤ͥ٤ꤹɬפ롥

ʾˤꡤHandler⡼ɤؤΰܹԤΤˤϡCPUå֤BASEPRI
¸SVCPendSVCꤹͥ٤򥫡ͥκǹͥ٤
Ĺ⤤ͥ٤ꤹɬפ롥

ARMv7-MǤSVCˤ¸롥SVNPendSVC¹ԥХإåɤ
ᡤSVCѤ

ARMv6-MǤSVCˤ¸롥ARMv6-MCPUå֤PRIMASKǼ¸
ƤPRIMASK򥻥åȤ֤SVC¹ԤȥեȤȤʤ뤿ᡤ
PendSVCȯԤơPRIMASK򥯥ꥢ뤳ȤǼ¸롥PendSVCγ
ͥ٤ϺǹȤƤ뤿ᡤδ֤ǳߤ뤳ȤϤʤ


7. 㳰/߽Ǥ¿ųߤȽ

7-1
 EXC_RETURNΥ⡼Ƚӥå
7-2
 EXC_RETURNΥåȽӥå
7-3
 ߥͥȲδѿ

㳰/߼դϡդ㳰/߰ʲγߤ϶ػߤ뤬
߶ػ߾֤ˤϤʤʤΤᡤߥͥȲδѿ򥤥
Ȥ˳ߤǽ뤿ᡤ7-3ϻѤ뤳Ȥ
ʤ

5ǵ̤ꡤIDLE롼פThread⡼ɤǼ¹Ԥ뤿ᡤ7-1ǤϤʤ
7-2ȽǤɬפ롥


8. IDLE롼

8-1
 Thread⡼ɤǼ¹
8-2
 Handler⡼ɤǼ¹

5ǵ̤ꡤThread⡼ɤǼ¹ԤǤХإåɤ
Thread⡼ɤǼ¹ԤƤ⡤ߤν󥿥
ȤȽǤСThread⡼ɤʤ


9ͥγߤΥݡ

9-1
 ͥγߤ򥵥ݡȤʤ
9-2
 ͥγߤ򥵥ݡȤ

ARMv7-MǤϡCPUåBASEPRIǼ¸Ƥ뤳ȡ٥ơ֥
ݡȤƤꡤߥϥɥCǵҲǽǤ뤿ᡤݡȤ
ưפǤ뤿ᡤݡȤ롥

ARMv6-MǤϡCPUåPRIMASKǼ¸Ƥ뤿ᡤݡȤʤ


10. CPUå

10-1
 BASEPRI(ARMv7-M) 
 ̤γ߶ػߵĤǥߥ졼(ARMv6-M)
10-2 
 FAULTMASK/PRIMASK

ͥδγߤ򥵥ݡȤʤ顤BASEPRIѤɬפ
롥

ARMv7-MǤCPUåBASEPRIѤ롥

ARMv6-MǤCPUåPRIMASKѤ롥̤γ߶ػߵĤǥߥ
졼󤹤ˡϡSysTicΤ̤Υ쥸ꤹɬפꡤ¹
Хإåɤ礭Ȥ꤬롥

11. ߥåCPU㳰δط

11-1
 BASEPRI(ARMv7-M) 
11-2 
 FAULTMASK/PRIMASK 

FAULTMASK/PRIMASKѤȡNMI  Hardware Fault ʳCPU㳰
ߤƤޤ

BASEPRIѤȡߥåˤCPU㳰դϡ
BASEPRIѤơǹͥ٤CPU㳰Τ˥ꥶ֤ɬפ롥

ߥå⡤CPU㳰դ褦ˤBASEPRIѤɬ
פ롥

IRON4.0ͤ3.5.3ǤϡCPU㳰ͥ٤ϼΤ褦Ƥ롥

"CPU㳰ϥɥ̤ͥϡCPU㳰ȯͥ٤ȡǥ
ѥå̤ͥΤ줫⤤"

CPU㳰ȯͥ٤⤤ȤΤǡCPUåߥ
å֤ΥȯǤ⡤ͥ褷Ƽ¹Ԥ٤Ȥͤ
롥

TOPPERSɸ߽ǥλͽǤϡCPU㳰ϡץå
˰ۤʤ뤿ᡤCPU㳰νǥɸಽƤоݳȤƤ롥
ᡤARM-MǤΰơޥ˥奢Ф褤ȹͤ롥

ARMv7-MǤϳߥåBASEPRIѤ롥

ARMv6-MǤϳߥåPRIMASKѤ롥


12. ͥ٤ͥ٤Ѵ

ͥ٤ȤAPIǻꤹͥ(PRI)ΤȤǤꡤͤ
ۤͥ٤⤤ߥϥɥˤϡ-1Ϣ³ͤǽ
롥ͥ٤ϡBASEPRINVICͥ٥쥸ꤹͤǤ롥

ͥ٤Υӥå TBITW_IPRI Ȥȡǽʳ
ͥ٤ϼΤ褦ˤʤ롥

  TIPM_ENAALLʡ0ˡ -(1 << TBITW_IPRI)


13. ͥκǹͥ(CPUå֤Ǥͥ٥ޥ)

6.ǽҤ٤褦ˡߤνиSVCϥɥƤӽФɬפ뤿ᡤ
SVCϥɥCPUå֤BASEPRIꤹͥ٥ޥ⤤ͥ
ꤹɬפ롥

ͥ٤Υӥå TBITW_IPRIͥΥͥ٤
ӥåTBIT_IPRIȤȡCPUå֡ʥͥߤ
ǽʺǹͥ١ˤȤƻǽͥ٥ޥϰϤϰʲͤ
ϤȤʤ롥

    -(2^(TBIW_IPRI) - 1) + (2^TBITW_SUBIPRI)  -1


14. ͥ٥ޥ

ARMv7-MǤBASEPRIˤ¸롥

ARMv6-MǤϸ̤γ߶ػߵĵǽѤƥߥ졼󤹤롥


15. FPUΥݡ

15-1
 FPUѤ륿/ISR桼ꤹ롥 ꤷƤʤ/ISR
 ǤFPUѤ㳰Ȥʤ롥
15-2
 FPUѤ륿/ISR桼ϻꤷʤƤΥ/ISRFPU
 ѲǽǤ롥
 
15-1ϰ̤˥ƥȤ¸ΥХإåɤ㸺ŪǺѤ
롥15-1ѤȡISR°γĥɬפȤʤ롥

ARMv7-MǤϡFPUѤΤ㳰ߤFPUƥ
Ȥ¸뵡ǽ뤿ᡤ15-2򤷤Ƥ⡤FPUȤʤ¤ϥڥ
ƥϤʤȹͤ15-2Ѥ롥

FPU˴ؤ륵ݡȤΥХꥨϼȤ߹碌ǽǤ롥

                       FPCCR                          ƥ  
                    LSPEN  ASPEN ѥ륪ץ  ¸     FPU
NO_FPU                -      -        ʤ           ʤ       ̵   
FPU_NO_PRESERV        0      0    -mfpu=fpv4-sp-d16      ʤ       ͭ
FPU_NO_LAZYSTACKING   0      1    -mfpu=fpv4-sp-d16             ͭ
FPU_LAZYSTACKING      1      1    -mfpu=fpv4-sp-d16             ͭ

NO_FPU
FPUѤʤCortex-M0/Cortex-M0+/Cortex-M3/Cortex-M4 ξ˻ꡥ
ǥѥåǤFPUƥȤ¸Ԥʤ

FPU_NO_PRESERV
FPUѤ롥Cortex-M4F ξ˻ǽ
ǥѥåǤFPUƥȤ¸Ԥʤ
FPUѲǽʥ1Ĥ⤷ϡƥκǹͥ٤ISRǻ
Ѳǽ

FPU_NO_LAZYSTACKING
FPUѤ롥Cortex-M4F ξ˻ǽ
ǥѥåǤFPUƥȤ¸ԤLazy stacking 
Ѥʤ
ƤΥ/ISRFPUѲǽ

FPU_LAZYSTACKING
FPUѤ롥Cortex-M4F ξ˻ǽ
ǥѥåǤFPUƥȤ¸ԤLazy stacking 
Ѥ롥
ƤΥ/ISRFPUѲǽ


FPU_NO_LAZYSTACKINGΥ쥸¸

FPU_NO_LAZYSTACKING ξϰ̥쥸Ʊߥ󥰤ǡǥѥ
ΥFPUѤƤȽǤƥ쥸¸
褤սϼ̤Ǥ롥

ǥѥå(dispatch)
CONTROL.FPCAå'1'ʤs16-s31¸
ѤCONTROL.FPCA򥿥å¸

ǥѥå(dispatch)
CONTROL.FPCA򥿥å
CONTROL.FPCAå'1'ʤs16-s31򥿥å
  롥

ٱǥѥå(ret_int_4)
ޤ줿ݤEXC_RETURN򥿥å¸Ƥ
EXC_RETURN򥿥å
EXC_RETURN[4] == 0(FPU)ʤs16-s31򥿥å¸
  롥
ѤEXC_RETURNͤ򥿥å¸  

ٱǥѥå(ret_int_r)
ޤ줿ݤEXC_RETURNͤ򥿥å
EXC_RETURN[4] == 0(FPU)ʤs16-s31򥿥å
SVCϥɥƤӽФFPU쥸Ѥޤʤ褦CONTROL.FPCA򥯥ꥢ

FPU_LAZYSTACKINGΥ쥸¸

FPU_NO_LAZYSTACKINGΥɤ򤽤Τޤ޻ѤFPU_LAZYSTACKINGξ
ϡߡ㳰ȯ˼Υߥ󥰤㳰ե졼FPUΥƥ
ȤϡɥˤäƼưŪ¸롥

㳰ߥϥɥ¹
FPUѤ/ISR¹㳰ߤȯ㳰ߥϥ
ɥFPU̿¹Ԥ硥FPCCR.LSPACT==1 ȤʤäƤ뤿ᡥ

ٱǥѥå(ret_int_4)
㳰ߥϥɥFPUѤʤäϡret_int_4¹Իˤϥ
ƥȤ¸Ƥʤ˳ƥ쥸ͤϼΤ褦ˤʤäƤ
롥
FPCCR.LSPACT == '1'
FPCAR = 㳰ե졼FPU쥸¸ɥ쥹(S0Υɥ쥹)
ret_int_4Ǥϡs16-s31 򥿥å¸롥FPUѤ
ᡤs0-s15,FPSR㳰ե졼¸롥

ʲβսFPU_LAZYSTACKINGξˤΤɬפǤ롥

߽иǤΥ㳰ƤӽФ
FPUѤ¹㳰/ߤȯ㳰/ߤνи
㳰ƤӽФˤϡFPCCR.LSPACT == '1' FPUƥ
Ȥ¸Ƥʤ֤ǥ㳰ƤӽФǽ롥
㳰ext_tsk()ƤӽФ¾Υ˥ǥѥå졤
ter_tsk()ǽλ줿ˤϡFPCCR.LSPACT  '0'˥ꥢɬ
롥ext_tsk()ΥϥåȰ¸exit_and_dispatch()Ƥӽ
뤿ᡤǥꥢɤter_tsk()ǤϥåȰ¸
ƤӽФʤᡤꥢ뤳ȤʤΤᡤ߽иǤΥ
㳰ƤӽФߥ󥰤FPUƥȤ򥹥å˳Ǽ뤿ᡤ
ѤΤʤFPU̿ȯԤ롥
ʤ¾Υ˥ǥѥå줿ϡCONTROL.FPCA'1'̵
(㳰FPUѤʤä)s16s31FPU쥸¸
Ԥ줺㳰ե졼ؤνᤷȯʤ

CONTROL.FPCAΥåȡꥢΥߥ

ꥢս꤬ʣսˤʤİǤ뤿ᡤǥѥåƬ
ϰΧCONTROL.FPCA'0'˥ꥢ롥

dispatchƤӽФؤΥ꥿󤹤ݤˤϡΥFPU
Ѥϡs16s31Ԥᡤνˤ
CONTROL.FPCA'1'˥åȤ롥

ޤEXC_RETURNˤ꡼EXC_RETURNͤˤäƥ꡼
ϡɥŪ˼ưŪCONTROL.FPCAξ֤Τǥեȥ
ˤɬפʤ

㳰ΰ

㳰FPUѤơ̾νFPUѤʤϡ
θƤӽФ CONTROL.FPCA ¸ˡ⤢뤬쥢
Ǥȹͤ뤿᥵ݡȤʤ

ABI

GCCǤ3ǽ

hard    : ư̿ѤABIFPU쥸ѡ
soft    : ư̿Ѥʤ
softfp  : ư̿Ѥ뤬ABIsoftƱ

¸Υ饤֥ȥ󥯤softfpͭ桼ޥ
ȤƥǥեȤϡhardȤ롥

ޥ

FPUƥ¸ͭޥ

TOPPERS_FPU_CONTEXT

FPUλѤͭޥ

TOPPERS_FPU_ENABLE

FPUΥƥꤹޥARMCCȹ碌ƼΥޥѤ롥
__TARGET_FPU_FPV4_SP

FPU_NO_PRESERV/FPU_NO_LAZYSTACKING/FPU_LAZYSTACKINGξϼΥޥ롥

TOPPERS_FPU_NO_PRESERV

TOPPERS_FPU_NO_LAZYSTACKING

TOPPERS_FPU_LAZYSTACKING


16. ̤
ߥåCPU㳰δط
  BASEPRIȤäȤƤ⡤CPU㳰¾㳰ȯȡ
  㳰ϼդʤᡤITRONͤʤ
  ->ƥޥ˥奢뵭ܤƨ뤫.
  ץƥ㳰ޥǽǤ뤿׷

ʾ塥
