@module
class UART2AXIS:
    def __init__(self):
        self.i_tx_en = Port(bit, 'out', 0)
        self.waddr = Port(bit3, 'out', 0)
        self.wdata = Port(bit8, 'out', 0)

        self.i_rx_en = Port(bit, 'out', 0)
        self.raddr = Port(bit3, 'out', 0)
        self.rdata = Port(bit8, 'in')

        self.term_out_tvalid = Port(bool, 'out', 0)
        self.term_out_tdata = Port(bit8, 'out', 0)
        self.term_out_tready = Port(bool, 'in', 0)

        self.append_worker(self.main)