.PHONY: build writefpga clean

SRC_TOP_SV=./src/spi_adc_dac_top.sv
SRC_MOD_SV=../../rtl/SPI_MASTER.sv
SRC_FIFOIP=./src/fifo_top/fifo_top.v
SRC_CST=./src/spi_adc_dac.cst
SRC_SDC=./src/spi_adc_dac.sdc
GW_PROJ_TCL=project.tcl
OUT_FS=./impl/pnr/spi_adc_dac.fs

build: $(OUT_FS)
$(OUT_FS) : $(GW_PROJ_TCL) $(SRC_TOP_SV) $(SRC_MOD_SV) $(SRC_FIFOIP) $(SRC_CST) $(SRC_SDC)
	gw_sh $(GW_PROJ_TCL)

$(SRC_FIFOIP):
	$(error Error! FIFO IP has not been generated. Please generate FIFO IP first following README.md)

writefpga: $(OUT_FS)
	openFPGALoader $(OUT_FS)

clean:
	$(RM) spi_adc_dac.gprj
	$(RM) spi_adc_dac.gprj.user
	$(RM) -r impl
