/***********************************************************************************************************************
 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
 **********************************************************************************************************************/

#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_

#include "fsl_common.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */

/*******************************************************************************
 ************************ BOARD_InitBootClocks function ************************
 ******************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes default configuration of clocks.
 *
 */
void BOARD_InitBootClocks(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************** Configuration BOARD_BootClockFRO12M **********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockFRO12M configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO12M_ADC0_CLOCK              0UL            /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO12M_ADC1_CLOCK              0UL            /* Clock consumers of ADC1_clock output : ADC1 */
#define BOARD_BOOTCLOCKFRO12M_CLK16K0_TOVBAT_CLOCK    0UL            /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK16K1_TOVSYS_CLOCK    0UL            /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFRO12M_CLK16K2_TOWAKE_CLOCK    0UL            /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK16K3_TOMAIN_CLOCK    0UL            /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK            0UL            /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_144M_CLOCK          144000000UL    /* Clock consumers of CLK_144M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_1M_CLOCK            0UL            /* Clock consumers of CLK_1M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_48M_CLOCK           48000000UL     /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_IN_CLOCK            0UL            /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFRO12M_CMP0FDIV_CLOCK          0UL            /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO12M_CMP0RRDIV_CLOCK         0UL            /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO12M_CMP1FDIV_CLOCK          0UL            /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO12M_CMP1RRDIV_CLOCK         0UL            /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO12M_CMP2FDIV_CLOCK          0UL            /* Clock consumers of CMP2FDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFRO12M_CMP2RRDIV_CLOCK         0UL            /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK           0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK           0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK           0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK           0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK           0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
#define BOARD_BOOTCLOCKFRO12M_DAC0_CLOCK              0UL            /* Clock consumers of DAC0_clock output : DAC0 */
#define BOARD_BOOTCLOCKFRO12M_DAC1_CLOCK              0UL            /* Clock consumers of DAC1_clock output : DAC1 */
#define BOARD_BOOTCLOCKFRO12M_DAC2_CLOCK              0UL            /* Clock consumers of DAC2_clock output : DAC2 */
#define BOARD_BOOTCLOCKFRO12M_EMVSIM0_CLOCK           0UL            /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
#define BOARD_BOOTCLOCKFRO12M_EMVSIM1_CLOCK           0UL            /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
#define BOARD_BOOTCLOCKFRO12M_ENETPTPREFCLK_CLOCK     0UL            /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
#define BOARD_BOOTCLOCKFRO12M_ENETRMII_CLOCK          0UL            /* Clock consumers of ENETRMII_clock output : ENET0 */
#define BOARD_BOOTCLOCKFRO12M_EWM_CLOCK               0UL            /* Clock consumers of EWM_clock output : EWM0 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCAN0_CLOCK          0UL            /* Clock consumers of FLEXCAN0_clock output : CAN0 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCAN1_CLOCK          0UL            /* Clock consumers of FLEXCAN1_clock output : CAN1 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM0_CLOCK         0UL            /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM1_CLOCK         0UL            /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM2_CLOCK         0UL            /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM3_CLOCK         0UL            /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM4_CLOCK         0UL            /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM5_CLOCK         0UL            /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM6_CLOCK         0UL            /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM7_CLOCK         0UL            /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM8_CLOCK         0UL            /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
#define BOARD_BOOTCLOCKFRO12M_FLEXCOMM9_CLOCK         0UL            /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
#define BOARD_BOOTCLOCKFRO12M_FLEXIO_CLOCK            0UL            /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
#define BOARD_BOOTCLOCKFRO12M_FLEXSPI_CLOCK           0UL            /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
#define BOARD_BOOTCLOCKFRO12M_FREQME_REFERENCE_CLOCK  0UL            /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO12M_FREQME_TARGET_CLOCK     0UL            /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO12M_FRO_12M_CLOCK           12000000UL     /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_DIV_CLOCK        0UL            /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_CLOCK            0UL            /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_I3C0_FCLK_CLOCK         0UL            /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_I3C0_SLOW_TC_CLOCK      0UL            /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_I3C0_SLOW_CLOCK         0UL            /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_I3C1_FCLK_CLOCK         0UL            /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
#define BOARD_BOOTCLOCKFRO12M_I3C1_SLOW_TC_CLOCK      0UL            /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
#define BOARD_BOOTCLOCKFRO12M_I3C1_SLOW_CLOCK         0UL            /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
#define BOARD_BOOTCLOCKFRO12M_LP_OSC_CLOCK            0UL            /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
#define BOARD_BOOTCLOCKFRO12M_MAIN_CLOCK              12000000UL     /* Clock consumers of MAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_MICFILFCLK_CLOCK        0UL            /* Clock consumers of MICFILFCLK_clock output : PDM */
#define BOARD_BOOTCLOCKFRO12M_OSTIMER_CLOCK           0UL            /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO12M_PLL0_CLK_CLOCK          0UL            /* Clock consumers of PLL0_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_PLL1_CLK_CLOCK          0UL            /* Clock consumers of PLL1_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_PLL_DIV_CLOCK           0UL            /* Clock consumers of PLL_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK          0UL            /* Clock consumers of PLUCLKIN_clock output : PLU0 */
#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK   0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFRO12M_SAI0_CLOCK              0UL            /* Clock consumers of SAI0_clock output : SAI0 */
#define BOARD_BOOTCLOCKFRO12M_SAI1_CLOCK              0UL            /* Clock consumers of SAI1_clock output : SAI1 */
#define BOARD_BOOTCLOCKFRO12M_FIRC_TRIM_CLOCK         0UL            /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_SIRC_TRIM_CLOCK         0UL            /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK               0UL            /* Clock consumers of SCT_clock output : SCT0 */
#define BOARD_BOOTCLOCKFRO12M_SINCFILT_CLOCK          0UL            /* Clock consumers of SINCFILT_clock output : SINC0 */
#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK          0UL            /* Clock consumers of SYSTICK0_clock output : SysTick0 */
#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK          0UL            /* Clock consumers of SYSTICK1_clock output : SysTick1 */
#define BOARD_BOOTCLOCKFRO12M_SLOW_CLOCK              3000000UL      /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK            12000000UL     /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK             0UL            /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO12M_TSI_CLOCK               0UL            /* Clock consumers of TSI_clock output : TSI0 */
#define BOARD_BOOTCLOCKFRO12M_USB_HSPLL_CLOCK         0UL            /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
#define BOARD_BOOTCLOCKFRO12M_USB_PLL_CLOCK           0UL            /* Clock consumers of USB_PLL_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_USB_CLOCK               0UL            /* Clock consumers of USB_clock output : USBFS0 */
#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK             0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO12M_WDT0_CLOCK              0UL            /* Clock consumers of WDT0_clock output : WWDT0 */
#define BOARD_BOOTCLOCKFRO12M_WDT1_CLOCK              0UL            /* Clock consumers of WDT1_clock output : WWDT1 */
#define BOARD_BOOTCLOCKFRO12M_XTAL32K0_TOVBAT_CLOCK   0UL            /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_XTAL32K1_TOVSYS_CLOCK   0UL            /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFRO12M_XTAL32K2_TOWAKE_CLOCK   0UL            /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_XTAL32K3_TOMAIN_CLOCK   0UL            /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_GDET_CLOCK              48000000UL     /* Clock consumers of gdet_clock output : GDET0, GDET1 */
#define BOARD_BOOTCLOCKFRO12M_PLL1_CLK0_CLOCK         0UL            /* Clock consumers of pll1_clk0_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_PLL1_CLK1_CLOCK         0UL            /* Clock consumers of pll1_clk1_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_TRNG_CLOCK              48000000UL     /* Clock consumers of trng_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_USDHC_CLOCK             0UL            /* Clock consumers of uSDHC_clock output : USDHC0 */


/*******************************************************************************
 * API for BOARD_BootClockFRO12M configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockFRO12M(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************* Configuration BOARD_BootClockFROHF48M *********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockFROHF48M configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFROHF48M_ADC0_CLOCK            0UL            /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFROHF48M_ADC1_CLOCK            0UL            /* Clock consumers of ADC1_clock output : ADC1 */
#define BOARD_BOOTCLOCKFROHF48M_CLK16K0_TOVBAT_CLOCK  0UL            /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK16K1_TOVSYS_CLOCK  0UL            /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF48M_CLK16K2_TOWAKE_CLOCK  0UL            /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK16K3_TOMAIN_CLOCK  0UL            /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLKOUT_CLOCK          0UL            /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK_144M_CLOCK        144000000UL    /* Clock consumers of CLK_144M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK_1M_CLOCK          0UL            /* Clock consumers of CLK_1M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK_48M_CLOCK         48000000UL     /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_CLK_IN_CLOCK          0UL            /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF48M_CMP0FDIV_CLOCK        0UL            /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFROHF48M_CMP0RRDIV_CLOCK       0UL            /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFROHF48M_CMP1FDIV_CLOCK        0UL            /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFROHF48M_CMP1RRDIV_CLOCK       0UL            /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFROHF48M_CMP2FDIV_CLOCK        0UL            /* Clock consumers of CMP2FDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFROHF48M_CMP2RRDIV_CLOCK       0UL            /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFROHF48M_CTIMER0_CLOCK         0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFROHF48M_CTIMER1_CLOCK         0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFROHF48M_CTIMER2_CLOCK         0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFROHF48M_CTIMER3_CLOCK         0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
#define BOARD_BOOTCLOCKFROHF48M_CTIMER4_CLOCK         0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
#define BOARD_BOOTCLOCKFROHF48M_DAC0_CLOCK            0UL            /* Clock consumers of DAC0_clock output : DAC0 */
#define BOARD_BOOTCLOCKFROHF48M_DAC1_CLOCK            0UL            /* Clock consumers of DAC1_clock output : DAC1 */
#define BOARD_BOOTCLOCKFROHF48M_DAC2_CLOCK            0UL            /* Clock consumers of DAC2_clock output : DAC2 */
#define BOARD_BOOTCLOCKFROHF48M_EMVSIM0_CLOCK         0UL            /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
#define BOARD_BOOTCLOCKFROHF48M_EMVSIM1_CLOCK         0UL            /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
#define BOARD_BOOTCLOCKFROHF48M_ENETPTPREFCLK_CLOCK   0UL            /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
#define BOARD_BOOTCLOCKFROHF48M_ENETRMII_CLOCK        0UL            /* Clock consumers of ENETRMII_clock output : ENET0 */
#define BOARD_BOOTCLOCKFROHF48M_EWM_CLOCK             0UL            /* Clock consumers of EWM_clock output : EWM0 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCAN0_CLOCK        0UL            /* Clock consumers of FLEXCAN0_clock output : CAN0 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCAN1_CLOCK        0UL            /* Clock consumers of FLEXCAN1_clock output : CAN1 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM0_CLOCK       0UL            /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM1_CLOCK       0UL            /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM2_CLOCK       0UL            /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM3_CLOCK       0UL            /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM4_CLOCK       0UL            /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM5_CLOCK       0UL            /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM6_CLOCK       0UL            /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM7_CLOCK       0UL            /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM8_CLOCK       0UL            /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXCOMM9_CLOCK       0UL            /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXIO_CLOCK          0UL            /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
#define BOARD_BOOTCLOCKFROHF48M_FLEXSPI_CLOCK         0UL            /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
#define BOARD_BOOTCLOCKFROHF48M_FREQME_REFERENCE_CLOCK 0UL           /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFROHF48M_FREQME_TARGET_CLOCK   0UL            /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFROHF48M_FRO_12M_CLOCK         12000000UL     /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF48M_FRO_HF_DIV_CLOCK      0UL            /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_FRO_HF_CLOCK          48000000UL     /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_I3C0_FCLK_CLOCK       0UL            /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF48M_I3C0_SLOW_TC_CLOCK    0UL            /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF48M_I3C0_SLOW_CLOCK       0UL            /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF48M_I3C1_FCLK_CLOCK       0UL            /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF48M_I3C1_SLOW_TC_CLOCK    0UL            /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF48M_I3C1_SLOW_CLOCK       0UL            /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF48M_LP_OSC_CLOCK          0UL            /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
#define BOARD_BOOTCLOCKFROHF48M_MAIN_CLOCK            48000000UL     /* Clock consumers of MAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_MICFILFCLK_CLOCK      0UL            /* Clock consumers of MICFILFCLK_clock output : PDM */
#define BOARD_BOOTCLOCKFROHF48M_OSTIMER_CLOCK         0UL            /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFROHF48M_PLL0_CLK_CLOCK        0UL            /* Clock consumers of PLL0_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_PLL1_CLK_CLOCK        0UL            /* Clock consumers of PLL1_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_PLL_DIV_CLOCK         0UL            /* Clock consumers of PLL_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_PLUCLKIN_CLOCK        0UL            /* Clock consumers of PLUCLKIN_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF48M_PLU_GLITCH_12MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF48M_PLU_GLITCH_1MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF48M_SAI0_CLOCK            0UL            /* Clock consumers of SAI0_clock output : SAI0 */
#define BOARD_BOOTCLOCKFROHF48M_SAI1_CLOCK            0UL            /* Clock consumers of SAI1_clock output : SAI1 */
#define BOARD_BOOTCLOCKFROHF48M_FIRC_TRIM_CLOCK       0UL            /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_SIRC_TRIM_CLOCK       0UL            /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_SCT_CLOCK             0UL            /* Clock consumers of SCT_clock output : SCT0 */
#define BOARD_BOOTCLOCKFROHF48M_SINCFILT_CLOCK        0UL            /* Clock consumers of SINCFILT_clock output : SINC0 */
#define BOARD_BOOTCLOCKFROHF48M_SYSTICK0_CLOCK        0UL            /* Clock consumers of SYSTICK0_clock output : SysTick0 */
#define BOARD_BOOTCLOCKFROHF48M_SYSTICK1_CLOCK        0UL            /* Clock consumers of SYSTICK1_clock output : SysTick1 */
#define BOARD_BOOTCLOCKFROHF48M_SLOW_CLOCK            12000000UL     /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
#define BOARD_BOOTCLOCKFROHF48M_SYSTEM_CLOCK          48000000UL     /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
#define BOARD_BOOTCLOCKFROHF48M_TRACE_CLOCK           0UL            /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFROHF48M_TSI_CLOCK             0UL            /* Clock consumers of TSI_clock output : TSI0 */
#define BOARD_BOOTCLOCKFROHF48M_USB_HSPLL_CLOCK       0UL            /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
#define BOARD_BOOTCLOCKFROHF48M_USB_PLL_CLOCK         0UL            /* Clock consumers of USB_PLL_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_USB_CLOCK             0UL            /* Clock consumers of USB_clock output : USBFS0 */
#define BOARD_BOOTCLOCKFROHF48M_UTICK_CLOCK           0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFROHF48M_WDT0_CLOCK            0UL            /* Clock consumers of WDT0_clock output : WWDT0 */
#define BOARD_BOOTCLOCKFROHF48M_WDT1_CLOCK            0UL            /* Clock consumers of WDT1_clock output : WWDT1 */
#define BOARD_BOOTCLOCKFROHF48M_XTAL32K0_TOVBAT_CLOCK 0UL            /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_XTAL32K1_TOVSYS_CLOCK 0UL            /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF48M_XTAL32K2_TOWAKE_CLOCK 0UL            /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_XTAL32K3_TOMAIN_CLOCK 0UL            /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_GDET_CLOCK            48000000UL     /* Clock consumers of gdet_clock output : GDET0, GDET1 */
#define BOARD_BOOTCLOCKFROHF48M_PLL1_CLK0_CLOCK       0UL            /* Clock consumers of pll1_clk0_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_PLL1_CLK1_CLOCK       0UL            /* Clock consumers of pll1_clk1_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_TRNG_CLOCK            48000000UL     /* Clock consumers of trng_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF48M_USDHC_CLOCK           0UL            /* Clock consumers of uSDHC_clock output : USDHC0 */


/*******************************************************************************
 * API for BOARD_BootClockFROHF48M configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockFROHF48M(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************* Configuration BOARD_BootClockFROHF144M ********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockFROHF144M configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFROHF144M_ADC0_CLOCK           0UL            /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFROHF144M_ADC1_CLOCK           0UL            /* Clock consumers of ADC1_clock output : ADC1 */
#define BOARD_BOOTCLOCKFROHF144M_CLK16K0_TOVBAT_CLOCK 0UL            /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK16K1_TOVSYS_CLOCK 0UL            /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF144M_CLK16K2_TOWAKE_CLOCK 0UL            /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK16K3_TOMAIN_CLOCK 0UL            /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLKOUT_CLOCK         0UL            /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK_144M_CLOCK       144000000UL    /* Clock consumers of CLK_144M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK_1M_CLOCK         0UL            /* Clock consumers of CLK_1M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK_48M_CLOCK        48000000UL     /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_CLK_IN_CLOCK         0UL            /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF144M_CMP0FDIV_CLOCK       0UL            /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFROHF144M_CMP0RRDIV_CLOCK      0UL            /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFROHF144M_CMP1FDIV_CLOCK       0UL            /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFROHF144M_CMP1RRDIV_CLOCK      0UL            /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFROHF144M_CMP2FDIV_CLOCK       0UL            /* Clock consumers of CMP2FDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFROHF144M_CMP2RRDIV_CLOCK      0UL            /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKFROHF144M_CTIMER0_CLOCK        0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFROHF144M_CTIMER1_CLOCK        0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFROHF144M_CTIMER2_CLOCK        0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFROHF144M_CTIMER3_CLOCK        0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
#define BOARD_BOOTCLOCKFROHF144M_CTIMER4_CLOCK        0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
#define BOARD_BOOTCLOCKFROHF144M_DAC0_CLOCK           0UL            /* Clock consumers of DAC0_clock output : DAC0 */
#define BOARD_BOOTCLOCKFROHF144M_DAC1_CLOCK           0UL            /* Clock consumers of DAC1_clock output : DAC1 */
#define BOARD_BOOTCLOCKFROHF144M_DAC2_CLOCK           0UL            /* Clock consumers of DAC2_clock output : DAC2 */
#define BOARD_BOOTCLOCKFROHF144M_EMVSIM0_CLOCK        0UL            /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
#define BOARD_BOOTCLOCKFROHF144M_EMVSIM1_CLOCK        0UL            /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
#define BOARD_BOOTCLOCKFROHF144M_ENETPTPREFCLK_CLOCK  0UL            /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
#define BOARD_BOOTCLOCKFROHF144M_ENETRMII_CLOCK       0UL            /* Clock consumers of ENETRMII_clock output : ENET0 */
#define BOARD_BOOTCLOCKFROHF144M_EWM_CLOCK            0UL            /* Clock consumers of EWM_clock output : EWM0 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCAN0_CLOCK       0UL            /* Clock consumers of FLEXCAN0_clock output : CAN0 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCAN1_CLOCK       0UL            /* Clock consumers of FLEXCAN1_clock output : CAN1 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM0_CLOCK      0UL            /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM1_CLOCK      0UL            /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM2_CLOCK      0UL            /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM3_CLOCK      0UL            /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM4_CLOCK      0UL            /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM5_CLOCK      0UL            /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM6_CLOCK      0UL            /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM7_CLOCK      0UL            /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM8_CLOCK      0UL            /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXCOMM9_CLOCK      0UL            /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXIO_CLOCK         0UL            /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
#define BOARD_BOOTCLOCKFROHF144M_FLEXSPI_CLOCK        0UL            /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
#define BOARD_BOOTCLOCKFROHF144M_FREQME_REFERENCE_CLOCK 0UL          /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFROHF144M_FREQME_TARGET_CLOCK  0UL            /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFROHF144M_FRO_12M_CLOCK        12000000UL     /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF144M_FRO_HF_DIV_CLOCK     0UL            /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_FRO_HF_CLOCK         144000000UL    /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_I3C0_FCLK_CLOCK      0UL            /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF144M_I3C0_SLOW_TC_CLOCK   0UL            /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF144M_I3C0_SLOW_CLOCK      0UL            /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFROHF144M_I3C1_FCLK_CLOCK      0UL            /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF144M_I3C1_SLOW_TC_CLOCK   0UL            /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF144M_I3C1_SLOW_CLOCK      0UL            /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
#define BOARD_BOOTCLOCKFROHF144M_LP_OSC_CLOCK         0UL            /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
#define BOARD_BOOTCLOCKFROHF144M_MAIN_CLOCK           144000000UL    /* Clock consumers of MAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_MICFILFCLK_CLOCK     0UL            /* Clock consumers of MICFILFCLK_clock output : PDM */
#define BOARD_BOOTCLOCKFROHF144M_OSTIMER_CLOCK        0UL            /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFROHF144M_PLL0_CLK_CLOCK       0UL            /* Clock consumers of PLL0_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_PLL1_CLK_CLOCK       0UL            /* Clock consumers of PLL1_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_PLL_DIV_CLOCK        0UL            /* Clock consumers of PLL_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_PLUCLKIN_CLOCK       0UL            /* Clock consumers of PLUCLKIN_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF144M_PLU_GLITCH_12MHZ_CLOCK 0UL          /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF144M_PLU_GLITCH_1MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKFROHF144M_SAI0_CLOCK           0UL            /* Clock consumers of SAI0_clock output : SAI0 */
#define BOARD_BOOTCLOCKFROHF144M_SAI1_CLOCK           0UL            /* Clock consumers of SAI1_clock output : SAI1 */
#define BOARD_BOOTCLOCKFROHF144M_FIRC_TRIM_CLOCK      0UL            /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_SIRC_TRIM_CLOCK      0UL            /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_SCT_CLOCK            0UL            /* Clock consumers of SCT_clock output : SCT0 */
#define BOARD_BOOTCLOCKFROHF144M_SINCFILT_CLOCK       0UL            /* Clock consumers of SINCFILT_clock output : SINC0 */
#define BOARD_BOOTCLOCKFROHF144M_SYSTICK0_CLOCK       0UL            /* Clock consumers of SYSTICK0_clock output : SysTick0 */
#define BOARD_BOOTCLOCKFROHF144M_SYSTICK1_CLOCK       0UL            /* Clock consumers of SYSTICK1_clock output : SysTick1 */
#define BOARD_BOOTCLOCKFROHF144M_SLOW_CLOCK           36000000UL     /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
#define BOARD_BOOTCLOCKFROHF144M_SYSTEM_CLOCK         144000000UL    /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
#define BOARD_BOOTCLOCKFROHF144M_TRACE_CLOCK          0UL            /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFROHF144M_TSI_CLOCK            0UL            /* Clock consumers of TSI_clock output : TSI0 */
#define BOARD_BOOTCLOCKFROHF144M_USB_HSPLL_CLOCK      0UL            /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
#define BOARD_BOOTCLOCKFROHF144M_USB_PLL_CLOCK        0UL            /* Clock consumers of USB_PLL_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_USB_CLOCK            0UL            /* Clock consumers of USB_clock output : USBFS0 */
#define BOARD_BOOTCLOCKFROHF144M_UTICK_CLOCK          0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFROHF144M_WDT0_CLOCK           0UL            /* Clock consumers of WDT0_clock output : WWDT0 */
#define BOARD_BOOTCLOCKFROHF144M_WDT1_CLOCK           0UL            /* Clock consumers of WDT1_clock output : WWDT1 */
#define BOARD_BOOTCLOCKFROHF144M_XTAL32K0_TOVBAT_CLOCK 0UL           /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_XTAL32K1_TOVSYS_CLOCK 0UL           /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKFROHF144M_XTAL32K2_TOWAKE_CLOCK 0UL           /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_XTAL32K3_TOMAIN_CLOCK 0UL           /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_GDET_CLOCK           48000000UL     /* Clock consumers of gdet_clock output : GDET0, GDET1 */
#define BOARD_BOOTCLOCKFROHF144M_PLL1_CLK0_CLOCK      0UL            /* Clock consumers of pll1_clk0_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_PLL1_CLK1_CLOCK      0UL            /* Clock consumers of pll1_clk1_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_TRNG_CLOCK           48000000UL     /* Clock consumers of trng_clock output : N/A */
#define BOARD_BOOTCLOCKFROHF144M_USDHC_CLOCK          0UL            /* Clock consumers of uSDHC_clock output : USDHC0 */


/*******************************************************************************
 * API for BOARD_BootClockFROHF144M configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockFROHF144M(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************** Configuration BOARD_BootClockPLL150M *********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockPLL150M configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKPLL150M_ADC0_CLOCK             0UL            /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKPLL150M_ADC1_CLOCK             0UL            /* Clock consumers of ADC1_clock output : ADC1 */
#define BOARD_BOOTCLOCKPLL150M_CLK16K0_TOVBAT_CLOCK   0UL            /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK16K1_TOVSYS_CLOCK   0UL            /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL150M_CLK16K2_TOWAKE_CLOCK   0UL            /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK16K3_TOMAIN_CLOCK   0UL            /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK_144M_CLOCK         144000000UL    /* Clock consumers of CLK_144M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK_1M_CLOCK           0UL            /* Clock consumers of CLK_1M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK_48M_CLOCK          48000000UL     /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_CLK_IN_CLOCK           0UL            /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL150M_CMP0FDIV_CLOCK         0UL            /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKPLL150M_CMP0RRDIV_CLOCK        0UL            /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKPLL150M_CMP1FDIV_CLOCK         0UL            /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKPLL150M_CMP1RRDIV_CLOCK        0UL            /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKPLL150M_CMP2FDIV_CLOCK         0UL            /* Clock consumers of CMP2FDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKPLL150M_CMP2RRDIV_CLOCK        0UL            /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
#define BOARD_BOOTCLOCKPLL150M_DAC0_CLOCK             0UL            /* Clock consumers of DAC0_clock output : DAC0 */
#define BOARD_BOOTCLOCKPLL150M_DAC1_CLOCK             0UL            /* Clock consumers of DAC1_clock output : DAC1 */
#define BOARD_BOOTCLOCKPLL150M_DAC2_CLOCK             0UL            /* Clock consumers of DAC2_clock output : DAC2 */
#define BOARD_BOOTCLOCKPLL150M_EMVSIM0_CLOCK          0UL            /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
#define BOARD_BOOTCLOCKPLL150M_EMVSIM1_CLOCK          0UL            /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
#define BOARD_BOOTCLOCKPLL150M_ENETPTPREFCLK_CLOCK    0UL            /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
#define BOARD_BOOTCLOCKPLL150M_ENETRMII_CLOCK         0UL            /* Clock consumers of ENETRMII_clock output : ENET0 */
#define BOARD_BOOTCLOCKPLL150M_EWM_CLOCK              0UL            /* Clock consumers of EWM_clock output : EWM0 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCAN0_CLOCK         0UL            /* Clock consumers of FLEXCAN0_clock output : CAN0 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCAN1_CLOCK         0UL            /* Clock consumers of FLEXCAN1_clock output : CAN1 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM0_CLOCK        0UL            /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM1_CLOCK        0UL            /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM2_CLOCK        0UL            /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM3_CLOCK        0UL            /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM4_CLOCK        0UL            /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM5_CLOCK        0UL            /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM6_CLOCK        0UL            /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM7_CLOCK        0UL            /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM8_CLOCK        0UL            /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
#define BOARD_BOOTCLOCKPLL150M_FLEXCOMM9_CLOCK        0UL            /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
#define BOARD_BOOTCLOCKPLL150M_FLEXIO_CLOCK           0UL            /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
#define BOARD_BOOTCLOCKPLL150M_FLEXSPI_CLOCK          0UL            /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
#define BOARD_BOOTCLOCKPLL150M_FREQME_REFERENCE_CLOCK 0UL            /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKPLL150M_FREQME_TARGET_CLOCK    0UL            /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKPLL150M_FRO_12M_CLOCK          12000000UL     /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL150M_FRO_HF_DIV_CLOCK       0UL            /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_FRO_HF_CLOCK           48000000UL     /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_I3C0_FCLK_CLOCK        0UL            /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL150M_I3C0_SLOW_TC_CLOCK     0UL            /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL150M_I3C0_SLOW_CLOCK        0UL            /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL150M_I3C1_FCLK_CLOCK        0UL            /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL150M_I3C1_SLOW_TC_CLOCK     0UL            /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL150M_I3C1_SLOW_CLOCK        0UL            /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL150M_LP_OSC_CLOCK           0UL            /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
#define BOARD_BOOTCLOCKPLL150M_MAIN_CLOCK             150000000UL    /* Clock consumers of MAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_MICFILFCLK_CLOCK       0UL            /* Clock consumers of MICFILFCLK_clock output : PDM */
#define BOARD_BOOTCLOCKPLL150M_OSTIMER_CLOCK          0UL            /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKPLL150M_PLL0_CLK_CLOCK         150000000UL    /* Clock consumers of PLL0_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_PLL1_CLK_CLOCK         0UL            /* Clock consumers of PLL1_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_PLL_DIV_CLOCK          0UL            /* Clock consumers of PLL_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL150M_SAI0_CLOCK             0UL            /* Clock consumers of SAI0_clock output : SAI0 */
#define BOARD_BOOTCLOCKPLL150M_SAI1_CLOCK             0UL            /* Clock consumers of SAI1_clock output : SAI1 */
#define BOARD_BOOTCLOCKPLL150M_FIRC_TRIM_CLOCK        0UL            /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_SIRC_TRIM_CLOCK        0UL            /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
#define BOARD_BOOTCLOCKPLL150M_SINCFILT_CLOCK         0UL            /* Clock consumers of SINCFILT_clock output : SINC0 */
#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : SysTick0 */
#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : SysTick1 */
#define BOARD_BOOTCLOCKPLL150M_SLOW_CLOCK             37500000UL     /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK           150000000UL    /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKPLL150M_TSI_CLOCK              0UL            /* Clock consumers of TSI_clock output : TSI0 */
#define BOARD_BOOTCLOCKPLL150M_USB_HSPLL_CLOCK        0UL            /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
#define BOARD_BOOTCLOCKPLL150M_USB_PLL_CLOCK          0UL            /* Clock consumers of USB_PLL_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_USB_CLOCK              0UL            /* Clock consumers of USB_clock output : USBFS0 */
#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKPLL150M_WDT0_CLOCK             0UL            /* Clock consumers of WDT0_clock output : WWDT0 */
#define BOARD_BOOTCLOCKPLL150M_WDT1_CLOCK             0UL            /* Clock consumers of WDT1_clock output : WWDT1 */
#define BOARD_BOOTCLOCKPLL150M_XTAL32K0_TOVBAT_CLOCK  0UL            /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_XTAL32K1_TOVSYS_CLOCK  0UL            /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL150M_XTAL32K2_TOWAKE_CLOCK  0UL            /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_XTAL32K3_TOMAIN_CLOCK  0UL            /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_GDET_CLOCK             48000000UL     /* Clock consumers of gdet_clock output : GDET0, GDET1 */
#define BOARD_BOOTCLOCKPLL150M_PLL1_CLK0_CLOCK        0UL            /* Clock consumers of pll1_clk0_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_PLL1_CLK1_CLOCK        0UL            /* Clock consumers of pll1_clk1_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_TRNG_CLOCK             48000000UL     /* Clock consumers of trng_clock output : N/A */
#define BOARD_BOOTCLOCKPLL150M_USDHC_CLOCK            0UL            /* Clock consumers of uSDHC_clock output : USDHC0 */


/*******************************************************************************
 * API for BOARD_BootClockPLL150M configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockPLL150M(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************** Configuration BOARD_BootClockPLL100M *********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockPLL100M configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKPLL100M_ADC0_CLOCK             0UL            /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKPLL100M_ADC1_CLOCK             0UL            /* Clock consumers of ADC1_clock output : ADC1 */
#define BOARD_BOOTCLOCKPLL100M_CLK16K0_TOVBAT_CLOCK   0UL            /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK16K1_TOVSYS_CLOCK   0UL            /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL100M_CLK16K2_TOWAKE_CLOCK   0UL            /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK16K3_TOMAIN_CLOCK   0UL            /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK_144M_CLOCK         144000000UL    /* Clock consumers of CLK_144M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK_1M_CLOCK           0UL            /* Clock consumers of CLK_1M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK_48M_CLOCK          48000000UL     /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_CLK_IN_CLOCK           24000000UL     /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL100M_CMP0FDIV_CLOCK         0UL            /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKPLL100M_CMP0RRDIV_CLOCK        0UL            /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKPLL100M_CMP1FDIV_CLOCK         0UL            /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKPLL100M_CMP1RRDIV_CLOCK        0UL            /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKPLL100M_CMP2FDIV_CLOCK         0UL            /* Clock consumers of CMP2FDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKPLL100M_CMP2RRDIV_CLOCK        0UL            /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
#define BOARD_BOOTCLOCKPLL100M_DAC0_CLOCK             0UL            /* Clock consumers of DAC0_clock output : DAC0 */
#define BOARD_BOOTCLOCKPLL100M_DAC1_CLOCK             0UL            /* Clock consumers of DAC1_clock output : DAC1 */
#define BOARD_BOOTCLOCKPLL100M_DAC2_CLOCK             0UL            /* Clock consumers of DAC2_clock output : DAC2 */
#define BOARD_BOOTCLOCKPLL100M_EMVSIM0_CLOCK          0UL            /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
#define BOARD_BOOTCLOCKPLL100M_EMVSIM1_CLOCK          0UL            /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
#define BOARD_BOOTCLOCKPLL100M_ENETPTPREFCLK_CLOCK    0UL            /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
#define BOARD_BOOTCLOCKPLL100M_ENETRMII_CLOCK         0UL            /* Clock consumers of ENETRMII_clock output : ENET0 */
#define BOARD_BOOTCLOCKPLL100M_EWM_CLOCK              0UL            /* Clock consumers of EWM_clock output : EWM0 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCAN0_CLOCK         0UL            /* Clock consumers of FLEXCAN0_clock output : CAN0 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCAN1_CLOCK         0UL            /* Clock consumers of FLEXCAN1_clock output : CAN1 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM0_CLOCK        0UL            /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM1_CLOCK        0UL            /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM2_CLOCK        0UL            /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM3_CLOCK        0UL            /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM4_CLOCK        0UL            /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM5_CLOCK        0UL            /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM6_CLOCK        0UL            /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM7_CLOCK        0UL            /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM8_CLOCK        0UL            /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
#define BOARD_BOOTCLOCKPLL100M_FLEXCOMM9_CLOCK        0UL            /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
#define BOARD_BOOTCLOCKPLL100M_FLEXIO_CLOCK           0UL            /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
#define BOARD_BOOTCLOCKPLL100M_FLEXSPI_CLOCK          0UL            /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
#define BOARD_BOOTCLOCKPLL100M_FREQME_REFERENCE_CLOCK 0UL            /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKPLL100M_FREQME_TARGET_CLOCK    0UL            /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKPLL100M_FRO_12M_CLOCK          12000000UL     /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL100M_FRO_HF_DIV_CLOCK       0UL            /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_FRO_HF_CLOCK           0UL            /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_I3C0_FCLK_CLOCK        0UL            /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL100M_I3C0_SLOW_TC_CLOCK     0UL            /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL100M_I3C0_SLOW_CLOCK        0UL            /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKPLL100M_I3C1_FCLK_CLOCK        0UL            /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL100M_I3C1_SLOW_TC_CLOCK     0UL            /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL100M_I3C1_SLOW_CLOCK        0UL            /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
#define BOARD_BOOTCLOCKPLL100M_LP_OSC_CLOCK           0UL            /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
#define BOARD_BOOTCLOCKPLL100M_MAIN_CLOCK             100000000UL    /* Clock consumers of MAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_MICFILFCLK_CLOCK       0UL            /* Clock consumers of MICFILFCLK_clock output : PDM */
#define BOARD_BOOTCLOCKPLL100M_OSTIMER_CLOCK          0UL            /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKPLL100M_PLL0_CLK_CLOCK         0UL            /* Clock consumers of PLL0_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_PLL1_CLK_CLOCK         100000000UL    /* Clock consumers of PLL1_CLK_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_PLL_DIV_CLOCK          0UL            /* Clock consumers of PLL_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
#define BOARD_BOOTCLOCKPLL100M_SAI0_CLOCK             0UL            /* Clock consumers of SAI0_clock output : SAI0 */
#define BOARD_BOOTCLOCKPLL100M_SAI1_CLOCK             0UL            /* Clock consumers of SAI1_clock output : SAI1 */
#define BOARD_BOOTCLOCKPLL100M_FIRC_TRIM_CLOCK        0UL            /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_SIRC_TRIM_CLOCK        0UL            /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
#define BOARD_BOOTCLOCKPLL100M_SINCFILT_CLOCK         0UL            /* Clock consumers of SINCFILT_clock output : SINC0 */
#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : SysTick0 */
#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : SysTick1 */
#define BOARD_BOOTCLOCKPLL100M_SLOW_CLOCK             25000000UL     /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK           100000000UL    /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKPLL100M_TSI_CLOCK              0UL            /* Clock consumers of TSI_clock output : TSI0 */
#define BOARD_BOOTCLOCKPLL100M_USB_HSPLL_CLOCK        0UL            /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
#define BOARD_BOOTCLOCKPLL100M_USB_PLL_CLOCK          0UL            /* Clock consumers of USB_PLL_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_USB_CLOCK              0UL            /* Clock consumers of USB_clock output : USBFS0 */
#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKPLL100M_WDT0_CLOCK             0UL            /* Clock consumers of WDT0_clock output : WWDT0 */
#define BOARD_BOOTCLOCKPLL100M_WDT1_CLOCK             0UL            /* Clock consumers of WDT1_clock output : WWDT1 */
#define BOARD_BOOTCLOCKPLL100M_XTAL32K0_TOVBAT_CLOCK  0UL            /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_XTAL32K1_TOVSYS_CLOCK  0UL            /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
#define BOARD_BOOTCLOCKPLL100M_XTAL32K2_TOWAKE_CLOCK  0UL            /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_XTAL32K3_TOMAIN_CLOCK  0UL            /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_GDET_CLOCK             48000000UL     /* Clock consumers of gdet_clock output : GDET0, GDET1 */
#define BOARD_BOOTCLOCKPLL100M_PLL1_CLK0_CLOCK        0UL            /* Clock consumers of pll1_clk0_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_PLL1_CLK1_CLOCK        0UL            /* Clock consumers of pll1_clk1_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_TRNG_CLOCK             48000000UL     /* Clock consumers of trng_clock output : N/A */
#define BOARD_BOOTCLOCKPLL100M_USDHC_CLOCK            0UL            /* Clock consumers of uSDHC_clock output : USDHC0 */


/*******************************************************************************
 * API for BOARD_BootClockPLL100M configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockPLL100M(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

#endif /* _CLOCK_CONFIG_H_ */

