Problem 1: The SOC Flow
Current HDL’s do not allow easy hardware software tradeoffs.
- C/C++ is mostly used as a system level description and in algorithm development
- No automatic path from C to HDL exists
- limits the amount of what-if-analysis that can be done
- problems in the transfer between software & hardware design teams
C/C++ lacks hardware design specific datatypes
VHDL/Verilog is not very suited for algorithm design.