ARTICLES USB 2.0 Printed Circuit Board Design Routing the USB Data Signal Compared to the 12 Mbits/s speed of USB 1.1, 480 Mbits/s is intimidating. Luckily, routing the D+ and D- lines doesn't require an RF specialist. By following some simple design rules, it is not difficult to achieve excellent signal quality. To avoid reflections and noise, the first design rule to is to give D+ and D- a differential impedance of 90 ohms. The proper board stack-up for a 1.6 mm, 4-layer PCB is shown in Figure 6. D+ and D- are routed above the GND plane. The line widths and spacing of the D+ and D- traces must also be set. The line width of each trace should be 0.4 mm, with 0.18 mm of space between the traces. For other board sizes, check with your PCB manufacturer for the proper PCB stack-up, line width, and line spacing. PCB manufacturers will also test impedance for you before the boards leave their shop. The GND plane should be one solid extent. Avoid splitting the plane. If splitting the GND plane is necessary, DO NOT split it underneath D+ and D-. Figure 6: board stack-up for a 1.6 mm, 4-layer PCB This is a typical stack-up to achieve 90-ohm differential impedance on a 4-layer, 1.6 mm PCB. D+ and D- are required to have a trace width of 0.4 mm and trace spacing of 0.18 mm. PCB manufacturers can recommend the proper stack-up for controlled impedance with other board dimensions. D+ and D- should be matched in length (within 2.5 mm of each other) to avoid signal skewing. Signal skewing can result in the crossover voltage being affected in signal integrity tests. The USB 2.0 specification allows for 1 ns of signal propagation time between the USB connector and transceiver so the signal trace lengths must also be kept under 75 mm (20-30 mm is recommended). Routing D+ and D- through vias produces discontinuities in trace impedance, which results in signal reflections. This should be avoided. Series termination resistors, if required for the selected USB chip, should be placed as close as possible to the transceiver pins. Other passive components that connect to D+ and D- should have their pads as close as possible, too. Long stubs from the signal lines to the pads cause reflections that affect signal quality. These types of discontinuities produce noise that will not only make it more difficult to pass compliance testing, but the high frequency signal components also increase RF emissions and make it more difficult to pass EMC testing later. It's much easier to make a clean design from scratch than it is to fix a noisy design later! To further reduce noise, place the USB connector on a peninsula. This is accomplished by cutting the VCC and GND planes around the connector except for in the location where D+ and D- are routed. Of course, you should also keep clock traces and other high-frequency signals away from the D+ and D- traces. The ideal board layout of D+ and D- is shown in Figure 7. It demonstrates all of the rules described above. Layers 1 and 4 are the signal layers, with D+ and D- routed on layer 1. Layer 2 is the GND plane and layer 3 is the VCC plane. Notice that the GND plane is solid with no splits except for the peninsula around the USB connector. Figure 7: ideal board layout of D+ and D- This shows the ideal routing of D+ and D- from the connector to USB chip. Notice how the pads for the series and pull-up resistors are on top of the signal traces and are kept close to the USB chip. Layer 2, the GND plane, is solid for proper differential impedance of D+ and D-. To ARTICLE Top page <<Former / Next>> To DESIGN WAVE MAGAZINE's Homepage (English) To CQ Publishing's Homepage (Japanese) Copyright(C) 1996-2001 CQ Publishing Co., Ltd.