00001 #include "afw.h"
00002 #include <signal.h>
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00010
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00012
00013 namespace afw{
00014
00015
00016
00017
00018
00019 void Init1836(void)
00020 {
00021 int i;
00022 int j;
00023 static unsigned char ucActive_LED = 0x01;
00024
00025
00026 *pFlashA_PortA_Data &= ~ucActive_LED;
00027 ssync();
00028
00029
00030 for (i=0; i<1000000; i++)
00031 asm volatile("nop;");
00032
00033
00034 *pFlashA_PortA_Data |= ucActive_LED;
00035 ssync();
00036
00037
00038 for (i=0; i<1000000; i++)
00039 asm volatile("nop;");
00040
00041
00042 *pSPI_FLG = FLS4;
00043
00044 *pSPI_BAUD = 16;
00045
00046
00047 *pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;
00048
00049
00050
00051 *pDMA5_PERIPHERAL_MAP = 0x5000;
00052
00053
00054
00055 *pDMA5_CONFIG = WDSIZE_16;
00056
00057 *pDMA5_START_ADDR = (void *)sCodec1836TxRegs;
00058
00059 *pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
00060
00061 *pDMA5_X_MODIFY = 2;
00062
00063
00064 *pDMA5_CONFIG |= DMAEN;
00065
00066 *pSPI_CTL |= SPE;
00067
00068
00069 for (j=0; j<1000000; j++)
00070 asm volatile ("nop;");
00071
00072
00073 *pSPI_CTL = 0x0000;
00074 }
00075
00076
00077
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00086
00087
00088
00089
00090 void Init_Sport0(void)
00091 {
00092
00093
00094
00095 *pSPORT0_RCR1 = RFSR;
00096 *pSPORT0_RCR2 = SLEN_32;
00097
00098
00099
00100
00101 *pSPORT0_TCR1 = TFSR;
00102 *pSPORT0_TCR2 = SLEN_32;
00103
00104
00105 *pSPORT0_MTCS0 = 0x000000FF;
00106 *pSPORT0_MRCS0 = 0x000000FF;
00107
00108
00109 *pSPORT0_MCMC1 = 0x0000;
00110 *pSPORT0_MCMC2 = 0x101c;
00111 }
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123 void Init_DMA(void)
00124 {
00125 int i, field;
00126
00127
00128
00129 *pDMA1_PERIPHERAL_MAP = 0x1000;
00130
00131
00132
00133 *pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | DI_SEL | FLOW_Autobuffer | DMA2D ;
00134
00135 *pDMA1_START_ADDR = (void *)iRxBuffer1;
00136
00137 *pDMA1_X_COUNT = SLOT_PER_SAMPLE * SAMPLES_PER_INTR;
00138
00139 *pDMA1_X_MODIFY = sizeof(int);
00140
00141 *pDMA1_Y_COUNT = INTR_PER_BUFFER;
00142
00143 *pDMA1_Y_MODIFY = sizeof(int);
00144
00145
00146
00147 *pDMA2_PERIPHERAL_MAP = 0x2000;
00148
00149
00150
00151 *pDMA2_CONFIG = WDSIZE_32 | FLOW_Autobuffer | DMA2D;
00152
00153 *pDMA2_START_ADDR = (void *)iTxBuffer1;
00154
00155 *pDMA2_X_COUNT = SLOT_PER_SAMPLE * SAMPLES_PER_INTR;
00156
00157 *pDMA2_X_MODIFY = sizeof(int);
00158
00159 *pDMA2_Y_COUNT = INTR_PER_BUFFER;
00160
00161 *pDMA2_Y_MODIFY = sizeof(int);
00162
00163 for ( i=0; i<SAMPLES_PER_INTR; i++ ){
00164 for ( field=0; field<INTR_PER_BUFFER; field ++ ){
00165
00166 iRxBuffer1[field][i][INTERNAL_ADC_L0] = 0;
00167 iRxBuffer1[field][i][INTERNAL_ADC_R0] = 0;
00168 iRxBuffer1[field][i][INTERNAL_ADC_L1] = 0;
00169 iRxBuffer1[field][i][INTERNAL_ADC_R1] = 0;
00170 iTxBuffer1[field][i][INTERNAL_DAC_L0] = 0;
00171 iTxBuffer1[field][i][INTERNAL_DAC_R0] = 0;
00172 iTxBuffer1[field][i][INTERNAL_DAC_L1] = 0;
00173 iTxBuffer1[field][i][INTERNAL_DAC_R1] = 0;
00174 iTxBuffer1[field][i][INTERNAL_DAC_L2] = 0;
00175 iTxBuffer1[field][i][INTERNAL_DAC_R2] = 0;
00176 }
00177 }
00178 }
00179
00180
00181
00182
00183
00184
00185 void Init_Sport_Interrupts(void)
00186 {
00187
00188 *pSIC_IMASK = 0x00000200;
00189 ssync();
00190 }
00191
00192
00193 void start(void)
00194 {
00195
00196 *pDMA2_CONFIG |= DMAEN;
00197 *pDMA1_CONFIG |= DMAEN;
00198
00199
00200 *pSPORT0_TCR1 |= TSPEN;
00201 *pSPORT0_RCR1 |= RSPEN;
00202 }
00203
00204 void init(void)
00205 {
00206 Init1836();
00207 Init_Sport0();
00208 Init_DMA();
00209 Init_Sport_Interrupts();
00210
00211 initProcessData( SAMPLES_PER_INTR );
00212 }
00213
00214
00215
00216
00217
00218
00219
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00221
00222
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00237
00238
00239 bool ISR( void )
00240 {
00241 static int field = 2;
00242 short leftIn[SAMPLES_PER_INTR], rightIn[SAMPLES_PER_INTR];
00243 short leftOut[SAMPLES_PER_INTR], rightOut[SAMPLES_PER_INTR];
00244
00245 if ( *pSIC_ISR & DMA1_IRQ ){
00246
00247 *pDMA1_IRQ_STATUS = 0x0001;
00248
00249
00250 if ( 2 == *pDMA2_CURR_Y_COUNT )
00251 field = 0;
00252 else
00253 field ++;
00254
00255 for ( int i=0; i<SAMPLES_PER_INTR; i++ ){
00256
00257 leftIn[i] = iRxBuffer1[field][i][INTERNAL_ADC_L0] >> 16;
00258 rightIn[i] = iRxBuffer1[field][i][INTERNAL_ADC_R0] >> 16;
00259 }
00260
00261 processData( leftIn, rightIn, leftOut, rightOut, SAMPLES_PER_INTR );
00262
00263 for ( int i=0; i<SAMPLES_PER_INTR; i++ ){
00264
00265 iTxBuffer1[field][i][INTERNAL_DAC_L0] = leftOut[i] << 16;
00266 iTxBuffer1[field][i][INTERNAL_DAC_R0] = rightOut[i] << 16;
00267 }
00268 return true;
00269 }
00270 else
00271 return false;
00272 }
00273
00274
00275
00276
00277
00278
00279
00280
00281 volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] =
00282 {
00283 DAC_CONTROL_1 | 0x000,
00284 DAC_CONTROL_2 | 0x000,
00285 DAC_VOLUME_0 | 0x3ff,
00286 DAC_VOLUME_1 | 0x3ff,
00287 DAC_VOLUME_2 | 0x3ff,
00288 DAC_VOLUME_3 | 0x3ff,
00289 DAC_VOLUME_4 | 0x3ff,
00290 DAC_VOLUME_5 | 0x3ff,
00291 ADC_CONTROL_1 | 0x000,
00292 ADC_CONTROL_2 | 0x180,
00293 ADC_CONTROL_3 | 0x000
00294
00295 };
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306 volatile int iTxBuffer1[INTR_PER_BUFFER][SAMPLES_PER_INTR][SLOT_PER_SAMPLE];
00307
00308
00309
00310
00311
00312
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00314
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00316
00317
00318 volatile int iRxBuffer1[INTR_PER_BUFFER][SAMPLES_PER_INTR][SLOT_PER_SAMPLE];
00319
00320
00321
00322 }