LYNX_DVI Project Status | |||
Project File: | lynx_dvi.ise | Current State: | Programming File Generated |
Module Name: | lynx_dvi |
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No Errors |
Target Device: | xc3s50an-4tqg144 |
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94 Warnings |
Product Version: | ISE 9.2.04i |
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? 2 20 12:11:13 2010 |
LYNX_DVI Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 199 | 1,408 | 14% | |
Number of 4 input LUTs | 383 | 1,408 | 27% | |
Logic Distribution | ||||
Number of occupied Slices | 291 | 704 | 41% | |
Number of Slices containing only related logic | 291 | 291 | 100% | |
Number of Slices containing unrelated logic | 0 | 291 | 0% | |
Total Number of 4 input LUTs | 392 | 1,408 | 27% | |
Number used as logic | 383 | |||
Number used as a route-thru | 9 | |||
Number of bonded IOBs | 54 | 108 | 50% | |
IOB Flip Flops | 27 | |||
IOB Master Pads | 8 | |||
IOB Slave Pads | 8 | |||
Number of ODDR2s used | 8 | |||
Number of GCLKs | 2 | 24 | 8% | |
Number of DCMs | 1 | 2 | 50% | |
Total equivalent gate count for design | 11,798 | |||
Additional JTAG gate count for IOBs | 2,592 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | ? 2 19 18:26:45 2010 | 0 | 50 Warnings | 9 Infos |
Translation Report | Current | ? 2 19 18:26:51 2010 | 0 | 10 Warnings | 1 Info |
Map Report | Current | ? 2 19 18:27:00 2010 | 0 | 22 Warnings | 5 Infos |
Place and Route Report | Current | ? 2 19 18:27:13 2010 | 0 | 12 Warnings | 2 Infos |
Static Timing Report | Current | ? 2 19 18:27:17 2010 | 0 | 0 | 2 Infos |
Bitgen Report | Current | ? 2 19 18:27:24 2010 | 0 | 0 | 0 |