;Copyright 2004 Ogiyama Masao TITLE "ON/OFFޮ" LIST P=PIC12F675 LIST N=250 ; 1 2 3 4 5 6 7 ;234567890123456789012345678901234567890123456789012345678901234567890123 ; * * * ;LABEL CMD OPERAND COMMENT ; REV DATE COMMENT ; 01-02 2004.07.23 ; ; Watch Dog (7-33)ms x 4 = (28-132)ms ;--------------------------------- Register Definitions ----------------- W EQU H'0000' F EQU H'0001' ; INDF EQU H'0000' ; Indirect Addressing TMR0 EQU H'0001' ; Timer 0 PCL EQU H'0002' ; Program Counter Low STATUS EQU H'0003' ; Status Reg. FSR EQU H'0004' ; Special Function Reg. GPIO EQU H'0005' ; Port PCLATH EQU H'000A' ; Program Counter Latch hi INTCON EQU H'000B' ; Interrupt Control PIR1 EQU H'000C' ; Interrupt Flag 1 TMR1L EQU H'000E' ; Timer 1 Low TMR1H EQU H'000F' ; Timer 1 Hi T1CON EQU H'0010' ; Timer 1 Control CMCON EQU H'0019' ; ADRESH EQU H'001E' ; ADC Reg. Hi ADCON0 EQU H'001F' ; ADC Control 0 ; OPTION_REG EQU H'0081' ; Option Reg. TRISIO EQU H'0085' ; Port Control PIE1 EQU H'008C' ; Interrupt Enable 1 PCON EQU H'008E' ; Power Control OSCCAL EQU H'0090' ; WPU EQU H'0095' ; IOC EQU H'0096' ; VRCON EQU H'0099' ; EEDATA EQU H'009A' ; EEROM DATA EEADR EQU H'009B' ; EEROM ADR EECON1 EQU H'009C' ; EEROM Condition 1 EECON2 EQU H'009D' ; EEROM Condition 2 ADRESL EQU H'009E' ; ANSEL EQU H'009F' ; ;--------------------------------- STATUS Bits [03,83] ----------------- IRP EQU H'7' ; BANK Sel.ݾ¼ò "0" RP1 EQU H'6' ; BANK Sel. "0" RP0 EQU H'5' ; .. 0:BANK0 1:BANK1 NOT_TO EQU H'4' ; ѱ 0:WatchDog 1:PowerON NOT_PD EQU H'3' ; ܰ޳ 0:SLEEP 1:PowerON Z EQU H'2' ; 1: DC EQU H'1' ; ޼ޯķذ 1: C EQU H'0' ; ذ 1: ;--------------------------------- INTCON Bits [0B,8B] ----------------- GIE EQU H'7' ; IRQ 1:Enabe PEIE EQU H'6' ; I/O IRQ 1:Enable T0IE EQU H'5' ; Timer 0 IRQ 1:Enable INTE EQU H'4' ; GP2/INT IRQ 1:Enable GPIE EQU H'3' ; GP ߰ IRQ 1:Enable T0IF EQU H'2' ; Timer 0 OVF 1: INTF EQU H'1' ; GP2/INT IRQ 1: GPIF EQU H'0' ; GP ߰ IRQ 1: ;--------------------------------- PIR1 Bits [0C] -------------------- EEIF EQU H'7' ; EEPROM WT END 1:End ADIF EQU H'6' ; A/D خ 1:خ CMIF EQU H'3' ; ڰ 1:ݶ TMR1IF EQU H'0' ; TMR1 OVF 1:ʯ ;--------------------------------- T1CON Bits [10] -------------------- TMR1GE EQU H'6' ; TMR 1 T1G۰ 1:۰ T1CKPS1 EQU H'5' ; TMR 1 ؽ T1CKPS0 EQU H'4' ; TMR 1 ؽ T1OSCEN EQU H'3' ; TMR 1 OSC CONT 1:OSC ޳ NOT_T1SYNC EQU H'2' ; TMR 1 EXT CLK ޳ 1: ޳ TMR1CS EQU H'1' ; TMR 1 CLK Souce 1:RC0/.. TMR1ON EQU H'0' ; TMR 1 ޳ 1:޳ ;--------------------------------- ADCON0 Bits [1F] -------------------- ADFM EQU H'7' ; A/D خ 1:з VCFG EQU H'6' ; Ref Sel. 1:VRef 0:Vdd CHS1 EQU H'3' ; CH Sel. CHS0 EQU H'2' ; .. GO EQU H'1' ; A/D Status GO NOT_DONE EQU H'1' ; GO_DONE EQU H'1' ; ADON EQU H'0' ; A/D ON 1:ޯ ;--------------------------------- OPTION_REG [81] -------------------- NOT_GPPU EQU H'7' ; GPIO Pullup 0: INTEDG EQU H'6' ; GP2/INT Edge 0: T0CS EQU H'5' ; TOCKI Select 0:Ų T0SE EQU H'4' ; Timer Edge 0: +1 PSA EQU H'3' ; ؽ 0:Timer0 1:WDT PS2 EQU H'2' ; ؽ Rate PS1 EQU H'1' ; .. PS0 EQU H'0' ; .. ;--------------------------------- PIE1 Bits [8C] -------------------- EEIEE EQU H'7' ; EPROM WT END IRQ 1:Enable ADIE EQU H'6' ; A/D IRQ 1:Enable CMIE EQU H'3' ; ڰ IRQ : Enable TMR1IE EQU H'0' ; TMR1 OVF IRQ 1:Enable ;--------------------------------- ANSEL [9F] -------------------- ADCS2 EQU H'6' ; CLK Sel. ADCS1 EQU H'5' ; .. ADCS0 EQU H'4' ; .. ANS3 EQU H'3' ; Analog Sel 3 1:Analog 0:Digital ANS2 EQU H'2' ; 2 ANS1 EQU H'1' ; 1 ANS0 EQU H'0' ; 0 ;--------------------------------- RAM Definition ----------------------- __MAXRAM H'FF' __BADRAM H'06'-H'09',H'0D',H'11'-H'18',H'1A'-H'1D',H'60'-H'7F' __BADRAM H'86'-H'89',H'8D',H'8F',H'91'-H'94',H'97'-H'98' __BADRAM H'E0'-H'FF' ;--------------------------------- Configuration Bits ------------------- __CONFIG _INTRC_NCL & _PWRTE_ON & _MCLRE_OFF & _WDT_ON ; 432109876543210 _CPD_ON EQU H'3EFF' ; EEPROM ø ON 0xxxxxxxx _CPD_OFF EQU H'3FFF' ; EEPROM ø OFF 1xxxxxxxx _CP_ON EQU H'3F7F' ; ø x0xxxxxxx _CP_OFF EQU H'3FFF' ; ø Ų x1xxxxxxx _BODEN_ON EQU H'3FFF' ; ׳ݱ ON xx1xxxxxx _BODEN_OFF EQU H'3FBF' ; ׳ݱ OFF xx0xxxxxx _MCLRE_ON EQU H'3FFF' ; 4 Pin=MCLR xxx1xxxxx _MCLRE_OFF EQU H'3FDF' ; 4 Pin=GP3 xxx0xxxxx _PWRTE_ON EQU H'3FEF' ; ܰϰ Enable xxxx0xxxx _PWRTE_OFF EQU H'3FFF' ; ܰϰ OFF xxxx1xxxx _WDT_ON EQU H'3FFF' ; Watch Dog Enable xxxxx1xxx _WDT_OFF EQU H'3FF7' ; Watch Dog OFF xxxxx0xxx _LP_OSC EQU H'3FF8' ; LP < 200 KHz xxxxxx000 _XT_OSC EQU H'3FF9' ; XT < 4 MHz xxxxxx001 _HS_OSC EQU H'3FFA' ; HS 4 < 20 MHz xxxxxx010 _EC_OSC EQU H'3FFB' ; xxxxxx011 _INTRC_NCL EQU H'3FFC' ; _INTRC_OSC_NOCLKOUT xxxxxx100 _INTRC_CLO EQU H'3FFD' ; _INTRC_OSC_CLKOUT xxxxxx101 _EXTRC_NCL EQU H'3FFE' ; _EXTRC_OSC_NOCLKOUT xxxxxx110 _EXTRC_CLO EQU H'3FFF' ; _EXTRC_OSC_CLKOUT xxxxxx111 ;--------------------------------- I/O Port ----------------------------- ;Pin GP3 Input ; 1 VDD +5V ; 2 CLKIN ,OSC1,T1CKI, , GP5 -> ײ ( ) ; 3 CLKOUT ,OSC2,T1G ,AN3, GP4 -> ( ) ; 4 VPP ,MCLR, , , GP3 <- ; 5 COUT ,INT ,T0CKI,AN2, GP2 -> ( ) ; 6 ICSPCLK,VREF,CIN- ,AN1, GP1 <- ò VR ; 7 ICSPDAT, ,CIN+ ,AN0, GP0 <- н Th ; 8 VSS GND ;------------------------------------------------------------------------ ; General Purpose Registers (H'0020' -> H'005F') ORG H'0020' ; CLR_T_ADR RES 1 ; RAM Top ADR V_VRT_H EQU CLR_T_ADR ; VR ݱ H V_VRT_L RES 1 ; .. L V_THM_H RES 1 ; н ݱ H V_THM_L RES 1 ; .. L C_VRT RES 1 ; VR C_VRT_W1 RES 1 ; .. WK C_NOW RES 1 ; н VR C_LOW RES 1 ; Lower Limit (30-70C) C_UP RES 1 ; Upper Limit (+ 2-12C) HT_NOW RES 1 ; ˰ خ Now 00:ON 20:OFF HT_TAR RES 1 ; .. Target HT_CNT RES 1 ; .. ; CONV_H RES 1 ; CONV Sub WK CONV_L RES 1 ; CONV_C RES 1 ; CONV_C_WK RES 1 ; CONV_C_TH RES 1 ; CONV_C_TL RES 1 ; ; TIM_WK_1 RES 1 ; Timer WK TIM_WK_2 RES 1 ; Timer WK ; CLR_E_ADR EQU H'005F' ; RAM End ADR ;------------------------------------------------------------------------ ORG H'0000' ; GOTO MAIN ; Power ON ; ORG H'0004' ; GOTO IRQ ; IRQ ;------------------------------------------------------------------------ ORG H'0010' DT H'12' ; REV DT H'20',H'04' ; DATE (YYYY) DT H'07',H'23' ; DATE (MMDD) ;------------------------------------------------------------------------ ; ޶ ݼ 502AT-2 2K 5Vٱ TH_TBL ADDWF PCL,F ; DT H'02',H'10' ; 50C ; DT H'02',H'08' ; 51 DT H'02',H'00' ; 52 DT H'01',H'F8' ; 53 DT H'01',H'F0' ; 54 DT H'01',H'E8' ; 55 DT H'01',H'E0' ; 56 DT H'01',H'D9' ; 57 DT H'01',H'D1' ; 58 DT H'01',H'C9' ; 59 DT H'01',H'C1' ; 60 ; DT H'01',H'BA' ; 61 DT H'01',H'B2' ; 62 DT H'01',H'AB' ; 63 DT H'01',H'A4' ; 64 DT H'01',H'9C' ; 65 DT H'01',H'95' ; 66 DT H'01',H'8E' ; 67 DT H'01',H'87' ; 68 DT H'01',H'80' ; 69 DT H'01',H'79' ; 70 ; DT H'01',H'72' ; 71 DT H'01',H'6C' ; 72 DT H'01',H'65' ; 73 DT H'01',H'5E' ; 74 DT H'01',H'58' ; 75 DT H'01',H'52' ; 76 DT H'01',H'4B' ; 77 DT H'01',H'45' ; 78 DT H'01',H'3F' ; 79 DT H'01',H'39' ; 80 ; DT H'01',H'33' ; 81 DT H'01',H'2E' ; 82 DT H'01',H'28' ; 83 DT H'01',H'22' ; 84 DT H'01',H'1D' ; 85 DT H'01',H'17' ; 86 DT H'01',H'12' ; 87 DT H'01',H'0D' ; 88 DT H'01',H'08' ; 89 DT H'01',H'02' ; 90 ; DT H'00',H'FE' ; 91 DT H'00',H'F9' ; 92 DT H'00',H'F4' ; 93 DT H'00',H'EF' ; 94 DT H'00',H'EB' ; 95 DT H'00',H'E6' ; 96 DT H'00',H'E2' ; 97 DT H'00',H'DD' ; 98 DT H'00',H'D9' ; 99 DT H'00',H'D5' ; 100 ; DT H'00',H'00' ; 101 Dummy ;------------------------------------------------------------------------ ; 0V(CCW:0)-5V(CW:10) VR_TBL ADDWF PCL,F ; Code A/D ݲ (HEX) ò DT H'00',H'33' ; 00 0.0 - 51.2(033) -> 50.0C DT H'00',H'99' ; 01 51.3 - 153.5(099) 55.0 DT H'00',H'FF' ; 02 153.6 - 255.8(0FF) 60.0 DT H'01',H'66' ; 03 255.9 - 358.1(166) 65.0 DT H'01',H'CC' ; 04 358.1 - 460.4(1CC) 70.0 DT H'02',H'32' ; 05 460.5 - 562.7(232) 75.0 DT H'02',H'99' ; 06 562.8 - 665.0(299) 80.0 DT H'02',H'FF' ; 07 665.1 - 767.3(2FF) 85.0 DT H'03',H'65' ; 08 767.4 - 869.6(365) 90.0 DT H'03',H'CB' ; 09 869.7 - 971.9(3CB) 95.0 DT H'03',H'FF' ; 10 972.0 -1023.1(3FF) 100.0 ; ; ۸ ADR Max 100 ;------------------------------------------------------------------------ MAIN ; ; 543210 MOVLW B'100000' ; Out (ײ) = Hi MOVWF GPIO ; BSF STATUS,RP0 ;|BANK = 1(01) MOVLW B'10001010' ;|Pull up , WDT , x4 MOVWF OPTION_REG ;| MOVLW B'001011' ;| MOVWF TRISIO ;|DIR BCF STATUS,RP0 ;|Bank 0(00) ; CLRWDT ; Watch Dog ر ; == Initialize == MOVLW CLR_T_ADR ; Top ADR MOVWF FSR ; MAIN_010 CLRF INDF ; INCF FSR,F ; MOVF FSR,W ; SUBLW CLR_E_ADR ; End ADR BTFSS STATUS,Z ; FSR = xxxx -> Skip GOTO MAIN_010 ; -> Loop ;------------------------------------------------------------------------ ; 40 ż ķ خ (ɲ ) ; ; 1.HT_Now = OFF ; HT_TAR = OFF ; I/O = OFF ; 2.HT_CNT = 40 ; 3.VR ݱ ذ VR ݶ ; V_VRT -> C_VRT ; 4.н ݱ ذ VC ݶ ; V_THM -> C_NOW ; 5.C_VRT Lower Limit TEMP (C_LOW) ; Upper Limit TEMP (C_UP ) ; 6.C_NOW C_LOW,C_UP ˶ ; HT_Now = OFF ޱ ; C_NOW < C_LOW --> HT_TAR = ON ; HT_Now = ON ޱ ; C_NOW > C_UP ---> HT_TAR = OFF ; 7.Timer 10ms ; 8.if HT_Now = HT_TAR --> 2. ; 9.HT_CNT -1 00 ------> 3. ; = 00 ------> HT_TAR -> HT_Now -> I/O -> 2. ; ; 543210 MOVLW B'100000' ; MOVWF HT_NOW ; ˰ Now = OFF MOVWF HT_TAR ; Target = OFF MOVWF GPIO ; I/O ; BSF STATUS,RP0 ;|BANK = 1(01) MOVLW B'00110011' ;|CLK=RC A/D=CH0,1 MOVWF ANSEL ;| BCF STATUS,RP0 ;|BANK = 0(00) ; MOVLW B'00000111' ; MOVWF CMCON ; ڰ OFF ; MAIN_050 MOVLW D'40' ; = 40 MOVWF HT_CNT ; ; ; 76543210 == VR == MAIN_100 MOVLW B'10000101' ; з޽,VDD,CH1,ADC_ON <-- Loop MOVWF ADCON0 ; ; CALL TIM_100U ; Aqu Time 100us ; BSF ADCON0,1 ; A/D Start (GO) ; MAIN_110 BTFSC ADCON0,1 ; A/D = End (DONE) GOTO MAIN_110 ; = -> Loop ; MOVF ADRESH,W ; A/D Hi MOVWF V_VRT_H ; MOVWF CONV_H ; BSF STATUS,RP0 ;|BANK = 1(01) MOVF ADRESL,W ;|A/D Low BCF STATUS,RP0 ;|BANK = 0(00) MOVWF V_VRT_L ; MOVWF CONV_L ; ; CALL CONV_VR ; CONV_H,L(ݱ) -> W Reg() MOVWF C_VRT ; 0-20 ; ; 76543210 == н == MOVLW B'10000001' ; з޽,VDD,CH0,ADC_ON MOVWF ADCON0 ; ; CALL TIM_100U ; Aqu Time 100us ; BSF ADCON0,1 ; A/D Start (GO) ; MAIN_310 BTFSC ADCON0,1 ; A/D = End (DONE) GOTO MAIN_310 ; = -> Loop ; MOVF ADRESH,W ; A/D Hi MOVWF V_THM_H ; MOVWF CONV_H ; BSF STATUS,RP0 ;|BANK = 1(01) MOVF ADRESL,W ;|A/D Low BCF STATUS,RP0 ;|BANK = 0(00) MOVWF V_THM_L ; MOVWF CONV_L ; ; CALL CONV_TH ; CONV_H,L(ݱ) -> W Reg() MOVWF C_NOW ; 50-101C ;------------------------------------------------------------------------ ; C_VRT(0-10) x5 +50 -> 50-100C MOVF C_VRT,W ; (0-10) MOVWF C_VRT_W1 ; BCF STATUS,C ; RLF C_VRT_W1,F ; <- (C_VRT x2) RLF C_VRT_W1,F ; <- (C_VRT x2) MOVF C_VRT_W1,W ; ADDWF C_VRT,W ; ( +C_VRT) ADDLW D'050' ; ( +50 ) ; MOVWF C_LOW ; Lower Limit TEMP ; ; (Offset ֲ 1C ) MOVWF C_UP ; Upper Limit TEMP ;------------------------------------------------------------------------ MOVF V_THM_H,W ; н ݾ CK (0C ݾ) SUBLW H'02' ; (V_THM=037A ) BTFSC STATUS,C ; THM H > 02 -> Skip GOTO MAIN_600 ; =< 02 -> OK ; MOVF V_THM_L,W ; SUBLW H'7A' ; BTFSS STATUS,C ; THM L =< 7A -> Skip GOTO MAIN_620 ; > 7A -> ݾ ; MAIN_600 BTFSS HT_NOW,5 ; ˰ Now = OFF -> Skip GOTO MAIN_610 ; = ON -> 600 ; ; ; == Target(Low) > Now -> ON == MOVF C_LOW,W ; Target SUBWF C_NOW,W ; Now BTFSC STATUS,C ; Target > Now -> Skip GOTO MAIN_610 ; Target =< Now -> Next ; BCF HT_TAR,5 ; ˰ Target = ON GOTO MAIN_700 ; -> Top Loop ; MAIN_610 ; == Target(UP) =< Now -> OFF == MOVF C_UP,W ; Target SUBWF C_NOW,W ; Now BTFSS STATUS,C ; Target =< Now -> Skip GOTO MAIN_700 ; Target > Now -> Top Loop ; MAIN_620 BSF HT_TAR,5 ; ˰ Target = OFF ; MAIN_700 CLRWDT ; Watch Dog ر CALL TIM_10M ; Timer 10ms ; MOVF HT_NOW,W ; SUBWF HT_TAR,W ; BTFSC STATUS,Z ; Now Target -> Skip GOTO MAIN_050 ; = ----> Top ; DECFSZ HT_CNT,F ; CNT -1 = 00 -> Skip GOTO MAIN_100 ; 00 ----> Top ; MOVF HT_TAR,W ; Target -> Now MOVWF HT_NOW ; MOVWF GPIO ; I/O ; GOTO MAIN_050 ; -> Top Loop ;------------------------------------------------------------------------ CONV_VR ; ݱ -> ݶ at VR ; Ը 30step x 10data = 600us ; Input : CONV_H,L ; Output: W Reg ; WK : CONV_C (0-10) ; CONV_WK ; Ref : VR_TBL ð ޭ ; CLRF CONV_C ; Code = 00 CONV_VR_10 MOVF CONV_C,W ; Code -> WK MOVWF CONV_C_WK ; BCF STATUS,C ; RLF CONV_C_WK,F ; WK x2 -> ADR MOVF CONV_C_WK,W ; CALL VR_TBL ; MOVWF CONV_C_TH ; Hi Data -> TH MOVF CONV_C_WK,W ; ADR +1 ADDLW D'1' ; CALL VR_TBL ; MOVWF CONV_C_TL ; Low Data -> TL ; MOVF CONV_H,W ; SUBWF CONV_C_TH,W ; BTFSC STATUS,Z ; Now TBL_H -> Skip GOTO CONV_VR_20 ; = -> Low CK BTFSS STATUS,C ; Now < TBL_H -> Skip (ò) GOTO CONV_VR_30 ; > -> Next GOTO CONV_VR_40 ; ; CONV_VR_20 MOVF CONV_L,W ; SUBWF CONV_C_TL,W ; BTFSC STATUS,C ; Now > TBL_H -> Skip GOTO CONV_VR_40 ; =< -> ò ; CONV_VR_30 INCF CONV_C,F ; Code +1 GOTO CONV_VR_10 ; --> Top Loop ; CONV_VR_40 MOVF CONV_C,W ; Code -> W Reg (Result) RETURN ; ;------------------------------------------------------------------------ CONV_TH ; ݱ -> ݶ at н ; Ը 30step x 51data = 1530 us ; 50C ޱ 50C ; Input : CONV_H,L ; Output: W Reg ; WK : CONV_C (0-51) +50 -> (50-101C) ; CONV_WK ; Ref : TH_TBL ð ޭ ; CLRF CONV_C ; Code = 00 CONV_TH_10 MOVF CONV_C,W ; Code -> WK MOVWF CONV_C_WK ; BCF STATUS,C ; RLF CONV_C_WK,F ; WK x2 -> ADR MOVF CONV_C_WK,W ; CALL TH_TBL ; MOVWF CONV_C_TH ; Hi Data -> TH MOVF CONV_C_WK,W ; ADR +1 ADDLW D'1' ; CALL TH_TBL ; MOVWF CONV_C_TL ; Low Data -> TL ; MOVF CONV_H,W ; SUBWF CONV_C_TH,W ; BTFSC STATUS,Z ; Now TBL_H -> Skip GOTO CONV_TH_20 ; = -> Low CK BTFSS STATUS,C ; Now < TBL_H -> Skip GOTO CONV_TH_40 ; > -> ò GOTO CONV_TH_30 ; ; CONV_TH_20 MOVF CONV_L,W ; SUBWF CONV_C_TL,W ; BTFSS STATUS,C ; Now =< TBL_L -> Skip GOTO CONV_TH_40 ; > -> ò BTFSC STATUS,Z ; < -> Skip GOTO CONV_TH_40 ; = -> ò ; CONV_TH_30 INCF CONV_C,F ; Code +1 GOTO CONV_TH_10 ; --> Top Loop ; CONV_TH_40 MOVLW D'050' ; +Offset (50C) ADDWF CONV_C,F ; MOVF CONV_C,W ; Code -> W Reg (Result) RETURN ; ;------------------------------------------------------------------------ TIM_100U ; Timer 100 usec (at CLK 1us) ; MOVLW D'32' ; B MOVWF TIM_WK_2 ; B TIM_100U_2 DECFSZ TIM_WK_2,F ; A CC GOTO TIM_100U_2 ; AA Ax(nn-1)+B+C+CALL RETURN ; BB 3x(32-1)+4+2+2 = 101 ;------------------------------------------------------------------------ TIM_10M ; Timer 10 msec MOVLW D'010' ; D MOVWF TIM_WK_1 ; D TIM_10M_1 MOVLW D'249' ; B | F MOVWF TIM_WK_2 ; B | F TIM_10M_2 NOP ; A C | E G DECFSZ TIM_WK_2,F ; A CC | E GG GOTO TIM_10M_2 ; AA | EE DECFSZ TIM_WK_1,F ; B | FF GOTO TIM_10M_1 ; BB | RETURN ; DD ; (Ax(nnn-1)+B+C)x(mmm-1)+D+(Ex(nnn-1)+F+G)+CALL ; (4x(249-1)+5+3)x(010-1)+4+(4x(249-1)+4+3)+2 =10,005 ;--------------------------------- IRQ routine -------------------------- IRQ ; RETFIE ; ;======================================================================== END