Loading plugins phase: Elapsed time ==> 12s.097ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -d CY8C4146LQI-S433 -s Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 33s.729ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.140ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 Bootloader_PSoC4_Example01.v -verilog
======================================================================

======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 Bootloader_PSoC4_Example01.v -verilog
======================================================================

======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   vlogfe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 -verilog Bootloader_PSoC4_Example01.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Thu Sep 07 18:29:43 2017


======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   vpp
Options  :    -yv2 -q10 Bootloader_PSoC4_Example01.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Thu Sep 07 18:29:44 2017

Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'

vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'Bootloader_PSoC4_Example01.ctl'.

vlogfe:  No errors.


======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   tovif
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 -verilog Bootloader_PSoC4_Example01.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Thu Sep 07 18:29:44 2017

Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\codegentemp\Bootloader_PSoC4_Example01.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\codegentemp\Bootloader_PSoC4_Example01.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.

tovif:  No errors.


======================================================================
Compiling:  Bootloader_PSoC4_Example01.v
Program  :   topld
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 -verilog Bootloader_PSoC4_Example01.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Thu Sep 07 18:29:45 2017

Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\codegentemp\Bootloader_PSoC4_Example01.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\codegentemp\Bootloader_PSoC4_Example01.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	\I2C_Slave:Net_1257\
	\I2C_Slave:uncfg_rx_irq\
	\I2C_Slave:Net_1099\
	\I2C_Slave:Net_1258\
	Net_105
	Net_106
	Net_115
	Net_116
	Net_117
	Net_118
	Net_119
	Net_120
	Net_121
	\UART:Net_1257\
	\UART:uncfg_rx_irq\
	\UART:Net_1099\
	\UART:Net_1258\
	Net_125
	Net_126
	Net_135
	Net_136
	Net_137
	Net_138
	Net_139
	Net_140
	Net_141


Deleted 26 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing \I2C_Slave:rx_wire\ to \I2C_Slave:select_s_wire\
Aliasing \I2C_Slave:sclk_s_wire\ to \I2C_Slave:select_s_wire\
Aliasing \I2C_Slave:mosi_s_wire\ to \I2C_Slave:select_s_wire\
Aliasing \I2C_Slave:miso_m_wire\ to \I2C_Slave:select_s_wire\
Aliasing zero to \I2C_Slave:select_s_wire\
Aliasing one to \I2C_Slave:tmpOE__sda_net_0\
Aliasing \I2C_Slave:tmpOE__scl_net_0\ to \I2C_Slave:tmpOE__sda_net_0\
Aliasing \I2C_Slave:cts_wire\ to \I2C_Slave:select_s_wire\
Aliasing tmpOE__Bootloader_Status_net_0 to \I2C_Slave:tmpOE__sda_net_0\
Aliasing \UART:select_s_wire\ to \I2C_Slave:select_s_wire\
Aliasing \UART:sclk_s_wire\ to \I2C_Slave:select_s_wire\
Aliasing \UART:mosi_s_wire\ to \I2C_Slave:select_s_wire\
Aliasing \UART:miso_m_wire\ to \I2C_Slave:select_s_wire\
Aliasing \UART:tmpOE__tx_net_0\ to \I2C_Slave:tmpOE__sda_net_0\
Aliasing \UART:tmpOE__rx_net_0\ to \I2C_Slave:tmpOE__sda_net_0\
Aliasing \UART:cts_wire\ to \I2C_Slave:select_s_wire\
Removing Lhs of wire \I2C_Slave:rx_wire\[3] = \I2C_Slave:select_s_wire\[2]
Removing Lhs of wire \I2C_Slave:Net_1170\[6] = \I2C_Slave:Net_847\[1]
Removing Lhs of wire \I2C_Slave:sclk_s_wire\[7] = \I2C_Slave:select_s_wire\[2]
Removing Lhs of wire \I2C_Slave:mosi_s_wire\[8] = \I2C_Slave:select_s_wire\[2]
Removing Lhs of wire \I2C_Slave:miso_m_wire\[9] = \I2C_Slave:select_s_wire\[2]
Removing Rhs of wire zero[12] = \I2C_Slave:select_s_wire\[2]
Removing Rhs of wire one[16] = \I2C_Slave:tmpOE__sda_net_0\[11]
Removing Lhs of wire \I2C_Slave:tmpOE__scl_net_0\[19] = one[16]
Removing Lhs of wire \I2C_Slave:cts_wire\[28] = zero[12]
Removing Lhs of wire tmpOE__Bootloader_Status_net_0[56] = one[16]
Removing Lhs of wire \UART:select_s_wire\[63] = zero[12]
Removing Rhs of wire \UART:rx_wire\[64] = \UART:Net_1268\[65]
Removing Lhs of wire \UART:Net_1170\[68] = \UART:Net_847\[62]
Removing Lhs of wire \UART:sclk_s_wire\[69] = zero[12]
Removing Lhs of wire \UART:mosi_s_wire\[70] = zero[12]
Removing Lhs of wire \UART:miso_m_wire\[71] = zero[12]
Removing Lhs of wire \UART:tmpOE__tx_net_0\[73] = one[16]
Removing Lhs of wire \UART:tmpOE__rx_net_0\[84] = one[16]
Removing Lhs of wire \UART:cts_wire\[88] = zero[12]

------------------------------------------------------
Aliased 0 equations, 19 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:


----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

topld:  No errors.

CYPRESS_DIR    : C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp
Warp Program   : C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -dcpsoc3 Bootloader_PSoC4_Example01.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 2s.543ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.0.0.432, Family: PSoC3, Started at: Thursday, 07 September 2017 18:29:45
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\Bootloader_PSoC4_Example01\Bootloader_PSoC4_Example01.cydsn\Bootloader_PSoC4_Example01.cyprj -d CY8C4146LQI-S433 Bootloader_PSoC4_Example01.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.190ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
    Fixed Function Clock 0: Automatic-assigning  clock 'I2C_Slave_SCBCLK'. Signal=\I2C_Slave:Net_847_ff0\
    Fixed Function Clock 1: Automatic-assigning  clock 'UART_SCBCLK'. Signal=\UART:Net_847_ff1\
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
</CYPRESSTAG>
ADD: pft.M0040: information: The following 2 pin(s) will be assigned a location by the fitter: \UART:rx(0)\, \UART:tx(0)\


Removing unused cells resulting from optimization
Done removing unused cells.
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = \I2C_Slave:sda(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \I2C_Slave:sda(0)\__PA ,
            fb => \I2C_Slave:sda_wire\ ,
            pad => \I2C_Slave:sda(0)_PAD\ );
        Properties:
        {
            port_location = "PORT(3,1)"
        }

    Pin : Name = \I2C_Slave:scl(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \I2C_Slave:scl(0)\__PA ,
            fb => \I2C_Slave:scl_wire\ ,
            pad => \I2C_Slave:scl(0)_PAD\ );
        Properties:
        {
            port_location = "PORT(3,0)"
        }

    Pin : Name = Bootloader_Status(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => Bootloader_Status(0)__PA ,
            annotation => Net_1782 ,
            pad => Bootloader_Status(0)_PAD );
        Properties:
        {
            port_location = "PORT(3,6)"
        }

    Pin : Name = \UART:tx(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \UART:tx(0)\__PA ,
            input => \UART:tx_wire\ ,
            pad => \UART:tx(0)_PAD\ );

    Pin : Name = \UART:rx(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \UART:rx(0)\__PA ,
            fb => \UART:rx_wire\ ,
            pad => \UART:rx(0)_PAD\ );
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">

    ------------------------------------------------------------
    Interrupt listing
    ------------------------------------------------------------

    interrupt: Name =\I2C_Slave:SCB_IRQ\
        PORT MAP (
            interrupt => Net_107 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\UART:SCB_IRQ\
        PORT MAP (
            interrupt => Net_127 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Interrupts                    :    2 :   18 :   20 : 10.00 %
IO                            :    7 :   27 :   34 : 20.59 %
Segment LCD                   :    0 :    1 :    1 :  0.00 %
CapSense                      :    0 :    1 :    1 :  0.00 %
Die Temp                      :    0 :    1 :    1 :  0.00 %
Serial Communication (SCB)    :    2 :    1 :    3 : 66.67 %
Timer/Counter/PWM             :    0 :    5 :    5 :  0.00 %
Smart IO Ports                :    0 :    2 :    2 :  0.00 %
Comparator/Opamp              :    0 :    2 :    2 :  0.00 %
Comparator                    :    0 :    1 :    1 :  0.00 %
LP Comparator                 :    0 :    2 :    2 :  0.00 %
SAR ADC                       :    0 :    1 :    1 :  0.00 %
DAC                           :      :      :      :        
  7-bit IDAC                  :    0 :    2 :    2 :  0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.210ms
Tech Mapping phase: Elapsed time ==> 0s.851ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
<CYPRESSTAG name="Analog Placement">
Elapsed time ==> 0.5553395s
</CYPRESSTAG>
Analog Placement phase: Elapsed time ==> 1s.211ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
<CYPRESSTAG name="Analog Routing">
Route success=True, Iterations=1 Elapsed=0.0012627 secs
</CYPRESSTAG>
Analog Routing phase: Elapsed time ==> 0s.040ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Analog Code Generation phase: Elapsed time ==> 0s.160ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2076: Total run-time: 0.9 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary">
No PLDs were packed.
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.030ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.580ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          0 :       0.00 :       0.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
Intr container @ [IntrContainer=(0)]: 
  Intr@ [IntrContainer=(0)][IntrId=(7)] 
    interrupt: Name =\UART:SCB_IRQ\
        PORT MAP (
            interrupt => Net_127 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(8)] 
    interrupt: Name =\I2C_Slave:SCB_IRQ\
        PORT MAP (
            interrupt => Net_107 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
Port 0 is empty
Port 1 contains the following IO cells:
[IoId=0]: 
Pin : Name = \UART:rx(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \UART:rx(0)\__PA ,
        fb => \UART:rx_wire\ ,
        pad => \UART:rx(0)_PAD\ );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = \UART:tx(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \UART:tx(0)\__PA ,
        input => \UART:tx_wire\ ,
        pad => \UART:tx(0)_PAD\ );
    Properties:
    {
    }

Port 2 is empty
Port 3 contains the following IO cells:
[IoId=0]: 
Pin : Name = \I2C_Slave:scl(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \I2C_Slave:scl(0)\__PA ,
        fb => \I2C_Slave:scl_wire\ ,
        pad => \I2C_Slave:scl(0)_PAD\ );
    Properties:
    {
        port_location = "PORT(3,0)"
    }

[IoId=1]: 
Pin : Name = \I2C_Slave:sda(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \I2C_Slave:sda(0)\__PA ,
        fb => \I2C_Slave:sda_wire\ ,
        pad => \I2C_Slave:sda(0)_PAD\ );
    Properties:
    {
        port_location = "PORT(3,1)"
    }

[IoId=6]: 
Pin : Name = Bootloader_Status(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => Bootloader_Status(0)__PA ,
        annotation => Net_1782 ,
        pad => Bootloader_Status(0)_PAD );
    Properties:
    {
        port_location = "PORT(3,6)"
    }

Port 4 is empty
Clock group 0: 
    Clock Block @ F(Clock,0): 
    m0s8clockblockcell: Name =ClockBlock
        PORT MAP (
            hfclk => ClockBlock_HFCLK ,
            imo => ClockBlock_IMO ,
            ext => ClockBlock_EXTCLK ,
            sysclk => ClockBlock_SYSCLK ,
            ilo => ClockBlock_ILO ,
            lfclk => ClockBlock_LFCLK ,
            wco => ClockBlock_WCO ,
            ff_div_0 => \I2C_Slave:Net_847_ff0\ ,
            ff_div_1 => \UART:Net_847_ff1\ );
        Properties:
        {
        }
SPC group 0: empty
Vref group 0: empty
WDT group 0: empty
LP Comparator group 0: empty
Serial Communication (SCB) group 0: 
    SCB Block @ F(SCB,0): 
    m0s8scbcell: Name =\UART:SCB\
        PORT MAP (
            clock => \UART:Net_847_ff1\ ,
            interrupt => Net_127 ,
            rx => \UART:rx_wire\ ,
            tx => \UART:tx_wire\ ,
            rts => \UART:rts_wire\ ,
            mosi_m => \UART:mosi_m_wire\ ,
            select_m_3 => \UART:select_m_wire_3\ ,
            select_m_2 => \UART:select_m_wire_2\ ,
            select_m_1 => \UART:select_m_wire_1\ ,
            select_m_0 => \UART:select_m_wire_0\ ,
            sclk_m => \UART:sclk_m_wire\ ,
            miso_s => \UART:miso_s_wire\ ,
            tx_req => Net_130 ,
            rx_req => Net_129 );
        Properties:
        {
            cy_registers = ""
            scb_mode = 2
        }
    SCB Block @ F(SCB,1): 
    m0s8scbcell: Name =\I2C_Slave:SCB\
        PORT MAP (
            clock => \I2C_Slave:Net_847_ff0\ ,
            interrupt => Net_107 ,
            tx => \I2C_Slave:tx_wire\ ,
            rts => \I2C_Slave:rts_wire\ ,
            mosi_m => \I2C_Slave:mosi_m_wire\ ,
            select_m_3 => \I2C_Slave:select_m_wire_3\ ,
            select_m_2 => \I2C_Slave:select_m_wire_2\ ,
            select_m_1 => \I2C_Slave:select_m_wire_1\ ,
            select_m_0 => \I2C_Slave:select_m_wire_0\ ,
            sclk_m => \I2C_Slave:sclk_m_wire\ ,
            miso_s => \I2C_Slave:miso_s_wire\ ,
            scl => \I2C_Slave:scl_wire\ ,
            sda => \I2C_Slave:sda_wire\ ,
            tx_req => Net_110 ,
            rx_req => Net_109 );
        Properties:
        {
            cy_registers = ""
            scb_mode = 0
        }
CapSense group 0: empty
7-bit IDAC group 0: empty
Timer/Counter/PWM group 0: empty
Comparator/Opamp group 0: empty
Die Temp group 0: empty
SAR ADC group 0: empty
Segment LCD group 0: empty
CLK_GEN group 0: 
    M0S8 Clock Gen Block @ F(CLK_GEN,0): 
    m0s8clockgenblockcell: Name =ClockGenBlock
        PORT MAP (
             );
        Properties:
        {
        }
LPCOMPBLOCK group 0: empty
PASSBLOCK group 0: empty
GANGED_PICU group 0: empty
WCO group 0: empty
Smart IO Ports group 0: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |                      | 
Port | Pin | Fixed |      Type |       Drive Mode |                 Name | Connections
-----+-----+-------+-----------+------------------+----------------------+-------------------------
   1 |   0 |       |      NONE |     HI_Z_DIGITAL |         \UART:rx(0)\ | FB(\UART:rx_wire\)
     |   1 |       |      NONE |         CMOS_OUT |         \UART:tx(0)\ | In(\UART:tx_wire\)
-----+-----+-------+-----------+------------------+----------------------+-------------------------
   3 |   0 |     * |      NONE |    OPEN_DRAIN_LO |   \I2C_Slave:scl(0)\ | FB(\I2C_Slave:scl_wire\)
     |   1 |     * |      NONE |    OPEN_DRAIN_LO |   \I2C_Slave:sda(0)\ | FB(\I2C_Slave:sda_wire\)
     |   6 |     * |      NONE |         CMOS_OUT | Bootloader_Status(0) | 
---------------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.010ms
Digital Placement phase: Elapsed time ==> 2s.964ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
Info: pft.M0077: There is no timing information available for the selected device. Static timing checks will not be applied and digital routing will not be timing-driven. (App=cydsfit)
Routing successful.
Digital Routing phase: Elapsed time ==> 0s.781ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 0s.851ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.090ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
No timing parameter file available for CY8C4146LQI-S433
Static timing analysis phase: Elapsed time ==> 0s.060ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.340ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 7s.851ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 7s.951ms
API generation phase: Elapsed time ==> 9s.624ms
Dependency generation phase: Elapsed time ==> 0s.170ms
Cleanup phase: Elapsed time ==> 0s.040ms
