.ifndef INCLUDED_CYFITTERGNU_INC
.set INCLUDED_CYFITTERGNU_INC, 1
.include "cydevicegnu_trm.inc"

/* PWM_cy_m0s8_tcpwm_1 */
.set PWM_cy_m0s8_tcpwm_1__CC, CYREG_TCPWM_CNT2_CC
.set PWM_cy_m0s8_tcpwm_1__CC_BUFF, CYREG_TCPWM_CNT2_CC_BUFF
.set PWM_cy_m0s8_tcpwm_1__COUNTER, CYREG_TCPWM_CNT2_COUNTER
.set PWM_cy_m0s8_tcpwm_1__CTRL, CYREG_TCPWM_CNT2_CTRL
.set PWM_cy_m0s8_tcpwm_1__INTR, CYREG_TCPWM_CNT2_INTR
.set PWM_cy_m0s8_tcpwm_1__INTR_MASK, CYREG_TCPWM_CNT2_INTR_MASK
.set PWM_cy_m0s8_tcpwm_1__INTR_MASKED, CYREG_TCPWM_CNT2_INTR_MASKED
.set PWM_cy_m0s8_tcpwm_1__INTR_SET, CYREG_TCPWM_CNT2_INTR_SET
.set PWM_cy_m0s8_tcpwm_1__PERIOD, CYREG_TCPWM_CNT2_PERIOD
.set PWM_cy_m0s8_tcpwm_1__PERIOD_BUFF, CYREG_TCPWM_CNT2_PERIOD_BUFF
.set PWM_cy_m0s8_tcpwm_1__STATUS, CYREG_TCPWM_CNT2_STATUS
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMD, CYREG_TCPWM_CMD
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK, 0x04
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT, 2
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK, 0x400
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT, 10
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK, 0x4000000
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT, 26
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK, 0x40000
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT, 18
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL, CYREG_TCPWM_CTRL
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK, 0x04
.set PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT, 2
.set PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE, CYREG_TCPWM_INTR_CAUSE
.set PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK, 0x04
.set PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT, 2
.set PWM_cy_m0s8_tcpwm_1__TCPWM_NUMBER, 2
.set PWM_cy_m0s8_tcpwm_1__TR_CTRL0, CYREG_TCPWM_CNT2_TR_CTRL0
.set PWM_cy_m0s8_tcpwm_1__TR_CTRL1, CYREG_TCPWM_CNT2_TR_CTRL1
.set PWM_cy_m0s8_tcpwm_1__TR_CTRL2, CYREG_TCPWM_CNT2_TR_CTRL2

/* SmartIO_1_cy_m0s8_prgio */
.set SmartIO_1_cy_m0s8_prgio__CTL, CYREG_PRGIO_PRT0_CTL
.set SmartIO_1_cy_m0s8_prgio__DATA, CYREG_PRGIO_PRT0_DATA
.set SmartIO_1_cy_m0s8_prgio__DU_CTL, CYREG_PRGIO_PRT0_DU_CTL
.set SmartIO_1_cy_m0s8_prgio__DU_SEL, CYREG_PRGIO_PRT0_DU_SEL
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL0, CYREG_PRGIO_PRT0_LUT_CTL0
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL1, CYREG_PRGIO_PRT0_LUT_CTL1
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL2, CYREG_PRGIO_PRT0_LUT_CTL2
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL3, CYREG_PRGIO_PRT0_LUT_CTL3
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL4, CYREG_PRGIO_PRT0_LUT_CTL4
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL5, CYREG_PRGIO_PRT0_LUT_CTL5
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL6, CYREG_PRGIO_PRT0_LUT_CTL6
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL7, CYREG_PRGIO_PRT0_LUT_CTL7
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL0, CYREG_PRGIO_PRT0_LUT_SEL0
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL1, CYREG_PRGIO_PRT0_LUT_SEL1
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL2, CYREG_PRGIO_PRT0_LUT_SEL2
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL3, CYREG_PRGIO_PRT0_LUT_SEL3
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL4, CYREG_PRGIO_PRT0_LUT_SEL4
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL5, CYREG_PRGIO_PRT0_LUT_SEL5
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL6, CYREG_PRGIO_PRT0_LUT_SEL6
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL7, CYREG_PRGIO_PRT0_LUT_SEL7
.set SmartIO_1_cy_m0s8_prgio__SYNC_CTL, CYREG_PRGIO_PRT0_SYNC_CTL

/* SmartIO_cy_m0s8_prgio */
.set SmartIO_cy_m0s8_prgio__CTL, CYREG_PRGIO_PRT1_CTL
.set SmartIO_cy_m0s8_prgio__DATA, CYREG_PRGIO_PRT1_DATA
.set SmartIO_cy_m0s8_prgio__DU_CTL, CYREG_PRGIO_PRT1_DU_CTL
.set SmartIO_cy_m0s8_prgio__DU_SEL, CYREG_PRGIO_PRT1_DU_SEL
.set SmartIO_cy_m0s8_prgio__LUT_CTL0, CYREG_PRGIO_PRT1_LUT_CTL0
.set SmartIO_cy_m0s8_prgio__LUT_CTL1, CYREG_PRGIO_PRT1_LUT_CTL1
.set SmartIO_cy_m0s8_prgio__LUT_CTL2, CYREG_PRGIO_PRT1_LUT_CTL2
.set SmartIO_cy_m0s8_prgio__LUT_CTL3, CYREG_PRGIO_PRT1_LUT_CTL3
.set SmartIO_cy_m0s8_prgio__LUT_CTL4, CYREG_PRGIO_PRT1_LUT_CTL4
.set SmartIO_cy_m0s8_prgio__LUT_CTL5, CYREG_PRGIO_PRT1_LUT_CTL5
.set SmartIO_cy_m0s8_prgio__LUT_CTL6, CYREG_PRGIO_PRT1_LUT_CTL6
.set SmartIO_cy_m0s8_prgio__LUT_CTL7, CYREG_PRGIO_PRT1_LUT_CTL7
.set SmartIO_cy_m0s8_prgio__LUT_SEL0, CYREG_PRGIO_PRT1_LUT_SEL0
.set SmartIO_cy_m0s8_prgio__LUT_SEL1, CYREG_PRGIO_PRT1_LUT_SEL1
.set SmartIO_cy_m0s8_prgio__LUT_SEL2, CYREG_PRGIO_PRT1_LUT_SEL2
.set SmartIO_cy_m0s8_prgio__LUT_SEL3, CYREG_PRGIO_PRT1_LUT_SEL3
.set SmartIO_cy_m0s8_prgio__LUT_SEL4, CYREG_PRGIO_PRT1_LUT_SEL4
.set SmartIO_cy_m0s8_prgio__LUT_SEL5, CYREG_PRGIO_PRT1_LUT_SEL5
.set SmartIO_cy_m0s8_prgio__LUT_SEL6, CYREG_PRGIO_PRT1_LUT_SEL6
.set SmartIO_cy_m0s8_prgio__LUT_SEL7, CYREG_PRGIO_PRT1_LUT_SEL7
.set SmartIO_cy_m0s8_prgio__SYNC_CTL, CYREG_PRGIO_PRT1_SYNC_CTL

/* Clock_pwm */
.set Clock_pwm__CTRL_REGISTER, CYREG_PERI_PCLK_CTL6
.set Clock_pwm__DIV_ID, 0x00000040
.set Clock_pwm__DIV_REGISTER, CYREG_PERI_DIV_16_CTL0
.set Clock_pwm__PA_DIV_ID, 0x000000FF

/* pin_LED_1 */
.set pin_LED_1__0__DR, CYREG_GPIO_PRT3_DR
.set pin_LED_1__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set pin_LED_1__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set pin_LED_1__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set pin_LED_1__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set pin_LED_1__0__HSIOM_MASK, 0x000F0000
.set pin_LED_1__0__HSIOM_SHIFT, 16
.set pin_LED_1__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_1__0__INTR, CYREG_GPIO_PRT3_INTR
.set pin_LED_1__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_1__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set pin_LED_1__0__MASK, 0x10
.set pin_LED_1__0__PC, CYREG_GPIO_PRT3_PC
.set pin_LED_1__0__PC2, CYREG_GPIO_PRT3_PC2
.set pin_LED_1__0__PORT, 3
.set pin_LED_1__0__PS, CYREG_GPIO_PRT3_PS
.set pin_LED_1__0__SHIFT, 4
.set pin_LED_1__DR, CYREG_GPIO_PRT3_DR
.set pin_LED_1__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set pin_LED_1__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set pin_LED_1__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set pin_LED_1__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_1__INTR, CYREG_GPIO_PRT3_INTR
.set pin_LED_1__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_1__INTSTAT, CYREG_GPIO_PRT3_INTR
.set pin_LED_1__MASK, 0x10
.set pin_LED_1__PC, CYREG_GPIO_PRT3_PC
.set pin_LED_1__PC2, CYREG_GPIO_PRT3_PC2
.set pin_LED_1__PORT, 3
.set pin_LED_1__PS, CYREG_GPIO_PRT3_PS
.set pin_LED_1__SHIFT, 4

/* pin_LED_2 */
.set pin_LED_2__0__DR, CYREG_GPIO_PRT3_DR
.set pin_LED_2__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set pin_LED_2__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set pin_LED_2__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set pin_LED_2__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set pin_LED_2__0__HSIOM_MASK, 0x0F000000
.set pin_LED_2__0__HSIOM_SHIFT, 24
.set pin_LED_2__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_2__0__INTR, CYREG_GPIO_PRT3_INTR
.set pin_LED_2__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_2__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set pin_LED_2__0__MASK, 0x40
.set pin_LED_2__0__PC, CYREG_GPIO_PRT3_PC
.set pin_LED_2__0__PC2, CYREG_GPIO_PRT3_PC2
.set pin_LED_2__0__PORT, 3
.set pin_LED_2__0__PS, CYREG_GPIO_PRT3_PS
.set pin_LED_2__0__SHIFT, 6
.set pin_LED_2__DR, CYREG_GPIO_PRT3_DR
.set pin_LED_2__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set pin_LED_2__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set pin_LED_2__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set pin_LED_2__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_2__INTR, CYREG_GPIO_PRT3_INTR
.set pin_LED_2__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set pin_LED_2__INTSTAT, CYREG_GPIO_PRT3_INTR
.set pin_LED_2__MASK, 0x40
.set pin_LED_2__PC, CYREG_GPIO_PRT3_PC
.set pin_LED_2__PC2, CYREG_GPIO_PRT3_PC2
.set pin_LED_2__PORT, 3
.set pin_LED_2__PS, CYREG_GPIO_PRT3_PS
.set pin_LED_2__SHIFT, 6

/* pin_LED_3 */
.set pin_LED_3__0__DR, CYREG_GPIO_PRT2_DR
.set pin_LED_3__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set pin_LED_3__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set pin_LED_3__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set pin_LED_3__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set pin_LED_3__0__HSIOM_MASK, 0x000F0000
.set pin_LED_3__0__HSIOM_SHIFT, 16
.set pin_LED_3__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_3__0__INTR, CYREG_GPIO_PRT2_INTR
.set pin_LED_3__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_3__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set pin_LED_3__0__MASK, 0x10
.set pin_LED_3__0__PC, CYREG_GPIO_PRT2_PC
.set pin_LED_3__0__PC2, CYREG_GPIO_PRT2_PC2
.set pin_LED_3__0__PORT, 2
.set pin_LED_3__0__PS, CYREG_GPIO_PRT2_PS
.set pin_LED_3__0__SHIFT, 4
.set pin_LED_3__DR, CYREG_GPIO_PRT2_DR
.set pin_LED_3__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set pin_LED_3__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set pin_LED_3__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set pin_LED_3__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_3__INTR, CYREG_GPIO_PRT2_INTR
.set pin_LED_3__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_3__INTSTAT, CYREG_GPIO_PRT2_INTR
.set pin_LED_3__MASK, 0x10
.set pin_LED_3__PC, CYREG_GPIO_PRT2_PC
.set pin_LED_3__PC2, CYREG_GPIO_PRT2_PC2
.set pin_LED_3__PORT, 2
.set pin_LED_3__PS, CYREG_GPIO_PRT2_PS
.set pin_LED_3__SHIFT, 4

/* pin_LED_4 */
.set pin_LED_4__0__DR, CYREG_GPIO_PRT2_DR
.set pin_LED_4__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set pin_LED_4__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set pin_LED_4__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set pin_LED_4__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set pin_LED_4__0__HSIOM_MASK, 0x0F000000
.set pin_LED_4__0__HSIOM_SHIFT, 24
.set pin_LED_4__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_4__0__INTR, CYREG_GPIO_PRT2_INTR
.set pin_LED_4__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_4__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set pin_LED_4__0__MASK, 0x40
.set pin_LED_4__0__PC, CYREG_GPIO_PRT2_PC
.set pin_LED_4__0__PC2, CYREG_GPIO_PRT2_PC2
.set pin_LED_4__0__PORT, 2
.set pin_LED_4__0__PS, CYREG_GPIO_PRT2_PS
.set pin_LED_4__0__SHIFT, 6
.set pin_LED_4__DR, CYREG_GPIO_PRT2_DR
.set pin_LED_4__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set pin_LED_4__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set pin_LED_4__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set pin_LED_4__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_4__INTR, CYREG_GPIO_PRT2_INTR
.set pin_LED_4__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set pin_LED_4__INTSTAT, CYREG_GPIO_PRT2_INTR
.set pin_LED_4__MASK, 0x40
.set pin_LED_4__PC, CYREG_GPIO_PRT2_PC
.set pin_LED_4__PC2, CYREG_GPIO_PRT2_PC2
.set pin_LED_4__PORT, 2
.set pin_LED_4__PS, CYREG_GPIO_PRT2_PS
.set pin_LED_4__SHIFT, 6

/* Clock_smartio */
.set Clock_smartio__CTRL_REGISTER, CYREG_PERI_PCLK_CTL10
.set Clock_smartio__DIV_ID, 0x00000041
.set Clock_smartio__DIV_REGISTER, CYREG_PERI_DIV_16_CTL1
.set Clock_smartio__PA_DIV_ID, 0x000000FF

/* Miscellaneous */
.set CYDEV_BCLK__HFCLK__HZ, 3000000
.set CYDEV_BCLK__HFCLK__KHZ, 3000
.set CYDEV_BCLK__HFCLK__MHZ, 3
.set CYDEV_BCLK__SYSCLK__HZ, 3000000
.set CYDEV_BCLK__SYSCLK__KHZ, 3000
.set CYDEV_BCLK__SYSCLK__MHZ, 3
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PSOC4A, 12
.set CYDEV_CHIP_DIE_PSOC5LP, 19
.set CYDEV_CHIP_DIE_PSOC5TM, 20
.set CYDEV_CHIP_DIE_TMA4, 2
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_FM0P, 4
.set CYDEV_CHIP_FAMILY_FM3, 5
.set CYDEV_CHIP_FAMILY_FM4, 6
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4
.set CYDEV_CHIP_JTAG_ID, 0x1B0011AB
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 12
.set CYDEV_CHIP_MEMBER_4C, 18
.set CYDEV_CHIP_MEMBER_4D, 8
.set CYDEV_CHIP_MEMBER_4E, 4
.set CYDEV_CHIP_MEMBER_4F, 13
.set CYDEV_CHIP_MEMBER_4G, 2
.set CYDEV_CHIP_MEMBER_4H, 11
.set CYDEV_CHIP_MEMBER_4I, 17
.set CYDEV_CHIP_MEMBER_4J, 9
.set CYDEV_CHIP_MEMBER_4K, 10
.set CYDEV_CHIP_MEMBER_4L, 16
.set CYDEV_CHIP_MEMBER_4M, 15
.set CYDEV_CHIP_MEMBER_4N, 6
.set CYDEV_CHIP_MEMBER_4O, 5
.set CYDEV_CHIP_MEMBER_4P, 14
.set CYDEV_CHIP_MEMBER_4Q, 7
.set CYDEV_CHIP_MEMBER_4U, 3
.set CYDEV_CHIP_MEMBER_5A, 20
.set CYDEV_CHIP_MEMBER_5B, 19
.set CYDEV_CHIP_MEMBER_FM3, 24
.set CYDEV_CHIP_MEMBER_FM4, 25
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4K
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1
.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1
.set CYDEV_CHIP_REV_TMA4_ES, 17
.set CYDEV_CHIP_REV_TMA4_ES2, 33
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
.set CYDEV_CHIP_REVISION_4G_ES, 17
.set CYDEV_CHIP_REVISION_4G_ES2, 33
.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4K_PRODUCTION
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
.set CYDEV_CONFIG_READ_ACCELERATOR, 1
.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_PROTECT_KILL, 4
.set CYDEV_DEBUG_PROTECT_OPEN, 1
.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN
.set CYDEV_DEBUG_PROTECT_PROTECTED, 2
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DFT_SELECT_CLK0, 8
.set CYDEV_DFT_SELECT_CLK1, 9
.set CYDEV_HEAP_SIZE, 0x80
.set CYDEV_IMO_TRIMMED_BY_USB, 0
.set CYDEV_IMO_TRIMMED_BY_WCO, 0
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_STACK_SIZE, 0x0400
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 1
.set CYDEV_VDDA_MV, 3300
.set CYDEV_VDDD_MV, 3300
.set CYDEV_WDT_GENERATE_ISR, 0
.set CYIPBLOCK_m0s8cpussv3_VERSION, 1
.set CYIPBLOCK_m0s8csdv2_VERSION, 1
.set CYIPBLOCK_m0s8ioss_VERSION, 1
.set CYIPBLOCK_m0s8lcd_VERSION, 2
.set CYIPBLOCK_m0s8lpcomp_VERSION, 2
.set CYIPBLOCK_m0s8pass4a_VERSION, 1
.set CYIPBLOCK_m0s8peri_VERSION, 1
.set CYIPBLOCK_m0s8scb_VERSION, 2
.set CYIPBLOCK_m0s8tcpwm_VERSION, 2
.set CYIPBLOCK_m0s8wco_VERSION, 1
.set CYIPBLOCK_s8srsslt_VERSION, 1
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
