# THIS FILE IS AUTOMATICALLY GENERATED
# Project: Z:\TMP\PSoC4SProj\CQ4S01_Sample\LEDBlinkPWM.cydsn\LEDBlinkPWM.cyprj
# Date: Thu, 15 Feb 2018 06:38:27 GMT
#set_units -time ns
create_clock -name {Clock_1(FFB)} -period 1000000 -waveform {0 500000} [list [get_pins {ClockBlock/ff_div_4}]]
create_clock -name {CyILO} -period 25000 -waveform {0 12500} [list [get_pins {ClockBlock/ilo}]]
create_clock -name {CyLFCLK} -period 25000 -waveform {0 12500} [list [get_pins {ClockBlock/lfclk}]]
create_clock -name {CyIMO} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/imo}]]
create_clock -name {CyHFCLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/hfclk}]]
create_clock -name {CySYSCLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/sysclk}]]
create_generated_clock -name {Clock_1} -source [get_pins {ClockBlock/hfclk}] -edges {1 24001 48001} [list]


# Component constraints for Z:\TMP\PSoC4SProj\CQ4S01_Sample\LEDBlinkPWM.cydsn\TopDesign\TopDesign.cysch
# Project: Z:\TMP\PSoC4SProj\CQ4S01_Sample\LEDBlinkPWM.cydsn\LEDBlinkPWM.cyprj
# Date: Thu, 15 Feb 2018 06:38:26 GMT
