/*******************************************************************************
* File Name: cydevice_trm.h
* 
* PSoC Creator  4.0
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#if !defined(CYDEVICE_TRM_H)
#define CYDEVICE_TRM_H
#define CYDEV_FLASH_BASE 0x00000000u
#define CYDEV_FLASH_SIZE 0x00010000u
#define CYREG_FLASH_DATA_MBASE 0x00000000u
#define CYREG_FLASH_DATA_MSIZE 0x00010000u
#define CYDEV_SFLASH_BASE 0x0ffff000u
#define CYDEV_SFLASH_SIZE 0x00000400u
#define CYREG_SFLASH_CSDV2_CSD1_ADC_TRIM1 0x0ffff0d4u
#define CYFLD_SFLASH_ADCTRIM_1p2V__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADCTRIM_1p2V__SIZE 0x00000005u
#define CYFLD_SFLASH_ADCTRIM_2p4V_2_0__OFFSET 0x00000005u
#define CYFLD_SFLASH_ADCTRIM_2p4V_2_0__SIZE 0x00000003u
#define CYREG_SFLASH_CSDV2_CSD1_ADC_TRIM2 0x0ffff0d5u
#define CYFLD_SFLASH_ADCTRIM_3p84V_2_0__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADCTRIM_3p84V_2_0__SIZE 0x00000005u
#define CYFLD_SFLASH_ADCTRIM_2p4V_5_4__OFFSET 0x00000005u
#define CYFLD_SFLASH_ADCTRIM_2p4V_5_4__SIZE 0x00000002u
#define CYREG_SFLASH_SILICON_ID 0x0ffff144u
#define CYFLD_SFLASH_ID__OFFSET 0x00000000u
#define CYFLD_SFLASH_ID__SIZE 0x00000010u
#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u
#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u
#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u
#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u
#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u
#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u
#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u
#define CYREG_SFLASH_FLASH_START 0x0ffff15cu
#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u
#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 0x0ffff160u
#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET 0x00000000u
#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE 0x00000008u
#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 0x0ffff161u
#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET 0x00000000u
#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE 0x00000008u
#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u
#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166u
#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u
#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u
#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u
#define CYFLD_SFLASH_LOT__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u
#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au
#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu
#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_X 0x0ffff17cu
#define CYFLD_SFLASH_X__OFFSET 0x00000000u
#define CYFLD_SFLASH_X__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_Y 0x0ffff17du
#define CYFLD_SFLASH_Y__OFFSET 0x00000000u
#define CYFLD_SFLASH_Y__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu
#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u
#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001u
#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002u
#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003u
#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004u
#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005u
#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001u
#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu
#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u
#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff1beu
#define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000u
#define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff1bfu
#define CYREG_SFLASH_IMO_TCTRIM_LT0 0x0ffff1ccu
#define CYFLD_SFLASH_STEPSIZE__OFFSET 0x00000000u
#define CYFLD_SFLASH_STEPSIZE__SIZE 0x00000005u
#define CYFLD_SFLASH_TCTRIM__OFFSET 0x00000005u
#define CYFLD_SFLASH_TCTRIM__SIZE 0x00000002u
#define CYREG_SFLASH_IMO_TCTRIM_LT1 0x0ffff1cdu
#define CYREG_SFLASH_IMO_TCTRIM_LT2 0x0ffff1ceu
#define CYREG_SFLASH_IMO_TCTRIM_LT3 0x0ffff1cfu
#define CYREG_SFLASH_IMO_TCTRIM_LT4 0x0ffff1d0u
#define CYREG_SFLASH_IMO_TCTRIM_LT5 0x0ffff1d1u
#define CYREG_SFLASH_IMO_TCTRIM_LT6 0x0ffff1d2u
#define CYREG_SFLASH_IMO_TCTRIM_LT7 0x0ffff1d3u
#define CYREG_SFLASH_IMO_TCTRIM_LT8 0x0ffff1d4u
#define CYREG_SFLASH_IMO_TCTRIM_LT9 0x0ffff1d5u
#define CYREG_SFLASH_IMO_TCTRIM_LT10 0x0ffff1d6u
#define CYREG_SFLASH_IMO_TCTRIM_LT11 0x0ffff1d7u
#define CYREG_SFLASH_IMO_TCTRIM_LT12 0x0ffff1d8u
#define CYREG_SFLASH_IMO_TCTRIM_LT13 0x0ffff1d9u
#define CYREG_SFLASH_IMO_TCTRIM_LT14 0x0ffff1dau
#define CYREG_SFLASH_IMO_TCTRIM_LT15 0x0ffff1dbu
#define CYREG_SFLASH_IMO_TCTRIM_LT16 0x0ffff1dcu
#define CYREG_SFLASH_IMO_TCTRIM_LT17 0x0ffff1ddu
#define CYREG_SFLASH_IMO_TCTRIM_LT18 0x0ffff1deu
#define CYREG_SFLASH_IMO_TCTRIM_LT19 0x0ffff1dfu
#define CYREG_SFLASH_IMO_TCTRIM_LT20 0x0ffff1e0u
#define CYREG_SFLASH_IMO_TCTRIM_LT21 0x0ffff1e1u
#define CYREG_SFLASH_IMO_TCTRIM_LT22 0x0ffff1e2u
#define CYREG_SFLASH_IMO_TCTRIM_LT23 0x0ffff1e3u
#define CYREG_SFLASH_IMO_TCTRIM_LT24 0x0ffff1e4u
#define CYREG_SFLASH_IMO_TRIM_LT0 0x0ffff1e5u
#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_LT1 0x0ffff1e6u
#define CYREG_SFLASH_IMO_TRIM_LT2 0x0ffff1e7u
#define CYREG_SFLASH_IMO_TRIM_LT3 0x0ffff1e8u
#define CYREG_SFLASH_IMO_TRIM_LT4 0x0ffff1e9u
#define CYREG_SFLASH_IMO_TRIM_LT5 0x0ffff1eau
#define CYREG_SFLASH_IMO_TRIM_LT6 0x0ffff1ebu
#define CYREG_SFLASH_IMO_TRIM_LT7 0x0ffff1ecu
#define CYREG_SFLASH_IMO_TRIM_LT8 0x0ffff1edu
#define CYREG_SFLASH_IMO_TRIM_LT9 0x0ffff1eeu
#define CYREG_SFLASH_IMO_TRIM_LT10 0x0ffff1efu
#define CYREG_SFLASH_IMO_TRIM_LT11 0x0ffff1f0u
#define CYREG_SFLASH_IMO_TRIM_LT12 0x0ffff1f1u
#define CYREG_SFLASH_IMO_TRIM_LT13 0x0ffff1f2u
#define CYREG_SFLASH_IMO_TRIM_LT14 0x0ffff1f3u
#define CYREG_SFLASH_IMO_TRIM_LT15 0x0ffff1f4u
#define CYREG_SFLASH_IMO_TRIM_LT16 0x0ffff1f5u
#define CYREG_SFLASH_IMO_TRIM_LT17 0x0ffff1f6u
#define CYREG_SFLASH_IMO_TRIM_LT18 0x0ffff1f7u
#define CYREG_SFLASH_IMO_TRIM_LT19 0x0ffff1f8u
#define CYREG_SFLASH_IMO_TRIM_LT20 0x0ffff1f9u
#define CYREG_SFLASH_IMO_TRIM_LT21 0x0ffff1fau
#define CYREG_SFLASH_IMO_TRIM_LT22 0x0ffff1fbu
#define CYREG_SFLASH_IMO_TRIM_LT23 0x0ffff1fcu
#define CYREG_SFLASH_IMO_TRIM_LT24 0x0ffff1fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff200u
#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000u
#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff201u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff202u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff203u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff204u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff205u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff206u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff207u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff208u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff209u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff20au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff20bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff20cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff20du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff20eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff20fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff210u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff211u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff212u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff213u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff214u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff215u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff216u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff217u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff218u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff219u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff21au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff21bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff21cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff21du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff21eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff21fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff220u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff221u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff222u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff223u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff224u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff225u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff226u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff227u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff228u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff229u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff22au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff22bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff22cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff22du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff22eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff22fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff230u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff231u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff232u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff233u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff234u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff235u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff236u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff237u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff238u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff239u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff23au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff23bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff23cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff23du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff23eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff23fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff240u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff241u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff242u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff243u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff244u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff245u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff246u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff247u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff248u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff249u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff24au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff24bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff24cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff24du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff24eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff24fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff250u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff251u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff252u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff253u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff254u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff255u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff256u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff257u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff258u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff259u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff25au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff25bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff25cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff25du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff25eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff25fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff260u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff261u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff262u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff263u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff264u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff265u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff266u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff267u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff268u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff269u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff26au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff26bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff26cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff26du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff26eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff26fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff270u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff271u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff272u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff273u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff274u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff275u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff276u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff277u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff278u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff279u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff27au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff27bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff27cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff27du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff27eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff27fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff280u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff281u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff282u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff283u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff284u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff285u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff286u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff287u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff288u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff289u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff28au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff28bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff28cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff28du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff28eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff28fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff290u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff291u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff292u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff293u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff294u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff295u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff296u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff297u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff298u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff299u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff29au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff29bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff29cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff29du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff29eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff29fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff2a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff2a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff2a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff2a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff2a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff2a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff2a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff2a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff2a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff2a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff2aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff2abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff2acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff2adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff2aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff2afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff2b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff2b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff2b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff2b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff2b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff2b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff2b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff2b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff2b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff2b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff2bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff2bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff2bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff2bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff2beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff2bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff2c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff2c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff2c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff2c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff2c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff2c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff2c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff2c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff2c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff2c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff2cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff2cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff2ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff2cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff2ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff2cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff2d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff2d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff2d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff2d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff2d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff2d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff2d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff2d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff2d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff2d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff2dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff2dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff2dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff2ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff2deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff2dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff2e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff2e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff2e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff2e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff2e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff2e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff2e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff2e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff2e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff2e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff2eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff2ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff2ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff2edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff2eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff2efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff2f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff2f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff2f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff2f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff2f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff2f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff2f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff2f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff2f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff2f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff2fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff2fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff2fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff2fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff2feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff2ffu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff300u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff301u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff302u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff303u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff304u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff305u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff306u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff307u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff308u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff309u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff30au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff30bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff30cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff30du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff30eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff30fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff310u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff311u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff312u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff313u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff314u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff315u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff316u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff317u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff318u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff319u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff31au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff31bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff31cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff31du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff31eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff31fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff320u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff321u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff322u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff323u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff324u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff325u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff326u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff327u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff328u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff329u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff32au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff32bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff32cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff32du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff32eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff32fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff330u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff331u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff332u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff333u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff334u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff335u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff336u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff337u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff338u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff339u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff33au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff33bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff33cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff33du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff33eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff33fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff340u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff341u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff342u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff343u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff344u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff345u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff346u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff347u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff348u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff349u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff34au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff34bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff34cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff34du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff34eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff34fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff350u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff351u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff352u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff353u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff354u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff355u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff356u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff357u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff358u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff359u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff35au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff35bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff35cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff35du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff35eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff35fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff360u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff361u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff362u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff363u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff364u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff365u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff366u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff367u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff368u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff369u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff36au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff36bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff36cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff36du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff36eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff36fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff370u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff371u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff372u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff373u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff374u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff375u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff376u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff377u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff378u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff379u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff37au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff37bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff37cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff37du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff37eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff37fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff380u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff381u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff382u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff383u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff384u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff385u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff386u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff387u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff388u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff389u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff38au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff38bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff38cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff38du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff38eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff38fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff390u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff391u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff392u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff393u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff394u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff395u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff396u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff397u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff398u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff399u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff39au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff39bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff39cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff39du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff39eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff39fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff3a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff3a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff3a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff3a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff3a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff3a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff3a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff3a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff3a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff3a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff3aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff3abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff3acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff3adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff3aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff3afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff3b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff3b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff3b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff3b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff3b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff3b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff3b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff3b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff3b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff3b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff3bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff3bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff3bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff3bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff3beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff3bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff3c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff3c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff3c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff3c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff3c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff3c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff3c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff3c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff3c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff3c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff3cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff3cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff3ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff3cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff3ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff3cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff3d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff3d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff3d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff3d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff3d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff3d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff3d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff3d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff3d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff3d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff3dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff3dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff3dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff3ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff3deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff3dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff3e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff3e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff3e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff3e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff3e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff3e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff3e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff3e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff3e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff3e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff3eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff3ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff3ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff3edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff3eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff3efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff3f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff3f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff3f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff3f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff3f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff3f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff3f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff3f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff3f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff3f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff3fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff3fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff3fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff3fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff3feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff3ffu
#define CYDEV_ROM_BASE 0x10000000u
#define CYDEV_ROM_SIZE 0x00002000u
#define CYREG_ROM_DATA_MBASE 0x10000000u
#define CYREG_ROM_DATA_MSIZE 0x00002000u
#define CYDEV_SRAM_BASE 0x20000000u
#define CYDEV_SRAM_SIZE 0x00002000u
#define CYREG_SRAM_DATA_MBASE 0x20000000u
#define CYREG_SRAM_DATA_MSIZE 0x00002000u
#define CYDEV_PERI_BASE 0x40010000u
#define CYDEV_PERI_SIZE 0x00010000u
#define CYREG_PERI_DIV_CMD 0x40010000u
#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000u
#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006u
#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000eu
#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_DISABLE__OFFSET 0x0000001eu
#define CYFLD_PERI_DISABLE__SIZE 0x00000001u
#define CYFLD_PERI_ENABLE__OFFSET 0x0000001fu
#define CYFLD_PERI_ENABLE__SIZE 0x00000001u
#define CYREG_PERI_PCLK_CTL0 0x40010100u
/* Duplicate field name in PERI: SEL_DIV [2:0] (previous: [5:0]) */
#define CYREG_PERI_PCLK_CTL1 0x40010104u
#define CYREG_PERI_PCLK_CTL2 0x40010108u
#define CYREG_PERI_PCLK_CTL3 0x4001010cu
#define CYREG_PERI_PCLK_CTL4 0x40010110u
#define CYREG_PERI_PCLK_CTL5 0x40010114u
#define CYREG_PERI_PCLK_CTL6 0x40010118u
#define CYREG_PERI_PCLK_CTL7 0x4001011cu
#define CYREG_PERI_PCLK_CTL8 0x40010120u
#define CYREG_PERI_PCLK_CTL9 0x40010124u
#define CYREG_PERI_PCLK_CTL10 0x40010128u
#define CYREG_PERI_PCLK_CTL11 0x4001012cu
#define CYREG_PERI_PCLK_CTL12 0x40010130u
#define CYREG_PERI_DIV_16_CTL0 0x40010300u
#define CYFLD_PERI_EN__OFFSET 0x00000000u
#define CYFLD_PERI_EN__SIZE 0x00000001u
#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010u
#define CYREG_PERI_DIV_16_CTL1 0x40010304u
#define CYREG_PERI_DIV_16_CTL2 0x40010308u
#define CYREG_PERI_DIV_16_CTL3 0x4001030cu
#define CYREG_PERI_DIV_16_CTL4 0x40010310u
#define CYREG_PERI_DIV_16_CTL5 0x40010314u
#define CYREG_PERI_DIV_16_5_CTL0 0x40010400u
#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003u
#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005u
#define CYREG_PERI_DIV_16_5_CTL1 0x40010404u
#define CYREG_PERI_DIV_16_5_CTL2 0x40010408u
#define CYREG_PERI_TR_CTL 0x40010600u
#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000u
#define CYFLD_PERI_TR_SEL__SIZE 0x00000007u
#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008u
#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004u
#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010u
#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008u
#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001eu
#define CYFLD_PERI_TR_OUT__SIZE 0x00000001u
#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001fu
#define CYFLD_PERI_TR_ACT__SIZE 0x00000001u
#define CYDEV_PERI_TR_GROUP0_BASE 0x40012000u
#define CYDEV_PERI_TR_GROUP0_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 0x40012000u
#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000u
#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000005u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 0x40012004u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 0x40012008u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 0x4001200cu
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 0x40012010u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 0x40012014u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 0x40012018u
#define CYDEV_PERI_TR_GROUP1_BASE 0x40012200u
#define CYDEV_PERI_TR_GROUP1_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL 0x40012200u
#define CYDEV_HSIOM_BASE 0x40020000u
#define CYDEV_HSIOM_SIZE 0x00004000u
#define CYREG_HSIOM_PORT_SEL0 0x40020000u
#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000u
#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000u
#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001u
#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002u
#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003u
#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005u
#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006u
#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007u
#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008u
#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009u
#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000au
#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000bu
#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000eu
#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000fu
#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004u
#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008u
#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000cu
#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010u
#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014u
#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018u
#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001cu
#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004u
#define CYREG_HSIOM_PORT_SEL1 0x40020100u
#define CYREG_HSIOM_PORT_SEL2 0x40020200u
#define CYREG_HSIOM_PORT_SEL3 0x40020300u
#define CYREG_HSIOM_PORT_SEL4 0x40020400u
#define CYREG_HSIOM_AMUX_SPLIT_CTL0 0x40022100u
#define CYFLD_HSIOM_SWITCH_AA_SL__OFFSET 0x00000000u
#define CYFLD_HSIOM_SWITCH_AA_SL__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_SR__OFFSET 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_SR__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_S0__OFFSET 0x00000002u
#define CYFLD_HSIOM_SWITCH_AA_S0__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_SL__OFFSET 0x00000004u
#define CYFLD_HSIOM_SWITCH_BB_SL__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_SR__OFFSET 0x00000005u
#define CYFLD_HSIOM_SWITCH_BB_SR__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_S0__OFFSET 0x00000006u
#define CYFLD_HSIOM_SWITCH_BB_S0__SIZE 0x00000001u
#define CYREG_HSIOM_AMUX_SPLIT_CTL1 0x40022104u
#define CYREG_PWR_CONTROL 0x40030000u
#define CYFLD__POWER_MODE__OFFSET 0x00000000u
#define CYFLD__POWER_MODE__SIZE 0x00000004u
#define CYVAL__POWER_MODE_RESET 0x00000000u
#define CYVAL__POWER_MODE_ACTIVE 0x00000001u
#define CYVAL__POWER_MODE_SLEEP 0x00000002u
#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u
#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u
#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u
#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u
#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u
#define CYFLD__LPM_READY__OFFSET 0x00000005u
#define CYFLD__LPM_READY__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_EN__OFFSET 0x00000010u
#define CYFLD__OVER_TEMP_EN__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_THRESH__OFFSET 0x00000011u
#define CYFLD__OVER_TEMP_THRESH__SIZE 0x00000001u
#define CYFLD__SPARE__OFFSET 0x00000012u
#define CYFLD__SPARE__SIZE 0x00000002u
#define CYFLD__EXT_VCCD__OFFSET 0x00000017u
#define CYFLD__EXT_VCCD__SIZE 0x00000001u
#define CYREG_PWR_KEY_DELAY 0x40030004u
#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_PWR_DDFT_SELECT 0x4003000cu
#define CYFLD__DDFT0_SEL__OFFSET 0x00000000u
#define CYFLD__DDFT0_SEL__SIZE 0x00000004u
#define CYVAL__DDFT0_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT0_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT0_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT0_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT0_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT0_SEL_ACT_REF_EN 0x00000005u
#define CYVAL__DDFT0_SEL_ACT_COMP_EN 0x00000006u
#define CYVAL__DDFT0_SEL_DPSLP_REF_EN 0x00000007u
#define CYVAL__DDFT0_SEL_DPSLP_REG_EN 0x00000008u
#define CYVAL__DDFT0_SEL_DPSLP_COMP_EN 0x00000009u
#define CYVAL__DDFT0_SEL_OVER_TEMP_EN 0x0000000au
#define CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N 0x0000000bu
#define CYVAL__DDFT0_SEL_ADFT_BUF_EN 0x0000000cu
#define CYVAL__DDFT0_SEL_ATPG_OBSERVE 0x0000000du
#define CYVAL__DDFT0_SEL_GND 0x0000000eu
#define CYVAL__DDFT0_SEL_PWR 0x0000000fu
#define CYFLD__DDFT1_SEL__OFFSET 0x00000004u
#define CYFLD__DDFT1_SEL__SIZE 0x00000004u
#define CYVAL__DDFT1_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT1_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT1_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT1_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT1_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT1_SEL_ACT_REF_VALID 0x00000005u
#define CYVAL__DDFT1_SEL_ACT_REG_VALID 0x00000006u
#define CYVAL__DDFT1_SEL_ACT_COMP_OUT 0x00000007u
#define CYVAL__DDFT1_SEL_ACT_TEMP_HIGH 0x00000008u
#define CYVAL__DDFT1_SEL_DPSLP_COMP_OUT 0x00000009u
#define CYVAL__DDFT1_SEL_DPSLP_POWER_UP 0x0000000au
#define CYVAL__DDFT1_SEL_AWAKE_DELAYED 0x0000000bu
#define CYVAL__DDFT1_SEL_LPM_READY 0x0000000cu
#define CYVAL__DDFT1_SEL_SLEEPHOLDACK_N 0x0000000du
#define CYVAL__DDFT1_SEL_GND 0x0000000eu
#define CYVAL__DDFT1_SEL_PWR 0x0000000fu
#define CYREG_TST_MODE 0x40030014u
#define CYFLD__SWD_CONNECTED__OFFSET 0x00000002u
#define CYFLD__SWD_CONNECTED__SIZE 0x00000001u
#define CYFLD__BLOCK_ALT_XRES__OFFSET 0x0000001cu
#define CYFLD__BLOCK_ALT_XRES__SIZE 0x00000001u
#define CYFLD__TEST_KEY_DFT_EN__OFFSET 0x0000001eu
#define CYFLD__TEST_KEY_DFT_EN__SIZE 0x00000001u
#define CYFLD__TEST_MODE__OFFSET 0x0000001fu
#define CYFLD__TEST_MODE__SIZE 0x00000001u
#define CYREG_TST_DDFT_CTRL 0x40030018u
#define CYFLD__DFT_SEL0__OFFSET 0x00000000u
#define CYFLD__DFT_SEL0__SIZE 0x00000004u
#define CYVAL__DFT_SEL0_SRC0 0x00000000u
#define CYVAL__DFT_SEL0_SRC1 0x00000001u
#define CYVAL__DFT_SEL0_SRC2 0x00000002u
#define CYVAL__DFT_SEL0_SRC3 0x00000003u
#define CYVAL__DFT_SEL0_SRC4 0x00000004u
#define CYVAL__DFT_SEL0_SRC5 0x00000005u
#define CYVAL__DFT_SEL0_SRC6 0x00000006u
#define CYVAL__DFT_SEL0_SRC7 0x00000007u
#define CYVAL__DFT_SEL0_CLK0 0x00000008u
#define CYVAL__DFT_SEL0_CLK1 0x00000009u
#define CYVAL__DFT_SEL0_PWR0 0x0000000au
#define CYVAL__DFT_SEL0_PWR1 0x0000000bu
#define CYVAL__DFT_SEL0_RES0 0x0000000cu
#define CYVAL__DFT_SEL0_RES1 0x0000000du
#define CYVAL__DFT_SEL0_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL0_VSS 0x0000000fu
#define CYFLD__DFT_SEL1__OFFSET 0x00000008u
#define CYFLD__DFT_SEL1__SIZE 0x00000004u
#define CYVAL__DFT_SEL1_SRC0 0x00000000u
#define CYVAL__DFT_SEL1_SRC1 0x00000001u
#define CYVAL__DFT_SEL1_SRC2 0x00000002u
#define CYVAL__DFT_SEL1_SRC3 0x00000003u
#define CYVAL__DFT_SEL1_SRC4 0x00000004u
#define CYVAL__DFT_SEL1_SRC5 0x00000005u
#define CYVAL__DFT_SEL1_SRC6 0x00000006u
#define CYVAL__DFT_SEL1_SRC7 0x00000007u
#define CYVAL__DFT_SEL1_CLK0 0x00000008u
#define CYVAL__DFT_SEL1_CLK1 0x00000009u
#define CYVAL__DFT_SEL1_PWR0 0x0000000au
#define CYVAL__DFT_SEL1_PWR1 0x0000000bu
#define CYVAL__DFT_SEL1_RES0 0x0000000cu
#define CYVAL__DFT_SEL1_RES1 0x0000000du
#define CYVAL__DFT_SEL1_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL1_VSS 0x0000000fu
#define CYFLD__ENABLE__OFFSET 0x0000001fu
#define CYFLD__ENABLE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR1 0x4003001cu
#define CYFLD__COUNTER__OFFSET 0x00000000u
#define CYFLD__COUNTER__SIZE 0x00000010u
#define CYFLD__COUNTER_DONE__OFFSET 0x0000001fu
#define CYFLD__COUNTER_DONE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR2 0x40030020u
#define CYREG_TST_ADFT_CTRL 0x40030024u
#define CYFLD__BUF_AUTO_ZERO__OFFSET 0x00000000u
#define CYFLD__BUF_AUTO_ZERO__SIZE 0x00000001u
#define CYFLD__BUF_MODE__OFFSET 0x00000008u
#define CYFLD__BUF_MODE__SIZE 0x00000002u
#define CYFLD__BUF_COMP_OUT__OFFSET 0x00000010u
#define CYFLD__BUF_COMP_OUT__SIZE 0x00000001u
#define CYFLD__BUF_EN__OFFSET 0x0000001fu
#define CYFLD__BUF_EN__SIZE 0x00000001u
#define CYREG_CLK_SELECT 0x40030028u
#define CYFLD__HFCLK_SEL__OFFSET 0x00000000u
#define CYFLD__HFCLK_SEL__SIZE 0x00000002u
#define CYVAL__HFCLK_SEL_IMO 0x00000000u
#define CYVAL__HFCLK_SEL_EXTCLK 0x00000001u
#define CYVAL__HFCLK_SEL_ECO 0x00000002u
#define CYFLD__HFCLK_DIV__OFFSET 0x00000002u
#define CYFLD__HFCLK_DIV__SIZE 0x00000002u
#define CYVAL__HFCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__HFCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__HFCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__HFCLK_DIV_DIV_BY_8 0x00000003u
#define CYFLD__PUMP_SEL__OFFSET 0x00000004u
#define CYFLD__PUMP_SEL__SIZE 0x00000002u
#define CYVAL__PUMP_SEL_GND 0x00000000u
#define CYVAL__PUMP_SEL_IMO 0x00000001u
#define CYVAL__PUMP_SEL_HFCLK 0x00000002u
#define CYFLD__SYSCLK_DIV__OFFSET 0x00000006u
#define CYFLD__SYSCLK_DIV__SIZE 0x00000002u
#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u
#define CYREG_CLK_ILO_CONFIG 0x4003002cu
#define CYREG_CLK_IMO_CONFIG 0x40030030u
#define CYREG_CLK_DFT_SELECT 0x40030034u
#define CYFLD__DFT_DIV0__OFFSET 0x00000004u
#define CYFLD__DFT_DIV0__SIZE 0x00000002u
#define CYVAL__DFT_DIV0_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV0_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV0_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV0_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE0__OFFSET 0x00000006u
#define CYFLD__DFT_EDGE0__SIZE 0x00000001u
#define CYVAL__DFT_EDGE0_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE0_NEGEDGE 0x00000001u
#define CYFLD__DFT_DIV1__OFFSET 0x0000000cu
#define CYFLD__DFT_DIV1__SIZE 0x00000002u
#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE1__OFFSET 0x0000000eu
#define CYFLD__DFT_EDGE1__SIZE 0x00000001u
#define CYVAL__DFT_EDGE1_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE1_NEGEDGE 0x00000001u
#define CYREG_WDT_DISABLE_KEY 0x40030038u
#define CYFLD__KEY__OFFSET 0x00000000u
#define CYFLD__KEY__SIZE 0x00000020u
#define CYREG_WDT_COUNTER 0x4003003cu
#define CYREG_WDT_MATCH 0x40030040u
#define CYFLD__MATCH__OFFSET 0x00000000u
#define CYFLD__MATCH__SIZE 0x00000010u
#define CYFLD__IGNORE_BITS__OFFSET 0x00000010u
#define CYFLD__IGNORE_BITS__SIZE 0x00000004u
#define CYREG_SRSS_INTR 0x40030044u
#define CYFLD__WDT_MATCH__OFFSET 0x00000000u
#define CYFLD__WDT_MATCH__SIZE 0x00000001u
#define CYFLD__TEMP_HIGH__OFFSET 0x00000001u
#define CYFLD__TEMP_HIGH__SIZE 0x00000001u
#define CYREG_SRSS_INTR_SET 0x40030048u
#define CYREG_SRSS_INTR_MASK 0x4003004cu
#define CYREG_RES_CAUSE 0x40030054u
#define CYFLD__RESET_WDT__OFFSET 0x00000000u
#define CYFLD__RESET_WDT__SIZE 0x00000001u
#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u
#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u
#define CYFLD__RESET_SOFT__OFFSET 0x00000004u
#define CYFLD__RESET_SOFT__SIZE 0x00000001u
#define CYREG_PWR_BG_TRIM1 0x40030f00u
#define CYFLD__REF_VTRIM__OFFSET 0x00000000u
#define CYFLD__REF_VTRIM__SIZE 0x00000006u
#define CYREG_PWR_BG_TRIM2 0x40030f04u
#define CYFLD__REF_ITRIM__OFFSET 0x00000000u
#define CYFLD__REF_ITRIM__SIZE 0x00000006u
#define CYREG_CLK_IMO_SELECT 0x40030f08u
#define CYFLD__FREQ__OFFSET 0x00000000u
#define CYFLD__FREQ__SIZE 0x00000003u
#define CYVAL__FREQ_24_MHZ 0x00000000u
#define CYVAL__FREQ_28_MHZ 0x00000001u
#define CYVAL__FREQ_32_MHZ 0x00000002u
#define CYVAL__FREQ_36_MHZ 0x00000003u
#define CYVAL__FREQ_40_MHZ 0x00000004u
#define CYVAL__FREQ_44_MHZ 0x00000005u
#define CYVAL__FREQ_48_MHZ 0x00000006u
#define CYREG_CLK_IMO_TRIM1 0x40030f0cu
#define CYFLD__OFFSET__OFFSET 0x00000000u
#define CYFLD__OFFSET__SIZE 0x00000008u
#define CYREG_CLK_IMO_TRIM2 0x40030f10u
#define CYFLD__FSOFFSET__OFFSET 0x00000000u
#define CYFLD__FSOFFSET__SIZE 0x00000003u
#define CYREG_PWR_PWRSYS_TRIM1 0x40030f14u
#define CYFLD__DPSLP_REF_TRIM__OFFSET 0x00000000u
#define CYFLD__DPSLP_REF_TRIM__SIZE 0x00000004u
#define CYFLD__SPARE_TRIM__OFFSET 0x00000004u
#define CYFLD__SPARE_TRIM__SIZE 0x00000004u
#define CYREG_CLK_IMO_TRIM3 0x40030f18u
#define CYFLD__STEPSIZE__OFFSET 0x00000000u
#define CYFLD__STEPSIZE__SIZE 0x00000005u
#define CYFLD__TCTRIM__OFFSET 0x00000005u
#define CYFLD__TCTRIM__SIZE 0x00000002u
#define CYDEV_GPIO_BASE 0x40040000u
#define CYDEV_GPIO_SIZE 0x00004000u
#define CYDEV_GPIO_PRT0_BASE 0x40040000u
#define CYDEV_GPIO_PRT0_SIZE 0x00000100u
#define CYREG_GPIO_PRT0_DR 0x40040000u
#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PS 0x40040004u
#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC 0x40040008u
#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003u
#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000u
#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001u
#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002u
#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003u
#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004u
#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005u
#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006u
#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007u
#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009u
#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000fu
#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019u
#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001eu
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002u
#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000cu
#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000au
#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000eu
#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003u
#define CYREG_GPIO_PRT0_INTR 0x40040010u
#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011u
#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013u
#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014u
#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016u
#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017u
#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC2 0x40040018u
#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_DR_SET 0x40040040u
#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008u
#define CYREG_GPIO_PRT0_DR_CLR 0x40040044u
#define CYREG_GPIO_PRT0_DR_INV 0x40040048u
#define CYDEV_GPIO_PRT1_BASE 0x40040100u
#define CYDEV_GPIO_PRT1_SIZE 0x00000100u
#define CYREG_GPIO_PRT1_DR 0x40040100u
#define CYREG_GPIO_PRT1_PS 0x40040104u
#define CYREG_GPIO_PRT1_PC 0x40040108u
#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010cu
#define CYREG_GPIO_PRT1_INTR 0x40040110u
#define CYREG_GPIO_PRT1_PC2 0x40040118u
#define CYREG_GPIO_PRT1_DR_SET 0x40040140u
#define CYREG_GPIO_PRT1_DR_CLR 0x40040144u
#define CYREG_GPIO_PRT1_DR_INV 0x40040148u
#define CYDEV_GPIO_PRT2_BASE 0x40040200u
#define CYDEV_GPIO_PRT2_SIZE 0x00000100u
#define CYREG_GPIO_PRT2_DR 0x40040200u
#define CYREG_GPIO_PRT2_PS 0x40040204u
#define CYREG_GPIO_PRT2_PC 0x40040208u
#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020cu
#define CYREG_GPIO_PRT2_INTR 0x40040210u
#define CYREG_GPIO_PRT2_PC2 0x40040218u
#define CYREG_GPIO_PRT2_DR_SET 0x40040240u
#define CYREG_GPIO_PRT2_DR_CLR 0x40040244u
#define CYREG_GPIO_PRT2_DR_INV 0x40040248u
#define CYDEV_GPIO_PRT3_BASE 0x40040300u
#define CYDEV_GPIO_PRT3_SIZE 0x00000100u
#define CYREG_GPIO_PRT3_DR 0x40040300u
#define CYREG_GPIO_PRT3_PS 0x40040304u
#define CYREG_GPIO_PRT3_PC 0x40040308u
#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030cu
#define CYREG_GPIO_PRT3_INTR 0x40040310u
#define CYREG_GPIO_PRT3_PC2 0x40040318u
#define CYREG_GPIO_PRT3_DR_SET 0x40040340u
#define CYREG_GPIO_PRT3_DR_CLR 0x40040344u
#define CYREG_GPIO_PRT3_DR_INV 0x40040348u
#define CYDEV_GPIO_PRT4_BASE 0x40040400u
#define CYDEV_GPIO_PRT4_SIZE 0x00000100u
#define CYREG_GPIO_PRT4_DR 0x40040400u
#define CYREG_GPIO_PRT4_PS 0x40040404u
#define CYREG_GPIO_PRT4_PC 0x40040408u
#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040cu
#define CYREG_GPIO_PRT4_INTR 0x40040410u
#define CYREG_GPIO_PRT4_PC2 0x40040418u
#define CYREG_GPIO_PRT4_DR_SET 0x40040440u
#define CYREG_GPIO_PRT4_DR_CLR 0x40040444u
#define CYREG_GPIO_PRT4_DR_INV 0x40040448u
#define CYREG_GPIO_INTR_CAUSE 0x40041000u
#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000u
#define CYFLD_GPIO_PORT_INT__SIZE 0x00000005u
#define CYDEV_PRGIO_BASE 0x40050000u
#define CYDEV_PRGIO_SIZE 0x00001000u
#define CYDEV_PRGIO_PRT0_BASE 0x40050000u
#define CYDEV_PRGIO_PRT0_SIZE 0x00000100u
#define CYREG_PRGIO_PRT0_CTL 0x40050000u
#define CYFLD_PRGIO_PRT_BYPASS__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_BYPASS__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE 0x00000005u
#define CYFLD_PRGIO_PRT_HLD_OVR__OFFSET 0x00000018u
#define CYFLD_PRGIO_PRT_HLD_OVR__SIZE 0x00000001u
#define CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET 0x00000019u
#define CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE 0x00000001u
#define CYFLD_PRGIO_PRT_ENABLED__OFFSET 0x0000001fu
#define CYFLD_PRGIO_PRT_ENABLED__SIZE 0x00000001u
#define CYREG_PRGIO_PRT0_SYNC_CTL 0x40050010u
#define CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE 0x00000008u
#define CYREG_PRGIO_PRT0_LUT_SEL0 0x40050020u
#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET 0x00000010u
#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE 0x00000004u
#define CYREG_PRGIO_PRT0_LUT_SEL1 0x40050024u
#define CYREG_PRGIO_PRT0_LUT_SEL2 0x40050028u
#define CYREG_PRGIO_PRT0_LUT_SEL3 0x4005002cu
#define CYREG_PRGIO_PRT0_LUT_SEL4 0x40050030u
#define CYREG_PRGIO_PRT0_LUT_SEL5 0x40050034u
#define CYREG_PRGIO_PRT0_LUT_SEL6 0x40050038u
#define CYREG_PRGIO_PRT0_LUT_SEL7 0x4005003cu
#define CYREG_PRGIO_PRT0_LUT_CTL0 0x40050040u
#define CYFLD_PRGIO_PRT_LUT__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_LUT__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_OPC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_OPC__SIZE 0x00000002u
#define CYREG_PRGIO_PRT0_LUT_CTL1 0x40050044u
#define CYREG_PRGIO_PRT0_LUT_CTL2 0x40050048u
#define CYREG_PRGIO_PRT0_LUT_CTL3 0x4005004cu
#define CYREG_PRGIO_PRT0_LUT_CTL4 0x40050050u
#define CYREG_PRGIO_PRT0_LUT_CTL5 0x40050054u
#define CYREG_PRGIO_PRT0_LUT_CTL6 0x40050058u
#define CYREG_PRGIO_PRT0_LUT_CTL7 0x4005005cu
#define CYREG_PRGIO_PRT0_DU_SEL 0x400500c0u
#define CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET 0x00000010u
#define CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET 0x00000018u
#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE 0x00000002u
#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET 0x0000001cu
#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE 0x00000002u
#define CYREG_PRGIO_PRT0_DU_CTL 0x400500c4u
#define CYFLD_PRGIO_PRT_DU_SIZE__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DU_SIZE__SIZE 0x00000003u
#define CYFLD_PRGIO_PRT_DU_OPC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_DU_OPC__SIZE 0x00000004u
#define CYREG_PRGIO_PRT0_DATA 0x400500f0u
#define CYFLD_PRGIO_PRT_DATA__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DATA__SIZE 0x00000008u
#define CYDEV_PRGIO_PRT1_BASE 0x40050100u
#define CYDEV_PRGIO_PRT1_SIZE 0x00000100u
#define CYREG_PRGIO_PRT1_CTL 0x40050100u
#define CYREG_PRGIO_PRT1_SYNC_CTL 0x40050110u
#define CYREG_PRGIO_PRT1_LUT_SEL0 0x40050120u
#define CYREG_PRGIO_PRT1_LUT_SEL1 0x40050124u
#define CYREG_PRGIO_PRT1_LUT_SEL2 0x40050128u
#define CYREG_PRGIO_PRT1_LUT_SEL3 0x4005012cu
#define CYREG_PRGIO_PRT1_LUT_SEL4 0x40050130u
#define CYREG_PRGIO_PRT1_LUT_SEL5 0x40050134u
#define CYREG_PRGIO_PRT1_LUT_SEL6 0x40050138u
#define CYREG_PRGIO_PRT1_LUT_SEL7 0x4005013cu
#define CYREG_PRGIO_PRT1_LUT_CTL0 0x40050140u
#define CYREG_PRGIO_PRT1_LUT_CTL1 0x40050144u
#define CYREG_PRGIO_PRT1_LUT_CTL2 0x40050148u
#define CYREG_PRGIO_PRT1_LUT_CTL3 0x4005014cu
#define CYREG_PRGIO_PRT1_LUT_CTL4 0x40050150u
#define CYREG_PRGIO_PRT1_LUT_CTL5 0x40050154u
#define CYREG_PRGIO_PRT1_LUT_CTL6 0x40050158u
#define CYREG_PRGIO_PRT1_LUT_CTL7 0x4005015cu
#define CYREG_PRGIO_PRT1_DU_SEL 0x400501c0u
#define CYREG_PRGIO_PRT1_DU_CTL 0x400501c4u
#define CYREG_PRGIO_PRT1_DATA 0x400501f0u
#define CYDEV_TCPWM_BASE 0x40060000u
#define CYDEV_TCPWM_SIZE 0x00010000u
#define CYREG_TCPWM_CTRL 0x40060000u
#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000005u
#define CYREG_TCPWM_CMD 0x40060008u
#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000005u
#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000005u
#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u
#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000005u
#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u
#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000005u
#define CYREG_TCPWM_INTR_CAUSE 0x4006000cu
#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000005u
#define CYDEV_TCPWM_CNT0_BASE 0x40060100u
#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u
#define CYREG_TCPWM_CNT0_CTRL 0x40060100u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u
#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u
#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u
#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u
#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u
#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u
#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u
#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u
#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u
#define CYREG_TCPWM_CNT0_STATUS 0x40060104u
#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu
#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_COUNTER 0x40060108u
#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC 0x4006010cu
#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC_BUFF 0x40060110u
#define CYREG_TCPWM_CNT0_PERIOD 0x40060114u
#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40060118u
#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40060120u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu
#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u
#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40060124u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u
#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u
#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40060128u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYREG_TCPWM_CNT0_INTR 0x40060130u
#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_INTR_SET 0x40060134u
#define CYREG_TCPWM_CNT0_INTR_MASK 0x40060138u
#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4006013cu
#define CYDEV_TCPWM_CNT1_BASE 0x40060140u
#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u
#define CYREG_TCPWM_CNT1_CTRL 0x40060140u
#define CYREG_TCPWM_CNT1_STATUS 0x40060144u
#define CYREG_TCPWM_CNT1_COUNTER 0x40060148u
#define CYREG_TCPWM_CNT1_CC 0x4006014cu
#define CYREG_TCPWM_CNT1_CC_BUFF 0x40060150u
#define CYREG_TCPWM_CNT1_PERIOD 0x40060154u
#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40060158u
#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40060160u
#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40060164u
#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40060168u
#define CYREG_TCPWM_CNT1_INTR 0x40060170u
#define CYREG_TCPWM_CNT1_INTR_SET 0x40060174u
#define CYREG_TCPWM_CNT1_INTR_MASK 0x40060178u
#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4006017cu
#define CYDEV_TCPWM_CNT2_BASE 0x40060180u
#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u
#define CYREG_TCPWM_CNT2_CTRL 0x40060180u
#define CYREG_TCPWM_CNT2_STATUS 0x40060184u
#define CYREG_TCPWM_CNT2_COUNTER 0x40060188u
#define CYREG_TCPWM_CNT2_CC 0x4006018cu
#define CYREG_TCPWM_CNT2_CC_BUFF 0x40060190u
#define CYREG_TCPWM_CNT2_PERIOD 0x40060194u
#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40060198u
#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400601a0u
#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400601a4u
#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400601a8u
#define CYREG_TCPWM_CNT2_INTR 0x400601b0u
#define CYREG_TCPWM_CNT2_INTR_SET 0x400601b4u
#define CYREG_TCPWM_CNT2_INTR_MASK 0x400601b8u
#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400601bcu
#define CYDEV_TCPWM_CNT3_BASE 0x400601c0u
#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u
#define CYREG_TCPWM_CNT3_CTRL 0x400601c0u
#define CYREG_TCPWM_CNT3_STATUS 0x400601c4u
#define CYREG_TCPWM_CNT3_COUNTER 0x400601c8u
#define CYREG_TCPWM_CNT3_CC 0x400601ccu
#define CYREG_TCPWM_CNT3_CC_BUFF 0x400601d0u
#define CYREG_TCPWM_CNT3_PERIOD 0x400601d4u
#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400601d8u
#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400601e0u
#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400601e4u
#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400601e8u
#define CYREG_TCPWM_CNT3_INTR 0x400601f0u
#define CYREG_TCPWM_CNT3_INTR_SET 0x400601f4u
#define CYREG_TCPWM_CNT3_INTR_MASK 0x400601f8u
#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400601fcu
#define CYDEV_TCPWM_CNT4_BASE 0x40060200u
#define CYDEV_TCPWM_CNT4_SIZE 0x00000040u
#define CYREG_TCPWM_CNT4_CTRL 0x40060200u
#define CYREG_TCPWM_CNT4_STATUS 0x40060204u
#define CYREG_TCPWM_CNT4_COUNTER 0x40060208u
#define CYREG_TCPWM_CNT4_CC 0x4006020cu
#define CYREG_TCPWM_CNT4_CC_BUFF 0x40060210u
#define CYREG_TCPWM_CNT4_PERIOD 0x40060214u
#define CYREG_TCPWM_CNT4_PERIOD_BUFF 0x40060218u
#define CYREG_TCPWM_CNT4_TR_CTRL0 0x40060220u
#define CYREG_TCPWM_CNT4_TR_CTRL1 0x40060224u
#define CYREG_TCPWM_CNT4_TR_CTRL2 0x40060228u
#define CYREG_TCPWM_CNT4_INTR 0x40060230u
#define CYREG_TCPWM_CNT4_INTR_SET 0x40060234u
#define CYREG_TCPWM_CNT4_INTR_MASK 0x40060238u
#define CYREG_TCPWM_CNT4_INTR_MASKED 0x4006023cu
#define CYDEV_WCO_BASE 0x40070000u
#define CYDEV_WCO_SIZE 0x00010000u
#define CYREG_WCO_CONFIG 0x40070000u
#define CYFLD_WCO_LPM_EN__OFFSET 0x00000000u
#define CYFLD_WCO_LPM_EN__SIZE 0x00000001u
#define CYFLD_WCO_LPM_AUTO__OFFSET 0x00000001u
#define CYFLD_WCO_LPM_AUTO__SIZE 0x00000001u
#define CYFLD_WCO_EXT_INPUT_EN__OFFSET 0x00000002u
#define CYFLD_WCO_EXT_INPUT_EN__SIZE 0x00000001u
#define CYFLD_WCO_ENBUS__OFFSET 0x00000010u
#define CYFLD_WCO_ENBUS__SIZE 0x00000008u
#define CYFLD_WCO_DPLL_ENABLE__OFFSET 0x0000001eu
#define CYFLD_WCO_DPLL_ENABLE__SIZE 0x00000001u
#define CYFLD_WCO_IP_ENABLE__OFFSET 0x0000001fu
#define CYFLD_WCO_IP_ENABLE__SIZE 0x00000001u
#define CYREG_WCO_STATUS 0x40070004u
#define CYFLD_WCO_OUT_BLNK_A__OFFSET 0x00000000u
#define CYFLD_WCO_OUT_BLNK_A__SIZE 0x00000001u
#define CYREG_WCO_DPLL 0x40070008u
#define CYFLD_WCO_DPLL_MULT__OFFSET 0x00000000u
#define CYFLD_WCO_DPLL_MULT__SIZE 0x0000000bu
#define CYFLD_WCO_DPLL_LF_IGAIN__OFFSET 0x00000010u
#define CYFLD_WCO_DPLL_LF_IGAIN__SIZE 0x00000003u
#define CYFLD_WCO_DPLL_LF_PGAIN__OFFSET 0x00000013u
#define CYFLD_WCO_DPLL_LF_PGAIN__SIZE 0x00000003u
#define CYFLD_WCO_DPLL_LF_LIMIT__OFFSET 0x00000016u
#define CYFLD_WCO_DPLL_LF_LIMIT__SIZE 0x00000008u
#define CYREG_WCO_WDT_CTRLOW 0x40070200u
#define CYFLD_WCO_WDT_CTR0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_CTR0__SIZE 0x00000010u
#define CYFLD_WCO_WDT_CTR1__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_CTR1__SIZE 0x00000010u
#define CYREG_WCO_WDT_CTRHIGH 0x40070204u
#define CYFLD_WCO_WDT_CTR2__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_CTR2__SIZE 0x00000020u
#define CYREG_WCO_WDT_MATCH 0x40070208u
#define CYFLD_WCO_WDT_MATCH0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_MATCH0__SIZE 0x00000010u
#define CYFLD_WCO_WDT_MATCH1__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_MATCH1__SIZE 0x00000010u
#define CYREG_WCO_WDT_CONFIG 0x4007020cu
#define CYFLD_WCO_WDT_MODE0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_MODE0__SIZE 0x00000002u
#define CYVAL_WCO_WDT_MODE0_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE0_INT 0x00000001u
#define CYVAL_WCO_WDT_MODE0_RESET 0x00000002u
#define CYVAL_WCO_WDT_MODE0_INT_THEN_RESET 0x00000003u
#define CYFLD_WCO_WDT_CLEAR0__OFFSET 0x00000002u
#define CYFLD_WCO_WDT_CLEAR0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_CASCADE0_1__OFFSET 0x00000003u
#define CYFLD_WCO_WDT_CASCADE0_1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_MODE1__OFFSET 0x00000008u
#define CYFLD_WCO_WDT_MODE1__SIZE 0x00000002u
#define CYVAL_WCO_WDT_MODE1_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE1_INT 0x00000001u
#define CYVAL_WCO_WDT_MODE1_RESET 0x00000002u
#define CYVAL_WCO_WDT_MODE1_INT_THEN_RESET 0x00000003u
#define CYFLD_WCO_WDT_CLEAR1__OFFSET 0x0000000au
#define CYFLD_WCO_WDT_CLEAR1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_CASCADE1_2__OFFSET 0x0000000bu
#define CYFLD_WCO_WDT_CASCADE1_2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_MODE2__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_MODE2__SIZE 0x00000001u
#define CYVAL_WCO_WDT_MODE2_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE2_INT 0x00000001u
#define CYFLD_WCO_WDT_BITS2__OFFSET 0x00000018u
#define CYFLD_WCO_WDT_BITS2__SIZE 0x00000005u
#define CYFLD_WCO_LFCLK_SEL__OFFSET 0x0000001eu
#define CYFLD_WCO_LFCLK_SEL__SIZE 0x00000002u
#define CYREG_WCO_WDT_CONTROL 0x40070210u
#define CYFLD_WCO_WDT_ENABLE0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_ENABLE0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED0__OFFSET 0x00000001u
#define CYFLD_WCO_WDT_ENABLED0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT0__OFFSET 0x00000002u
#define CYFLD_WCO_WDT_INT0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET0__OFFSET 0x00000003u
#define CYFLD_WCO_WDT_RESET0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLE1__OFFSET 0x00000008u
#define CYFLD_WCO_WDT_ENABLE1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED1__OFFSET 0x00000009u
#define CYFLD_WCO_WDT_ENABLED1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT1__OFFSET 0x0000000au
#define CYFLD_WCO_WDT_INT1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET1__OFFSET 0x0000000bu
#define CYFLD_WCO_WDT_RESET1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLE2__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_ENABLE2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED2__OFFSET 0x00000011u
#define CYFLD_WCO_WDT_ENABLED2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT2__OFFSET 0x00000012u
#define CYFLD_WCO_WDT_INT2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET2__OFFSET 0x00000013u
#define CYFLD_WCO_WDT_RESET2__SIZE 0x00000001u
#define CYREG_WCO_WDT_CLKEN 0x40070214u
#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET 0x00000000u
#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE 0x00000001u
#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET 0x00000001u
#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE 0x00000001u
#define CYREG_WCO_TRIM 0x40070f00u
#define CYFLD_WCO_XGM__OFFSET 0x00000000u
#define CYFLD_WCO_XGM__SIZE 0x00000003u
#define CYFLD_WCO_LPM_GM__OFFSET 0x00000004u
#define CYFLD_WCO_LPM_GM__SIZE 0x00000002u
#define CYDEV_SCB0_BASE 0x40080000u
#define CYDEV_SCB0_SIZE 0x00010000u
#define CYREG_SCB0_CTRL 0x40080000u
#define CYFLD_SCB_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_OVS__SIZE 0x00000004u
#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u
#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u
#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u
#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000bu
#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001u
#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u
#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u
#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u
#define CYFLD_SCB_BLOCK__SIZE 0x00000001u
#define CYFLD_SCB_MODE__OFFSET 0x00000018u
#define CYFLD_SCB_MODE__SIZE 0x00000002u
#define CYVAL_SCB_MODE_I2C 0x00000000u
#define CYVAL_SCB_MODE_SPI 0x00000001u
#define CYVAL_SCB_MODE_UART 0x00000002u
#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SCB_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_STATUS 0x40080004u
#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u
#define CYREG_SCB0_SPI_CTRL 0x40080020u
#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u
#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u
#define CYFLD_SCB_CPHA__OFFSET 0x00000002u
#define CYFLD_SCB_CPHA__SIZE 0x00000001u
#define CYFLD_SCB_CPOL__OFFSET 0x00000003u
#define CYFLD_SCB_CPOL__SIZE 0x00000001u
#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u
#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u
#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005u
#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008u
#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009u
#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000au
#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000bu
#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001u
#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u
#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au
#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u
#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu
#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u
#define CYREG_SCB0_SPI_STATUS 0x40080024u
#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008u
#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010u
#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008u
#define CYREG_SCB0_UART_CTRL 0x40080040u
#define CYREG_SCB0_UART_TX_CTRL 0x40080044u
#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u
#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u
#define CYFLD_SCB_PARITY__OFFSET 0x00000004u
#define CYFLD_SCB_PARITY__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u
#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u
#define CYREG_SCB0_UART_RX_CTRL 0x40080048u
#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u
#define CYFLD_SCB_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu
#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u
#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du
#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u
#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u
#define CYREG_SCB0_UART_RX_STATUS 0x4008004cu
#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u
#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu
#define CYREG_SCB0_UART_FLOW_CTRL 0x40080050u
#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000004u
#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010u
#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018u
#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019u
#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CTRL 0x40080060u
#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u
#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu
#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu
#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du
#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu
#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u
#define CYREG_SCB0_I2C_STATUS 0x40080064u
#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_S_READ__OFFSET 0x00000004u
#define CYFLD_SCB_S_READ__SIZE 0x00000001u
#define CYFLD_SCB_M_READ__OFFSET 0x00000005u
#define CYFLD_SCB_M_READ__SIZE 0x00000001u
#define CYREG_SCB0_I2C_M_CMD 0x40080068u
#define CYFLD_SCB_M_START__OFFSET 0x00000000u
#define CYFLD_SCB_M_START__SIZE 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u
#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_M_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u
#define CYFLD_SCB_M_NACK__SIZE 0x00000001u
#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_M_STOP__SIZE 0x00000001u
#define CYREG_SCB0_I2C_S_CMD 0x4008006cu
#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u
#define CYFLD_SCB_S_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_S_NACK__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CFG 0x40080070u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004u
#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000cu
#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001cu
#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002u
#define CYREG_SCB0_TX_CTRL 0x40080200u
#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u
#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u
#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u
#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_CTRL 0x40080204u
#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u
#define CYFLD_SCB_CLEAR__SIZE 0x00000001u
#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u
#define CYFLD_SCB_FREEZE__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_STATUS 0x40080208u
#define CYFLD_SCB_USED__OFFSET 0x00000000u
#define CYFLD_SCB_USED__SIZE 0x00000005u
#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu
#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u
#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u
#define CYFLD_SCB_RD_PTR__SIZE 0x00000004u
#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u
#define CYFLD_SCB_WR_PTR__SIZE 0x00000004u
#define CYREG_SCB0_TX_FIFO_WR 0x40080240u
#define CYFLD_SCB_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_DATA__SIZE 0x00000010u
#define CYREG_SCB0_RX_CTRL 0x40080300u
#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u
#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u
#define CYREG_SCB0_RX_FIFO_CTRL 0x40080304u
#define CYREG_SCB0_RX_FIFO_STATUS 0x40080308u
#define CYREG_SCB0_RX_MATCH 0x40080310u
#define CYFLD_SCB_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_MASK__OFFSET 0x00000010u
#define CYFLD_SCB_MASK__SIZE 0x00000008u
#define CYREG_SCB0_RX_FIFO_RD 0x40080340u
#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40080344u
#define CYREG_SCB0_EZ_DATA0 0x40080400u
#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u
#define CYREG_SCB0_EZ_DATA1 0x40080404u
#define CYREG_SCB0_EZ_DATA2 0x40080408u
#define CYREG_SCB0_EZ_DATA3 0x4008040cu
#define CYREG_SCB0_EZ_DATA4 0x40080410u
#define CYREG_SCB0_EZ_DATA5 0x40080414u
#define CYREG_SCB0_EZ_DATA6 0x40080418u
#define CYREG_SCB0_EZ_DATA7 0x4008041cu
#define CYREG_SCB0_EZ_DATA8 0x40080420u
#define CYREG_SCB0_EZ_DATA9 0x40080424u
#define CYREG_SCB0_EZ_DATA10 0x40080428u
#define CYREG_SCB0_EZ_DATA11 0x4008042cu
#define CYREG_SCB0_EZ_DATA12 0x40080430u
#define CYREG_SCB0_EZ_DATA13 0x40080434u
#define CYREG_SCB0_EZ_DATA14 0x40080438u
#define CYREG_SCB0_EZ_DATA15 0x4008043cu
#define CYREG_SCB0_EZ_DATA16 0x40080440u
#define CYREG_SCB0_EZ_DATA17 0x40080444u
#define CYREG_SCB0_EZ_DATA18 0x40080448u
#define CYREG_SCB0_EZ_DATA19 0x4008044cu
#define CYREG_SCB0_EZ_DATA20 0x40080450u
#define CYREG_SCB0_EZ_DATA21 0x40080454u
#define CYREG_SCB0_EZ_DATA22 0x40080458u
#define CYREG_SCB0_EZ_DATA23 0x4008045cu
#define CYREG_SCB0_EZ_DATA24 0x40080460u
#define CYREG_SCB0_EZ_DATA25 0x40080464u
#define CYREG_SCB0_EZ_DATA26 0x40080468u
#define CYREG_SCB0_EZ_DATA27 0x4008046cu
#define CYREG_SCB0_EZ_DATA28 0x40080470u
#define CYREG_SCB0_EZ_DATA29 0x40080474u
#define CYREG_SCB0_EZ_DATA30 0x40080478u
#define CYREG_SCB0_EZ_DATA31 0x4008047cu
#define CYREG_SCB0_INTR_CAUSE 0x40080e00u
#define CYFLD_SCB_M__OFFSET 0x00000000u
#define CYFLD_SCB_M__SIZE 0x00000001u
#define CYFLD_SCB_S__OFFSET 0x00000001u
#define CYFLD_SCB_S__SIZE 0x00000001u
#define CYFLD_SCB_TX__OFFSET 0x00000002u
#define CYFLD_SCB_TX__SIZE 0x00000001u
#define CYFLD_SCB_RX__OFFSET 0x00000003u
#define CYFLD_SCB_RX__SIZE 0x00000001u
#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u
#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC 0x40080e80u
#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u
#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u
#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u
#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40080e88u
#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40080e8cu
#define CYREG_SCB0_INTR_SPI_EC 0x40080ec0u
#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40080ec8u
#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40080eccu
#define CYREG_SCB0_INTR_M 0x40080f00u
#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u
#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u
#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u
#define CYREG_SCB0_INTR_M_SET 0x40080f04u
#define CYREG_SCB0_INTR_M_MASK 0x40080f08u
#define CYREG_SCB0_INTR_M_MASKED 0x40080f0cu
#define CYREG_SCB0_INTR_S 0x40080f40u
#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u
#define CYFLD_SCB_I2C_START__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u
#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u
#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u
#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au
#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu
#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u
#define CYREG_SCB0_INTR_S_SET 0x40080f44u
#define CYREG_SCB0_INTR_S_MASK 0x40080f48u
#define CYREG_SCB0_INTR_S_MASKED 0x40080f4cu
#define CYREG_SCB0_INTR_TX 0x40080f80u
#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u
#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u
#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u
#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u
#define CYFLD_SCB_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u
#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u
#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u
#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u
#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u
#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u
#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au
#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u
#define CYREG_SCB0_INTR_TX_SET 0x40080f84u
#define CYREG_SCB0_INTR_TX_MASK 0x40080f88u
#define CYREG_SCB0_INTR_TX_MASKED 0x40080f8cu
#define CYREG_SCB0_INTR_RX 0x40080fc0u
#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u
#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_FULL__OFFSET 0x00000003u
#define CYFLD_SCB_FULL__SIZE 0x00000001u
#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au
#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu
#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u
#define CYREG_SCB0_INTR_RX_SET 0x40080fc4u
#define CYREG_SCB0_INTR_RX_MASK 0x40080fc8u
#define CYREG_SCB0_INTR_RX_MASKED 0x40080fccu
#define CYDEV_SCB1_BASE 0x40090000u
#define CYDEV_SCB1_SIZE 0x00010000u
#define CYREG_SCB1_CTRL 0x40090000u
#define CYREG_SCB1_STATUS 0x40090004u
#define CYREG_SCB1_SPI_CTRL 0x40090020u
#define CYREG_SCB1_SPI_STATUS 0x40090024u
#define CYREG_SCB1_UART_CTRL 0x40090040u
#define CYREG_SCB1_UART_TX_CTRL 0x40090044u
#define CYREG_SCB1_UART_RX_CTRL 0x40090048u
#define CYREG_SCB1_UART_RX_STATUS 0x4009004cu
#define CYREG_SCB1_UART_FLOW_CTRL 0x40090050u
#define CYREG_SCB1_I2C_CTRL 0x40090060u
#define CYREG_SCB1_I2C_STATUS 0x40090064u
#define CYREG_SCB1_I2C_M_CMD 0x40090068u
#define CYREG_SCB1_I2C_S_CMD 0x4009006cu
#define CYREG_SCB1_I2C_CFG 0x40090070u
#define CYREG_SCB1_TX_CTRL 0x40090200u
#define CYREG_SCB1_TX_FIFO_CTRL 0x40090204u
#define CYREG_SCB1_TX_FIFO_STATUS 0x40090208u
#define CYREG_SCB1_TX_FIFO_WR 0x40090240u
#define CYREG_SCB1_RX_CTRL 0x40090300u
#define CYREG_SCB1_RX_FIFO_CTRL 0x40090304u
#define CYREG_SCB1_RX_FIFO_STATUS 0x40090308u
#define CYREG_SCB1_RX_MATCH 0x40090310u
#define CYREG_SCB1_RX_FIFO_RD 0x40090340u
#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40090344u
#define CYREG_SCB1_EZ_DATA0 0x40090400u
#define CYREG_SCB1_EZ_DATA1 0x40090404u
#define CYREG_SCB1_EZ_DATA2 0x40090408u
#define CYREG_SCB1_EZ_DATA3 0x4009040cu
#define CYREG_SCB1_EZ_DATA4 0x40090410u
#define CYREG_SCB1_EZ_DATA5 0x40090414u
#define CYREG_SCB1_EZ_DATA6 0x40090418u
#define CYREG_SCB1_EZ_DATA7 0x4009041cu
#define CYREG_SCB1_EZ_DATA8 0x40090420u
#define CYREG_SCB1_EZ_DATA9 0x40090424u
#define CYREG_SCB1_EZ_DATA10 0x40090428u
#define CYREG_SCB1_EZ_DATA11 0x4009042cu
#define CYREG_SCB1_EZ_DATA12 0x40090430u
#define CYREG_SCB1_EZ_DATA13 0x40090434u
#define CYREG_SCB1_EZ_DATA14 0x40090438u
#define CYREG_SCB1_EZ_DATA15 0x4009043cu
#define CYREG_SCB1_EZ_DATA16 0x40090440u
#define CYREG_SCB1_EZ_DATA17 0x40090444u
#define CYREG_SCB1_EZ_DATA18 0x40090448u
#define CYREG_SCB1_EZ_DATA19 0x4009044cu
#define CYREG_SCB1_EZ_DATA20 0x40090450u
#define CYREG_SCB1_EZ_DATA21 0x40090454u
#define CYREG_SCB1_EZ_DATA22 0x40090458u
#define CYREG_SCB1_EZ_DATA23 0x4009045cu
#define CYREG_SCB1_EZ_DATA24 0x40090460u
#define CYREG_SCB1_EZ_DATA25 0x40090464u
#define CYREG_SCB1_EZ_DATA26 0x40090468u
#define CYREG_SCB1_EZ_DATA27 0x4009046cu
#define CYREG_SCB1_EZ_DATA28 0x40090470u
#define CYREG_SCB1_EZ_DATA29 0x40090474u
#define CYREG_SCB1_EZ_DATA30 0x40090478u
#define CYREG_SCB1_EZ_DATA31 0x4009047cu
#define CYREG_SCB1_INTR_CAUSE 0x40090e00u
#define CYREG_SCB1_INTR_I2C_EC 0x40090e80u
#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40090e88u
#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40090e8cu
#define CYREG_SCB1_INTR_SPI_EC 0x40090ec0u
#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40090ec8u
#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40090eccu
#define CYREG_SCB1_INTR_M 0x40090f00u
#define CYREG_SCB1_INTR_M_SET 0x40090f04u
#define CYREG_SCB1_INTR_M_MASK 0x40090f08u
#define CYREG_SCB1_INTR_M_MASKED 0x40090f0cu
#define CYREG_SCB1_INTR_S 0x40090f40u
#define CYREG_SCB1_INTR_S_SET 0x40090f44u
#define CYREG_SCB1_INTR_S_MASK 0x40090f48u
#define CYREG_SCB1_INTR_S_MASKED 0x40090f4cu
#define CYREG_SCB1_INTR_TX 0x40090f80u
#define CYREG_SCB1_INTR_TX_SET 0x40090f84u
#define CYREG_SCB1_INTR_TX_MASK 0x40090f88u
#define CYREG_SCB1_INTR_TX_MASKED 0x40090f8cu
#define CYREG_SCB1_INTR_RX 0x40090fc0u
#define CYREG_SCB1_INTR_RX_SET 0x40090fc4u
#define CYREG_SCB1_INTR_RX_MASK 0x40090fc8u
#define CYREG_SCB1_INTR_RX_MASKED 0x40090fccu
#define CYDEV_SCB2_BASE 0x400a0000u
#define CYDEV_SCB2_SIZE 0x00010000u
#define CYREG_SCB2_CTRL 0x400a0000u
#define CYREG_SCB2_STATUS 0x400a0004u
#define CYREG_SCB2_SPI_CTRL 0x400a0020u
#define CYREG_SCB2_SPI_STATUS 0x400a0024u
#define CYREG_SCB2_UART_CTRL 0x400a0040u
#define CYREG_SCB2_UART_TX_CTRL 0x400a0044u
#define CYREG_SCB2_UART_RX_CTRL 0x400a0048u
#define CYREG_SCB2_UART_RX_STATUS 0x400a004cu
#define CYREG_SCB2_UART_FLOW_CTRL 0x400a0050u
#define CYREG_SCB2_I2C_CTRL 0x400a0060u
#define CYREG_SCB2_I2C_STATUS 0x400a0064u
#define CYREG_SCB2_I2C_M_CMD 0x400a0068u
#define CYREG_SCB2_I2C_S_CMD 0x400a006cu
#define CYREG_SCB2_I2C_CFG 0x400a0070u
#define CYREG_SCB2_TX_CTRL 0x400a0200u
#define CYREG_SCB2_TX_FIFO_CTRL 0x400a0204u
#define CYREG_SCB2_TX_FIFO_STATUS 0x400a0208u
#define CYREG_SCB2_TX_FIFO_WR 0x400a0240u
#define CYREG_SCB2_RX_CTRL 0x400a0300u
#define CYREG_SCB2_RX_FIFO_CTRL 0x400a0304u
#define CYREG_SCB2_RX_FIFO_STATUS 0x400a0308u
#define CYREG_SCB2_RX_MATCH 0x400a0310u
#define CYREG_SCB2_RX_FIFO_RD 0x400a0340u
#define CYREG_SCB2_RX_FIFO_RD_SILENT 0x400a0344u
#define CYREG_SCB2_EZ_DATA0 0x400a0400u
#define CYREG_SCB2_EZ_DATA1 0x400a0404u
#define CYREG_SCB2_EZ_DATA2 0x400a0408u
#define CYREG_SCB2_EZ_DATA3 0x400a040cu
#define CYREG_SCB2_EZ_DATA4 0x400a0410u
#define CYREG_SCB2_EZ_DATA5 0x400a0414u
#define CYREG_SCB2_EZ_DATA6 0x400a0418u
#define CYREG_SCB2_EZ_DATA7 0x400a041cu
#define CYREG_SCB2_EZ_DATA8 0x400a0420u
#define CYREG_SCB2_EZ_DATA9 0x400a0424u
#define CYREG_SCB2_EZ_DATA10 0x400a0428u
#define CYREG_SCB2_EZ_DATA11 0x400a042cu
#define CYREG_SCB2_EZ_DATA12 0x400a0430u
#define CYREG_SCB2_EZ_DATA13 0x400a0434u
#define CYREG_SCB2_EZ_DATA14 0x400a0438u
#define CYREG_SCB2_EZ_DATA15 0x400a043cu
#define CYREG_SCB2_EZ_DATA16 0x400a0440u
#define CYREG_SCB2_EZ_DATA17 0x400a0444u
#define CYREG_SCB2_EZ_DATA18 0x400a0448u
#define CYREG_SCB2_EZ_DATA19 0x400a044cu
#define CYREG_SCB2_EZ_DATA20 0x400a0450u
#define CYREG_SCB2_EZ_DATA21 0x400a0454u
#define CYREG_SCB2_EZ_DATA22 0x400a0458u
#define CYREG_SCB2_EZ_DATA23 0x400a045cu
#define CYREG_SCB2_EZ_DATA24 0x400a0460u
#define CYREG_SCB2_EZ_DATA25 0x400a0464u
#define CYREG_SCB2_EZ_DATA26 0x400a0468u
#define CYREG_SCB2_EZ_DATA27 0x400a046cu
#define CYREG_SCB2_EZ_DATA28 0x400a0470u
#define CYREG_SCB2_EZ_DATA29 0x400a0474u
#define CYREG_SCB2_EZ_DATA30 0x400a0478u
#define CYREG_SCB2_EZ_DATA31 0x400a047cu
#define CYREG_SCB2_INTR_CAUSE 0x400a0e00u
#define CYREG_SCB2_INTR_I2C_EC 0x400a0e80u
#define CYREG_SCB2_INTR_I2C_EC_MASK 0x400a0e88u
#define CYREG_SCB2_INTR_I2C_EC_MASKED 0x400a0e8cu
#define CYREG_SCB2_INTR_SPI_EC 0x400a0ec0u
#define CYREG_SCB2_INTR_SPI_EC_MASK 0x400a0ec8u
#define CYREG_SCB2_INTR_SPI_EC_MASKED 0x400a0eccu
#define CYREG_SCB2_INTR_M 0x400a0f00u
#define CYREG_SCB2_INTR_M_SET 0x400a0f04u
#define CYREG_SCB2_INTR_M_MASK 0x400a0f08u
#define CYREG_SCB2_INTR_M_MASKED 0x400a0f0cu
#define CYREG_SCB2_INTR_S 0x400a0f40u
#define CYREG_SCB2_INTR_S_SET 0x400a0f44u
#define CYREG_SCB2_INTR_S_MASK 0x400a0f48u
#define CYREG_SCB2_INTR_S_MASKED 0x400a0f4cu
#define CYREG_SCB2_INTR_TX 0x400a0f80u
#define CYREG_SCB2_INTR_TX_SET 0x400a0f84u
#define CYREG_SCB2_INTR_TX_MASK 0x400a0f88u
#define CYREG_SCB2_INTR_TX_MASKED 0x400a0f8cu
#define CYREG_SCB2_INTR_RX 0x400a0fc0u
#define CYREG_SCB2_INTR_RX_SET 0x400a0fc4u
#define CYREG_SCB2_INTR_RX_MASK 0x400a0fc8u
#define CYREG_SCB2_INTR_RX_MASKED 0x400a0fccu
#define CYDEV_LCD_BASE 0x400b0000u
#define CYDEV_LCD_SIZE 0x00010000u
#define CYREG_LCD_ID 0x400b0000u
#define CYFLD_LCD_ID__OFFSET 0x00000000u
#define CYFLD_LCD_ID__SIZE 0x00000010u
#define CYFLD_LCD_REVISION__OFFSET 0x00000010u
#define CYFLD_LCD_REVISION__SIZE 0x00000010u
#define CYREG_LCD_DIVIDER 0x400b0004u
#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u
#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u
#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u
#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u
#define CYREG_LCD_CONTROL 0x400b0008u
#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u
#define CYFLD_LCD_LS_EN__SIZE 0x00000001u
#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u
#define CYFLD_LCD_HS_EN__SIZE 0x00000001u
#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u
#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u
#define CYVAL_LCD_LCD_MODE_LS 0x00000000u
#define CYVAL_LCD_LCD_MODE_HS 0x00000001u
#define CYFLD_LCD_TYPE__OFFSET 0x00000003u
#define CYFLD_LCD_TYPE__SIZE 0x00000001u
#define CYVAL_LCD_TYPE_TYPE_A 0x00000000u
#define CYVAL_LCD_TYPE_TYPE_B 0x00000001u
#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u
#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u
#define CYVAL_LCD_OP_MODE_PWM 0x00000000u
#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u
#define CYFLD_LCD_BIAS__OFFSET 0x00000005u
#define CYFLD_LCD_BIAS__SIZE 0x00000002u
#define CYVAL_LCD_BIAS_HALF 0x00000000u
#define CYVAL_LCD_BIAS_THIRD 0x00000001u
#define CYVAL_LCD_BIAS_FOURTH 0x00000002u
#define CYVAL_LCD_BIAS_FIFTH 0x00000003u
#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u
#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u
#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu
#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u
#define CYREG_LCD_DATA00 0x400b0100u
#define CYFLD_LCD_DATA__OFFSET 0x00000000u
#define CYFLD_LCD_DATA__SIZE 0x00000020u
#define CYREG_LCD_DATA01 0x400b0104u
#define CYREG_LCD_DATA02 0x400b0108u
#define CYREG_LCD_DATA03 0x400b010cu
#define CYREG_LCD_DATA04 0x400b0110u
#define CYREG_LCD_DATA10 0x400b0200u
#define CYREG_LCD_DATA11 0x400b0204u
#define CYREG_LCD_DATA12 0x400b0208u
#define CYREG_LCD_DATA13 0x400b020cu
#define CYREG_LCD_DATA14 0x400b0210u
#define CYDEV_CSD_BASE 0x400c0000u
#define CYDEV_CSD_SIZE 0x00001000u
#define CYREG_CSD_CONFIG 0x400c0000u
#define CYFLD_CSD_FILTER_DELAY__OFFSET 0x00000004u
#define CYFLD_CSD_FILTER_DELAY__SIZE 0x00000003u
#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000008u
#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u
#define CYVAL_CSD_SHIELD_DELAY_OFF 0x00000000u
#define CYVAL_CSD_SHIELD_DELAY_D5NS 0x00000001u
#define CYVAL_CSD_SHIELD_DELAY_D10NS 0x00000002u
#define CYVAL_CSD_SHIELD_DELAY_D20NS 0x00000003u
#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu
#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_CHARGE_MODE__OFFSET 0x0000000eu
#define CYFLD_CSD_CHARGE_MODE__SIZE 0x00000001u
#define CYVAL_CSD_CHARGE_MODE_CHARGE_OFF 0x00000000u
#define CYVAL_CSD_CHARGE_MODE_CHARGE_IO 0x00000001u
#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u
#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u
#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u
#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u
#define CYFLD_CSD_CSX_DUAL_CNT__OFFSET 0x00000013u
#define CYFLD_CSD_CSX_DUAL_CNT__SIZE 0x00000001u
#define CYVAL_CSD_CSX_DUAL_CNT_ONE 0x00000000u
#define CYVAL_CSD_CSX_DUAL_CNT_TWO 0x00000001u
#define CYFLD_CSD_DSI_COUNT_SEL__OFFSET 0x00000018u
#define CYFLD_CSD_DSI_COUNT_SEL__SIZE 0x00000001u
#define CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT 0x00000000u
#define CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT 0x00000001u
#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000019u
#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u
#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x0000001au
#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u
#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x0000001bu
#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_LP_MODE__OFFSET 0x0000001eu
#define CYFLD_CSD_LP_MODE__SIZE 0x00000001u
#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu
#define CYFLD_CSD_ENABLE__SIZE 0x00000001u
#define CYREG_CSD_SPARE 0x400c0004u
#define CYFLD_CSD_SPARE__OFFSET 0x00000000u
#define CYFLD_CSD_SPARE__SIZE 0x00000004u
#define CYREG_CSD_STATUS 0x400c0080u
#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u
#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u
#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u
#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u
#define CYFLD_CSD_HSCMP_OUT__OFFSET 0x00000002u
#define CYFLD_CSD_HSCMP_OUT__SIZE 0x00000001u
#define CYVAL_CSD_HSCMP_OUT_C_LT_VREF 0x00000000u
#define CYVAL_CSD_HSCMP_OUT_C_GT_VREF 0x00000001u
#define CYFLD_CSD_CSDCMP_OUT__OFFSET 0x00000003u
#define CYFLD_CSD_CSDCMP_OUT__SIZE 0x00000001u
#define CYREG_CSD_STAT_SEQ 0x400c0084u
#define CYFLD_CSD_SEQ_STATE__OFFSET 0x00000000u
#define CYFLD_CSD_SEQ_STATE__SIZE 0x00000003u
#define CYFLD_CSD_ADC_STATE__OFFSET 0x00000010u
#define CYFLD_CSD_ADC_STATE__SIZE 0x00000003u
#define CYREG_CSD_STAT_CNTS 0x400c0088u
#define CYFLD_CSD_NUM_CONV__OFFSET 0x00000000u
#define CYFLD_CSD_NUM_CONV__SIZE 0x00000010u
#define CYREG_CSD_RESULT_VAL1 0x400c00d0u
#define CYFLD_CSD_VALUE__OFFSET 0x00000000u
#define CYFLD_CSD_VALUE__SIZE 0x00000010u
#define CYFLD_CSD_BAD_CONVS__OFFSET 0x00000010u
#define CYFLD_CSD_BAD_CONVS__SIZE 0x00000008u
#define CYREG_CSD_RESULT_VAL2 0x400c00d4u
#define CYREG_CSD_ADC_RES 0x400c00e0u
#define CYFLD_CSD_VIN_CNT__OFFSET 0x00000000u
#define CYFLD_CSD_VIN_CNT__SIZE 0x00000010u
#define CYFLD_CSD_HSCMP_POL__OFFSET 0x00000010u
#define CYFLD_CSD_HSCMP_POL__SIZE 0x00000001u
#define CYFLD_CSD_ADC_OVERFLOW__OFFSET 0x0000001eu
#define CYFLD_CSD_ADC_OVERFLOW__SIZE 0x00000001u
#define CYFLD_CSD_ADC_ABORT__OFFSET 0x0000001fu
#define CYFLD_CSD_ADC_ABORT__SIZE 0x00000001u
#define CYREG_CSD_INTR 0x400c00f0u
#define CYFLD_CSD_SAMPLE__OFFSET 0x00000001u
#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u
#define CYFLD_CSD_INIT__OFFSET 0x00000002u
#define CYFLD_CSD_INIT__SIZE 0x00000001u
#define CYFLD_CSD_ADC_RES__OFFSET 0x00000008u
#define CYFLD_CSD_ADC_RES__SIZE 0x00000001u
#define CYREG_CSD_INTR_SET 0x400c00f4u
#define CYREG_CSD_INTR_MASK 0x400c00f8u
#define CYREG_CSD_INTR_MASKED 0x400c00fcu
#define CYREG_CSD_HSCMP 0x400c0180u
#define CYFLD_CSD_HSCMP_EN__OFFSET 0x00000000u
#define CYFLD_CSD_HSCMP_EN__SIZE 0x00000001u
#define CYVAL_CSD_HSCMP_EN_OFF 0x00000000u
#define CYVAL_CSD_HSCMP_EN_ON 0x00000001u
#define CYFLD_CSD_HSCMP_INVERT__OFFSET 0x00000004u
#define CYFLD_CSD_HSCMP_INVERT__SIZE 0x00000001u
#define CYFLD_CSD_AZ_EN__OFFSET 0x0000001fu
#define CYFLD_CSD_AZ_EN__SIZE 0x00000001u
#define CYREG_CSD_AMBUF 0x400c0184u
#define CYFLD_CSD_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CSD_PWR_MODE__SIZE 0x00000002u
#define CYVAL_CSD_PWR_MODE_OFF 0x00000000u
#define CYVAL_CSD_PWR_MODE_NORM 0x00000001u
#define CYVAL_CSD_PWR_MODE_HI 0x00000002u
#define CYREG_CSD_REFGEN 0x400c0188u
#define CYFLD_CSD_REFGEN_EN__OFFSET 0x00000000u
#define CYFLD_CSD_REFGEN_EN__SIZE 0x00000001u
#define CYVAL_CSD_REFGEN_EN_OFF 0x00000000u
#define CYVAL_CSD_REFGEN_EN_ON 0x00000001u
#define CYFLD_CSD_BYPASS__OFFSET 0x00000004u
#define CYFLD_CSD_BYPASS__SIZE 0x00000001u
#define CYFLD_CSD_VDDA_EN__OFFSET 0x00000005u
#define CYFLD_CSD_VDDA_EN__SIZE 0x00000001u
#define CYFLD_CSD_RES_EN__OFFSET 0x00000006u
#define CYFLD_CSD_RES_EN__SIZE 0x00000001u
#define CYFLD_CSD_GAIN__OFFSET 0x00000008u
#define CYFLD_CSD_GAIN__SIZE 0x00000005u
#define CYFLD_CSD_VREFLO_SEL__OFFSET 0x00000010u
#define CYFLD_CSD_VREFLO_SEL__SIZE 0x00000005u
#define CYFLD_CSD_VREFLO_INT__OFFSET 0x00000017u
#define CYFLD_CSD_VREFLO_INT__SIZE 0x00000001u
#define CYREG_CSD_CSDCMP 0x400c018cu
#define CYFLD_CSD_CSDCMP_EN__OFFSET 0x00000000u
#define CYFLD_CSD_CSDCMP_EN__SIZE 0x00000001u
#define CYVAL_CSD_CSDCMP_EN_OFF 0x00000000u
#define CYVAL_CSD_CSDCMP_EN_ON 0x00000001u
#define CYFLD_CSD_POLARITY_SEL__OFFSET 0x00000004u
#define CYFLD_CSD_POLARITY_SEL__SIZE 0x00000002u
#define CYVAL_CSD_POLARITY_SEL_IDACA_POL 0x00000000u
#define CYVAL_CSD_POLARITY_SEL_IDACB_POL 0x00000001u
#define CYVAL_CSD_POLARITY_SEL_DUAL_POL 0x00000002u
#define CYFLD_CSD_CMP_PHASE__OFFSET 0x00000008u
#define CYFLD_CSD_CMP_PHASE__SIZE 0x00000002u
#define CYVAL_CSD_CMP_PHASE_FULL 0x00000000u
#define CYVAL_CSD_CMP_PHASE_PHI1 0x00000001u
#define CYVAL_CSD_CMP_PHASE_PHI2 0x00000002u
#define CYVAL_CSD_CMP_PHASE_PHI1_2 0x00000003u
#define CYFLD_CSD_CMP_MODE__OFFSET 0x0000001cu
#define CYFLD_CSD_CMP_MODE__SIZE 0x00000001u
#define CYVAL_CSD_CMP_MODE_CSD 0x00000000u
#define CYVAL_CSD_CMP_MODE_GP 0x00000001u
#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001du
#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u
#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u
#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u
#define CYREG_CSD_IDACA 0x400c01c0u
#define CYFLD_CSD_VAL__OFFSET 0x00000000u
#define CYFLD_CSD_VAL__SIZE 0x00000007u
#define CYFLD_CSD_POL_DYN__OFFSET 0x00000007u
#define CYFLD_CSD_POL_DYN__SIZE 0x00000001u
#define CYVAL_CSD_POL_DYN_STATIC 0x00000000u
#define CYVAL_CSD_POL_DYN_DYNAMIC 0x00000001u
#define CYFLD_CSD_POLARITY__OFFSET 0x00000008u
#define CYFLD_CSD_POLARITY__SIZE 0x00000002u
#define CYVAL_CSD_POLARITY_VSSA_SRC 0x00000000u
#define CYVAL_CSD_POLARITY_VDDA_SNK 0x00000001u
#define CYVAL_CSD_POLARITY_SENSE 0x00000002u
#define CYVAL_CSD_POLARITY_SENSE_INV 0x00000003u
#define CYFLD_CSD_BAL_MODE__OFFSET 0x0000000au
#define CYFLD_CSD_BAL_MODE__SIZE 0x00000002u
#define CYVAL_CSD_BAL_MODE_FULL 0x00000000u
#define CYVAL_CSD_BAL_MODE_PHI1 0x00000001u
#define CYVAL_CSD_BAL_MODE_PHI2 0x00000002u
#define CYVAL_CSD_BAL_MODE_PHI1_2 0x00000003u
#define CYFLD_CSD_LEG1_MODE__OFFSET 0x00000010u
#define CYFLD_CSD_LEG1_MODE__SIZE 0x00000002u
#define CYVAL_CSD_LEG1_MODE_GP_STATIC 0x00000000u
#define CYVAL_CSD_LEG1_MODE_GP 0x00000001u
#define CYVAL_CSD_LEG1_MODE_CSD_STATIC 0x00000002u
#define CYVAL_CSD_LEG1_MODE_CSD 0x00000003u
#define CYFLD_CSD_LEG2_MODE__OFFSET 0x00000012u
#define CYFLD_CSD_LEG2_MODE__SIZE 0x00000002u
#define CYVAL_CSD_LEG2_MODE_GP_STATIC 0x00000000u
#define CYVAL_CSD_LEG2_MODE_GP 0x00000001u
#define CYVAL_CSD_LEG2_MODE_CSD_STATIC 0x00000002u
#define CYVAL_CSD_LEG2_MODE_CSD 0x00000003u
#define CYFLD_CSD_DSI_CTRL_EN__OFFSET 0x00000015u
#define CYFLD_CSD_DSI_CTRL_EN__SIZE 0x00000001u
#define CYFLD_CSD_RANGE__OFFSET 0x00000016u
#define CYFLD_CSD_RANGE__SIZE 0x00000002u
#define CYVAL_CSD_RANGE_IDAC_LO 0x00000000u
#define CYVAL_CSD_RANGE_IDAC_MED 0x00000001u
#define CYVAL_CSD_RANGE_IDAC_HI 0x00000002u
#define CYFLD_CSD_LEG1_EN__OFFSET 0x00000018u
#define CYFLD_CSD_LEG1_EN__SIZE 0x00000001u
#define CYFLD_CSD_LEG2_EN__OFFSET 0x00000019u
#define CYFLD_CSD_LEG2_EN__SIZE 0x00000001u
#define CYREG_CSD_IDACB 0x400c01c4u
#define CYFLD_CSD_LEG3_EN__OFFSET 0x0000001au
#define CYFLD_CSD_LEG3_EN__SIZE 0x00000001u
#define CYREG_CSD_SW_RES 0x400c01f0u
#define CYFLD_CSD_RES_HCAV__OFFSET 0x00000000u
#define CYFLD_CSD_RES_HCAV__SIZE 0x00000002u
#define CYVAL_CSD_RES_HCAV_LOW 0x00000000u
#define CYVAL_CSD_RES_HCAV_MED 0x00000001u
#define CYVAL_CSD_RES_HCAV_HIGH 0x00000002u
#define CYVAL_CSD_RES_HCAV_LOWEMI 0x00000003u
#define CYFLD_CSD_RES_HCAG__OFFSET 0x00000002u
#define CYFLD_CSD_RES_HCAG__SIZE 0x00000002u
#define CYFLD_CSD_RES_HCBV__OFFSET 0x00000004u
#define CYFLD_CSD_RES_HCBV__SIZE 0x00000002u
#define CYFLD_CSD_RES_HCBG__OFFSET 0x00000006u
#define CYFLD_CSD_RES_HCBG__SIZE 0x00000002u
#define CYFLD_CSD_RES_F1PM__OFFSET 0x00000010u
#define CYFLD_CSD_RES_F1PM__SIZE 0x00000002u
#define CYVAL_CSD_RES_F1PM_LOW 0x00000000u
#define CYVAL_CSD_RES_F1PM_MED 0x00000001u
#define CYVAL_CSD_RES_F1PM_HIGH 0x00000002u
#define CYVAL_CSD_RES_F1PM_RESERVED 0x00000003u
#define CYFLD_CSD_RES_F2PT__OFFSET 0x00000012u
#define CYFLD_CSD_RES_F2PT__SIZE 0x00000002u
#define CYREG_CSD_SENSE_PERIOD 0x400c0200u
#define CYFLD_CSD_SENSE_DIV__OFFSET 0x00000000u
#define CYFLD_CSD_SENSE_DIV__SIZE 0x0000000cu
#define CYFLD_CSD_LFSR_SIZE__OFFSET 0x00000010u
#define CYFLD_CSD_LFSR_SIZE__SIZE 0x00000003u
#define CYVAL_CSD_LFSR_SIZE_OFF 0x00000000u
#define CYVAL_CSD_LFSR_SIZE_6B 0x00000001u
#define CYVAL_CSD_LFSR_SIZE_7B 0x00000002u
#define CYVAL_CSD_LFSR_SIZE_9B 0x00000003u
#define CYVAL_CSD_LFSR_SIZE_10B 0x00000004u
#define CYVAL_CSD_LFSR_SIZE_8B 0x00000005u
#define CYVAL_CSD_LFSR_SIZE_12B 0x00000006u
#define CYFLD_CSD_LFSR_SCALE__OFFSET 0x00000014u
#define CYFLD_CSD_LFSR_SCALE__SIZE 0x00000004u
#define CYFLD_CSD_LFSR_CLEAR__OFFSET 0x00000018u
#define CYFLD_CSD_LFSR_CLEAR__SIZE 0x00000001u
#define CYFLD_CSD_SEL_LFSR_MSB__OFFSET 0x00000019u
#define CYFLD_CSD_SEL_LFSR_MSB__SIZE 0x00000001u
#define CYREG_CSD_SENSE_DUTY 0x400c0204u
#define CYFLD_CSD_SENSE_WIDTH__OFFSET 0x00000000u
#define CYFLD_CSD_SENSE_WIDTH__SIZE 0x0000000cu
#define CYFLD_CSD_SENSE_POL__OFFSET 0x00000010u
#define CYFLD_CSD_SENSE_POL__SIZE 0x00000001u
#define CYFLD_CSD_OVERLAP_PHI1__OFFSET 0x00000012u
#define CYFLD_CSD_OVERLAP_PHI1__SIZE 0x00000001u
#define CYFLD_CSD_OVERLAP_PHI2__OFFSET 0x00000013u
#define CYFLD_CSD_OVERLAP_PHI2__SIZE 0x00000001u
#define CYREG_CSD_SW_HS_P_SEL 0x400c0280u
#define CYFLD_CSD_SW_HMPM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_HMPM__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMPT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_HMPT__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMPS__OFFSET 0x00000008u
#define CYFLD_CSD_SW_HMPS__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMMA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_HMMA__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HMMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMCA__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HMCA__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMCB__OFFSET 0x00000018u
#define CYFLD_CSD_SW_HMCB__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMRH__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_HMRH__SIZE 0x00000001u
#define CYREG_CSD_SW_HS_N_SEL 0x400c0284u
#define CYFLD_CSD_SW_HCCC__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HCCC__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCCD__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HCCD__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_HCRH__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_HCRL__SIZE 0x00000003u
#define CYREG_CSD_SW_SHIELD_SEL 0x400c0288u
#define CYFLD_CSD_SW_HCAV__OFFSET 0x00000000u
#define CYFLD_CSD_SW_HCAV__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCAG__OFFSET 0x00000004u
#define CYFLD_CSD_SW_HCAG__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCBV__OFFSET 0x00000008u
#define CYFLD_CSD_SW_HCBV__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCBG__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_HCBG__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCCV__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HCCV__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCCG__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HCCG__SIZE 0x00000001u
#define CYREG_CSD_SW_AMUXBUF_SEL 0x400c0290u
#define CYFLD_CSD_SW_IRBY__OFFSET 0x00000004u
#define CYFLD_CSD_SW_IRBY__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRLB__OFFSET 0x00000008u
#define CYFLD_CSD_SW_IRLB__SIZE 0x00000001u
#define CYFLD_CSD_SW_ICA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_ICA__SIZE 0x00000001u
#define CYFLD_CSD_SW_ICB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_ICB__SIZE 0x00000003u
#define CYFLD_CSD_SW_IRLI__OFFSET 0x00000014u
#define CYFLD_CSD_SW_IRLI__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_IRH__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_IRL__SIZE 0x00000001u
#define CYREG_CSD_SW_BYP_SEL 0x400c0294u
#define CYFLD_CSD_SW_BYA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_BYA__SIZE 0x00000001u
#define CYFLD_CSD_SW_BYB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_BYB__SIZE 0x00000001u
#define CYFLD_CSD_SW_CBCC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_CBCC__SIZE 0x00000001u
#define CYREG_CSD_SW_CMP_P_SEL 0x400c02a0u
#define CYFLD_CSD_SW_SFPM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_SFPM__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFPT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_SFPT__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFPS__OFFSET 0x00000008u
#define CYFLD_CSD_SW_SFPS__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFMA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_SFMA__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_SFMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFCA__OFFSET 0x00000014u
#define CYFLD_CSD_SW_SFCA__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFCB__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SFCB__SIZE 0x00000001u
#define CYREG_CSD_SW_CMP_N_SEL 0x400c02a4u
#define CYFLD_CSD_SW_SCRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SCRH__SIZE 0x00000003u
#define CYFLD_CSD_SW_SCRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_SCRL__SIZE 0x00000003u
#define CYREG_CSD_SW_REFGEN_SEL 0x400c02a8u
#define CYFLD_CSD_SW_IAIB__OFFSET 0x00000000u
#define CYFLD_CSD_SW_IAIB__SIZE 0x00000001u
#define CYFLD_CSD_SW_IBCB__OFFSET 0x00000004u
#define CYFLD_CSD_SW_IBCB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_SGMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGRE__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SGRE__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGR__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_SGR__SIZE 0x00000001u
#define CYREG_CSD_SW_FW_MOD_SEL 0x400c02b0u
#define CYFLD_CSD_SW_F1PM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_F1PM__SIZE 0x00000001u
#define CYFLD_CSD_SW_F1MA__OFFSET 0x00000008u
#define CYFLD_CSD_SW_F1MA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F1CA__OFFSET 0x00000010u
#define CYFLD_CSD_SW_F1CA__SIZE 0x00000003u
#define CYFLD_CSD_SW_C1CC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_C1CC__SIZE 0x00000001u
#define CYFLD_CSD_SW_C1CD__OFFSET 0x00000018u
#define CYFLD_CSD_SW_C1CD__SIZE 0x00000001u
#define CYFLD_CSD_SW_C1F1__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_C1F1__SIZE 0x00000001u
#define CYREG_CSD_SW_FW_TANK_SEL 0x400c02b4u
#define CYFLD_CSD_SW_F2PT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_F2PT__SIZE 0x00000001u
#define CYFLD_CSD_SW_F2MA__OFFSET 0x00000008u
#define CYFLD_CSD_SW_F2MA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F2CA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_F2CA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F2CB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_F2CB__SIZE 0x00000003u
#define CYFLD_CSD_SW_C2CC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_C2CC__SIZE 0x00000001u
#define CYFLD_CSD_SW_C2CD__OFFSET 0x00000018u
#define CYFLD_CSD_SW_C2CD__SIZE 0x00000001u
#define CYFLD_CSD_SW_C2F2__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_C2F2__SIZE 0x00000001u
#define CYREG_CSD_SW_DSI_SEL 0x400c02c0u
#define CYFLD_CSD_DSI_CSH_TANK__OFFSET 0x00000000u
#define CYFLD_CSD_DSI_CSH_TANK__SIZE 0x00000003u
#define CYFLD_CSD_DSI_CMOD__OFFSET 0x00000004u
#define CYFLD_CSD_DSI_CMOD__SIZE 0x00000003u
#define CYREG_CSD_SEQ_TIME 0x400c0300u
#define CYFLD_CSD_AZ_TIME__OFFSET 0x00000000u
#define CYFLD_CSD_AZ_TIME__SIZE 0x00000008u
#define CYREG_CSD_SEQ_INIT_CNT 0x400c0310u
#define CYFLD_CSD_CONV_CNT__OFFSET 0x00000000u
#define CYFLD_CSD_CONV_CNT__SIZE 0x00000010u
#define CYREG_CSD_SEQ_NORM_CNT 0x400c0314u
#define CYREG_CSD_ADC_CTL 0x400c0320u
#define CYFLD_CSD_ADC_TIME__OFFSET 0x00000000u
#define CYFLD_CSD_ADC_TIME__SIZE 0x00000008u
#define CYFLD_CSD_ADC_MODE__OFFSET 0x00000010u
#define CYFLD_CSD_ADC_MODE__SIZE 0x00000002u
#define CYVAL_CSD_ADC_MODE_OFF 0x00000000u
#define CYVAL_CSD_ADC_MODE_VREF_CNT 0x00000001u
#define CYVAL_CSD_ADC_MODE_VREF_BY2_CNT 0x00000002u
#define CYVAL_CSD_ADC_MODE_VIN_CNT 0x00000003u
#define CYREG_CSD_SEQ_START 0x400c0340u
#define CYFLD_CSD_START__OFFSET 0x00000000u
#define CYFLD_CSD_START__SIZE 0x00000001u
#define CYFLD_CSD_SEQ_MODE__OFFSET 0x00000001u
#define CYFLD_CSD_SEQ_MODE__SIZE 0x00000001u
#define CYFLD_CSD_ABORT__OFFSET 0x00000003u
#define CYFLD_CSD_ABORT__SIZE 0x00000001u
#define CYFLD_CSD_DSI_START_EN__OFFSET 0x00000004u
#define CYFLD_CSD_DSI_START_EN__SIZE 0x00000001u
#define CYFLD_CSD_AZ0_SKIP__OFFSET 0x00000008u
#define CYFLD_CSD_AZ0_SKIP__SIZE 0x00000001u
#define CYFLD_CSD_AZ1_SKIP__OFFSET 0x00000009u
#define CYFLD_CSD_AZ1_SKIP__SIZE 0x00000001u
#define CYREG_CSD_TRIM_CTRL 0x400c0f00u
#define CYFLD_CSD_DELAY_TRIM__OFFSET 0x00000000u
#define CYFLD_CSD_DELAY_TRIM__SIZE 0x00000002u
#define CYFLD_CSD_DELAY_HYS__OFFSET 0x00000004u
#define CYFLD_CSD_DELAY_HYS__SIZE 0x00000002u
#define CYDEV_LPCOMP_BASE 0x400d0000u
#define CYDEV_LPCOMP_SIZE 0x00010000u
#define CYREG_LPCOMP_ID 0x400d0000u
#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u
#define CYFLD_LPCOMP_ID__SIZE 0x00000010u
#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u
#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u
#define CYREG_LPCOMP_CONFIG 0x400d0004u
#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u
#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u
#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u
#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u
#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u
#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u
#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u
#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au
#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu
#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu
#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu
#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu
#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_BYPASS1__OFFSET 0x00000010u
#define CYFLD_LPCOMP_DSI_BYPASS1__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_LEVEL1__OFFSET 0x00000011u
#define CYFLD_LPCOMP_DSI_LEVEL1__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_BYPASS2__OFFSET 0x00000014u
#define CYFLD_LPCOMP_DSI_BYPASS2__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_LEVEL2__OFFSET 0x00000015u
#define CYFLD_LPCOMP_DSI_LEVEL2__SIZE 0x00000001u
#define CYREG_LPCOMP_DFT 0x400d0008u
#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u
#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u
#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u
#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR 0x400d0010u
#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR_SET 0x400d0014u
#define CYREG_LPCOMP_INTR_MASK 0x400d0018u
#define CYFLD_LPCOMP_COMP1_MASK__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_MASK__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASK__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASK__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR_MASKED 0x400d001cu
#define CYFLD_LPCOMP_COMP1_MASKED__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_MASKED__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASKED__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASKED__SIZE 0x00000001u
#define CYREG_LPCOMP_TRIM1 0x400dff00u
#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM2 0x400dff04u
#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM3 0x400dff08u
#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM4 0x400dff0cu
#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u
#define CYDEV_CPUSS_BASE 0x40100000u
#define CYDEV_CPUSS_SIZE 0x00001000u
#define CYREG_CPUSS_SYSREQ 0x40100004u
#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010u
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001bu
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001u
#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu
#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u
#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du
#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001eu
#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001u
#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001fu
#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001u
#define CYREG_CPUSS_SYSARG 0x40100008u
#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020u
#define CYREG_CPUSS_PROTECTION 0x4010000cu
#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000u
#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004u
#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001eu
#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001u
#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001fu
#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001u
#define CYREG_CPUSS_PRIV_ROM 0x40100010u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008u
#define CYREG_CPUSS_PRIV_RAM 0x40100014u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009u
#define CYREG_CPUSS_PRIV_FLASH 0x40100018u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000cu
#define CYREG_CPUSS_WOUNDING 0x4010001cu
#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u
#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u
#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u
#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u
#define CYREG_CPUSS_FLASH_CTL 0x40100030u
#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002u
#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004u
#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008u
#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001u
#define CYREG_CPUSS_ROM_CTL 0x40100034u
#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001u
#define CYDEV_SPCIF_BASE 0x40110000u
#define CYDEV_SPCIF_SIZE 0x00010000u
#define CYREG_SPCIF_GEOMETRY 0x40110000u
#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u
#define CYFLD_SPCIF_FLASH__SIZE 0x0000000eu
#define CYFLD_SPCIF_SFLASH__OFFSET 0x0000000eu
#define CYFLD_SPCIF_SFLASH__SIZE 0x00000006u
#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u
#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u
#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u
#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u
#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu
#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u
#define CYREG_SPCIF_INTR 0x401107f0u
#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000u
#define CYFLD_SPCIF_TIMER__SIZE 0x00000001u
#define CYREG_SPCIF_INTR_SET 0x401107f4u
#define CYREG_SPCIF_INTR_MASK 0x401107f8u
#define CYREG_SPCIF_INTR_MASKED 0x401107fcu
#define CYDEV_CTBM0_BASE 0x40300000u
#define CYDEV_CTBM0_SIZE 0x00010000u
#define CYREG_CTBM0_CTB_CTRL 0x40300000u
#define CYFLD_CTBM_DEEPSLEEP_ON__OFFSET 0x0000001eu
#define CYFLD_CTBM_DEEPSLEEP_ON__SIZE 0x00000001u
#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu
#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u
#define CYREG_CTBM0_OA_RES0_CTRL 0x40300004u
#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u
#define CYVAL_CTBM_OA0_PWR_MODE_OFF 0x00000000u
#define CYVAL_CTBM_OA0_PWR_MODE_LOW 0x00000001u
#define CYVAL_CTBM_OA0_PWR_MODE_MEDIUM 0x00000002u
#define CYVAL_CTBM_OA0_PWR_MODE_HIGH 0x00000003u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET 0x00000007u
#define CYFLD_CTBM_OA0_DSI_LEVEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM0_OA_RES1_CTRL 0x40300008u
#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET 0x00000007u
#define CYFLD_CTBM_OA1_DSI_LEVEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM0_COMP_STAT 0x4030000cu
#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u
#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u
#define CYREG_CTBM0_INTR 0x40300020u
#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_SET 0x40300024u
#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_MASK 0x40300028u
#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_MASKED 0x4030002cu
#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u
#define CYREG_CTBM0_DFT_CTRL 0x40300030u
#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u
#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu
#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_SW 0x40300080u
#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u
#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u
#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u
#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_SW_CLEAR 0x40300084u
#define CYREG_CTBM0_OA1_SW 0x40300088u
#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u
#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u
#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u
#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u
#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u
#define CYREG_CTBM0_OA1_SW_CLEAR 0x4030008cu
#define CYREG_CTBM0_CTB_SW_HW_CTRL 0x403000c0u
#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u
#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u
#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u
#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u
#define CYREG_CTBM0_CTB_SW_STATUS 0x403000c4u
#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu
#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du
#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu
#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_OFFSET_TRIM 0x40300f00u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM 0x40300f04u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA0_COMP_TRIM 0x40300f08u
#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u
#define CYREG_CTBM0_OA1_OFFSET_TRIM 0x40300f0cu
#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM 0x40300f10u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA1_COMP_TRIM 0x40300f14u
#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u
#define CYDEV_SAR_BASE 0x403a0000u
#define CYDEV_SAR_SIZE 0x00010000u
#define CYREG_SAR_CTRL 0x403a0000u
#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u
#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u
#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u
#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u
#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u
#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u
#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u
#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u
#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u
#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u
#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u
#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u
#define CYVAL_SAR_NEG_SEL_P1 0x00000002u
#define CYVAL_SAR_NEG_SEL_P3 0x00000003u
#define CYVAL_SAR_NEG_SEL_P5 0x00000004u
#define CYVAL_SAR_NEG_SEL_P7 0x00000005u
#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u
#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u
#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu
#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u
#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_SPARE__OFFSET 0x00000010u
#define CYFLD_SAR_SPARE__SIZE 0x00000004u
#define CYFLD_SAR_BOOSTPUMP_EN__OFFSET 0x00000014u
#define CYFLD_SAR_BOOSTPUMP_EN__SIZE 0x00000001u
#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u
#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u
#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u
#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u
#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_DEEPSLEEP_ON__OFFSET 0x0000001bu
#define CYFLD_SAR_DEEPSLEEP_ON__SIZE 0x00000001u
#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu
#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u
#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du
#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u
#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu
#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u
#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SAR_ENABLED__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_CTRL 0x403a0004u
#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u
#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u
#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u
#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u
#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u
#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u
#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u
#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u
#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_TIME01 0x403a0010u
#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au
#define CYREG_SAR_SAMPLE_TIME23 0x403a0014u
#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au
#define CYREG_SAR_RANGE_THRES 0x403a0018u
#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u
#define CYREG_SAR_RANGE_COND 0x403a001cu
#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u
#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u
#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u
#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u
#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u
#define CYREG_SAR_CHAN_EN 0x403a0020u
#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u
#define CYREG_SAR_START_CTRL 0x403a0024u
#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u
#define CYREG_SAR_DFT_CTRL 0x403a0030u
#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u
#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u
#define CYFLD_SAR_HIZ__OFFSET 0x00000001u
#define CYFLD_SAR_HIZ__SIZE 0x00000001u
#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u
#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u
#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u
#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u
#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u
#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u
#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu
#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u
#define CYFLD_SAR_DCEN__OFFSET 0x0000001du
#define CYFLD_SAR_DCEN__SIZE 0x00000001u
#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu
#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG0 0x403a0080u
#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 0x00000005u
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 0x00000006u
#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_RESOLUTION_MAXRES 0x00000000u
#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG1 0x403a0084u
#define CYREG_SAR_CHAN_CONFIG2 0x403a0088u
#define CYREG_SAR_CHAN_CONFIG3 0x403a008cu
#define CYREG_SAR_CHAN_CONFIG4 0x403a0090u
#define CYREG_SAR_CHAN_CONFIG5 0x403a0094u
#define CYREG_SAR_CHAN_CONFIG6 0x403a0098u
#define CYREG_SAR_CHAN_CONFIG7 0x403a009cu
#define CYREG_SAR_CHAN_CONFIG8 0x403a00a0u
#define CYREG_SAR_CHAN_CONFIG9 0x403a00a4u
#define CYREG_SAR_CHAN_CONFIG10 0x403a00a8u
#define CYREG_SAR_CHAN_CONFIG11 0x403a00acu
#define CYREG_SAR_CHAN_CONFIG12 0x403a00b0u
#define CYREG_SAR_CHAN_CONFIG13 0x403a00b4u
#define CYREG_SAR_CHAN_CONFIG14 0x403a00b8u
#define CYREG_SAR_CHAN_CONFIG15 0x403a00bcu
#define CYREG_SAR_CHAN_WORK0 0x403a0100u
#define CYFLD_SAR_WORK__OFFSET 0x00000000u
#define CYFLD_SAR_WORK__SIZE 0x00000010u
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_WORK1 0x403a0104u
#define CYREG_SAR_CHAN_WORK2 0x403a0108u
#define CYREG_SAR_CHAN_WORK3 0x403a010cu
#define CYREG_SAR_CHAN_WORK4 0x403a0110u
#define CYREG_SAR_CHAN_WORK5 0x403a0114u
#define CYREG_SAR_CHAN_WORK6 0x403a0118u
#define CYREG_SAR_CHAN_WORK7 0x403a011cu
#define CYREG_SAR_CHAN_WORK8 0x403a0120u
#define CYREG_SAR_CHAN_WORK9 0x403a0124u
#define CYREG_SAR_CHAN_WORK10 0x403a0128u
#define CYREG_SAR_CHAN_WORK11 0x403a012cu
#define CYREG_SAR_CHAN_WORK12 0x403a0130u
#define CYREG_SAR_CHAN_WORK13 0x403a0134u
#define CYREG_SAR_CHAN_WORK14 0x403a0138u
#define CYREG_SAR_CHAN_WORK15 0x403a013cu
#define CYREG_SAR_CHAN_RESULT0 0x403a0180u
#define CYFLD_SAR_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_RESULT1 0x403a0184u
#define CYREG_SAR_CHAN_RESULT2 0x403a0188u
#define CYREG_SAR_CHAN_RESULT3 0x403a018cu
#define CYREG_SAR_CHAN_RESULT4 0x403a0190u
#define CYREG_SAR_CHAN_RESULT5 0x403a0194u
#define CYREG_SAR_CHAN_RESULT6 0x403a0198u
#define CYREG_SAR_CHAN_RESULT7 0x403a019cu
#define CYREG_SAR_CHAN_RESULT8 0x403a01a0u
#define CYREG_SAR_CHAN_RESULT9 0x403a01a4u
#define CYREG_SAR_CHAN_RESULT10 0x403a01a8u
#define CYREG_SAR_CHAN_RESULT11 0x403a01acu
#define CYREG_SAR_CHAN_RESULT12 0x403a01b0u
#define CYREG_SAR_CHAN_RESULT13 0x403a01b4u
#define CYREG_SAR_CHAN_RESULT14 0x403a01b8u
#define CYREG_SAR_CHAN_RESULT15 0x403a01bcu
#define CYREG_SAR_CHAN_WORK_VALID 0x403a0200u
#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u
#define CYREG_SAR_CHAN_RESULT_VALID 0x403a0204u
#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u
#define CYREG_SAR_STATUS 0x403a0208u
#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u
#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu
#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u
#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu
#define CYFLD_SAR_BUSY__SIZE 0x00000001u
#define CYREG_SAR_AVG_STAT 0x403a020cu
#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u
#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u
#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u
#define CYREG_SAR_INTR 0x403a0210u
#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u
#define CYREG_SAR_INTR_SET 0x403a0214u
#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASK 0x403a0218u
#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASKED 0x403a021cu
#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u
#define CYREG_SAR_SATURATE_INTR 0x403a0220u
#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_SET 0x403a0224u
#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASK 0x403a0228u
#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASKED 0x403a022cu
#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR 0x403a0230u
#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_SET 0x403a0234u
#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASK 0x403a0238u
#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASKED 0x403a023cu
#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_INTR_CAUSE 0x403a0240u
#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu
#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu
#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u
#define CYREG_SAR_INJ_CHAN_CONFIG 0x403a0280u
#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u
#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u
#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u
#define CYREG_SAR_INJ_RESULT 0x403a0290u
#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH0 0x403a0300u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au
#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu
#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu
#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du
#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu
#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu
#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au
#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu
#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu
#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du
#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x403a0304u
#define CYREG_SAR_MUX_SWITCH1 0x403a0308u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x403a030cu
#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x403a0340u
#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_STATUS 0x403a0348u
#define CYREG_SAR_PUMP_CTRL 0x403a0380u
#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u
#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u
#define CYREG_SAR_ANA_TRIM 0x403a0f00u
#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u
#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u
#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u
#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u
#define CYREG_SAR_WOUNDING 0x403a0f04u
#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u
#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u
#define CYDEV_PASS_BASE 0x403f0000u
#define CYDEV_PASS_SIZE 0x00010000u
#define CYREG_PASS_INTR_CAUSE 0x403f0000u
#define CYFLD_PASS_CTB0_INT__OFFSET 0x00000000u
#define CYFLD_PASS_CTB0_INT__SIZE 0x00000001u
#define CYREG_PASS_DFT_CTRL 0x403f0030u
#define CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE 0x00000001u
#define CYREG_PASS_PASS_CTRL 0x403f0108u
#define CYFLD_PASS_PMPCLK_BYP__OFFSET 0x00000000u
#define CYFLD_PASS_PMPCLK_BYP__SIZE 0x00000001u
#define CYFLD_PASS_PMPCLK_SRC__OFFSET 0x00000001u
#define CYFLD_PASS_PMPCLK_SRC__SIZE 0x00000001u
#define CYFLD_PASS_RMB_BITS__OFFSET 0x00000008u
#define CYFLD_PASS_RMB_BITS__SIZE 0x00000008u
#define CYDEV_PASS_DSAB_BASE 0x403f0e00u
#define CYDEV_PASS_DSAB_SIZE 0x00000100u
#define CYREG_PASS_DSAB_DSAB_CTRL 0x403f0e00u
#define CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_CURRENT_SEL__SIZE 0x00000006u
#define CYFLD_PASS_DSAB_SEL_OUT__OFFSET 0x00000008u
#define CYFLD_PASS_DSAB_SEL_OUT__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET 0x00000010u
#define CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET 0x00000018u
#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE 0x00000001u
#define CYFLD_PASS_DSAB_STARTUP_RM__OFFSET 0x0000001cu
#define CYFLD_PASS_DSAB_STARTUP_RM__SIZE 0x00000001u
#define CYFLD_PASS_DSAB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_PASS_DSAB_ENABLED__SIZE 0x00000001u
#define CYREG_PASS_DSAB_DSAB_DFT 0x403f0e04u
#define CYFLD_PASS_DSAB_EN_DFT__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_EN_DFT__SIZE 0x00000004u
#define CYREG_PASS_DSAB_TRIM 0x403f0f00u
#define CYFLD_PASS_IBIAS_TRIM__OFFSET 0x00000000u
#define CYFLD_PASS_IBIAS_TRIM__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_RMB_BITS__OFFSET 0x00000004u
#define CYFLD_PASS_DSAB_RMB_BITS__SIZE 0x00000002u
#define CYDEV_CM0P_BASE 0xe0000000u
#define CYDEV_CM0P_SIZE 0x00100000u
#define CYREG_CM0P_DWT_PID4 0xe0001fd0u
#define CYFLD_CM0P_VALUE__OFFSET 0x00000000u
#define CYFLD_CM0P_VALUE__SIZE 0x00000020u
#define CYREG_CM0P_DWT_PID0 0xe0001fe0u
#define CYREG_CM0P_DWT_PID1 0xe0001fe4u
#define CYREG_CM0P_DWT_PID2 0xe0001fe8u
#define CYREG_CM0P_DWT_PID3 0xe0001fecu
#define CYREG_CM0P_DWT_CID0 0xe0001ff0u
#define CYREG_CM0P_DWT_CID1 0xe0001ff4u
#define CYREG_CM0P_DWT_CID2 0xe0001ff8u
#define CYREG_CM0P_DWT_CID3 0xe0001ffcu
#define CYREG_CM0P_BP_PID4 0xe0002fd0u
#define CYREG_CM0P_BP_PID0 0xe0002fe0u
#define CYREG_CM0P_BP_PID1 0xe0002fe4u
#define CYREG_CM0P_BP_PID2 0xe0002fe8u
#define CYREG_CM0P_BP_PID3 0xe0002fecu
#define CYREG_CM0P_BP_CID0 0xe0002ff0u
#define CYREG_CM0P_BP_CID1 0xe0002ff4u
#define CYREG_CM0P_BP_CID2 0xe0002ff8u
#define CYREG_CM0P_BP_CID3 0xe0002ffcu
#define CYREG_CM0P_SYST_CSR 0xe000e010u
#define CYFLD_CM0P_ENABLE__OFFSET 0x00000000u
#define CYFLD_CM0P_ENABLE__SIZE 0x00000001u
#define CYFLD_CM0P_TICKINT__OFFSET 0x00000001u
#define CYFLD_CM0P_TICKINT__SIZE 0x00000001u
#define CYFLD_CM0P_CLKSOURCE__OFFSET 0x00000002u
#define CYFLD_CM0P_CLKSOURCE__SIZE 0x00000001u
#define CYFLD_CM0P_COUNTFLAG__OFFSET 0x00000010u
#define CYFLD_CM0P_COUNTFLAG__SIZE 0x00000001u
#define CYREG_CM0P_SYST_RVR 0xe000e014u
#define CYFLD_CM0P_RELOAD__OFFSET 0x00000000u
#define CYFLD_CM0P_RELOAD__SIZE 0x00000018u
#define CYREG_CM0P_SYST_CVR 0xe000e018u
#define CYFLD_CM0P_CURRENT__OFFSET 0x00000000u
#define CYFLD_CM0P_CURRENT__SIZE 0x00000018u
#define CYREG_CM0P_SYST_CALIB 0xe000e01cu
#define CYFLD_CM0P_TENMS__OFFSET 0x00000000u
#define CYFLD_CM0P_TENMS__SIZE 0x00000018u
#define CYFLD_CM0P_SKEW__OFFSET 0x0000001eu
#define CYFLD_CM0P_SKEW__SIZE 0x00000001u
#define CYFLD_CM0P_NOREF__OFFSET 0x0000001fu
#define CYFLD_CM0P_NOREF__SIZE 0x00000001u
#define CYREG_CM0P_ISER 0xe000e100u
#define CYFLD_CM0P_SETENA__OFFSET 0x00000000u
#define CYFLD_CM0P_SETENA__SIZE 0x00000020u
#define CYREG_CM0P_ICER 0xe000e180u
#define CYFLD_CM0P_CLRENA__OFFSET 0x00000000u
#define CYFLD_CM0P_CLRENA__SIZE 0x00000020u
#define CYREG_CM0P_ISPR 0xe000e200u
#define CYFLD_CM0P_SETPEND__OFFSET 0x00000000u
#define CYFLD_CM0P_SETPEND__SIZE 0x00000020u
#define CYREG_CM0P_ICPR 0xe000e280u
#define CYFLD_CM0P_CLRPEND__OFFSET 0x00000000u
#define CYFLD_CM0P_CLRPEND__SIZE 0x00000020u
#define CYREG_CM0P_IPR0 0xe000e400u
#define CYFLD_CM0P_PRI_N0__OFFSET 0x00000006u
#define CYFLD_CM0P_PRI_N0__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N1__OFFSET 0x0000000eu
#define CYFLD_CM0P_PRI_N1__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N2__OFFSET 0x00000016u
#define CYFLD_CM0P_PRI_N2__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N3__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_N3__SIZE 0x00000002u
#define CYREG_CM0P_IPR1 0xe000e404u
#define CYREG_CM0P_IPR2 0xe000e408u
#define CYREG_CM0P_IPR3 0xe000e40cu
#define CYREG_CM0P_IPR4 0xe000e410u
#define CYREG_CM0P_IPR5 0xe000e414u
#define CYREG_CM0P_IPR6 0xe000e418u
#define CYREG_CM0P_IPR7 0xe000e41cu
#define CYREG_CM0P_CPUID 0xe000ed00u
#define CYFLD_CM0P_REVISION__OFFSET 0x00000000u
#define CYFLD_CM0P_REVISION__SIZE 0x00000004u
#define CYFLD_CM0P_PARTNO__OFFSET 0x00000004u
#define CYFLD_CM0P_PARTNO__SIZE 0x0000000cu
#define CYFLD_CM0P_CONSTANT__OFFSET 0x00000010u
#define CYFLD_CM0P_CONSTANT__SIZE 0x00000004u
#define CYFLD_CM0P_VARIANT__OFFSET 0x00000014u
#define CYFLD_CM0P_VARIANT__SIZE 0x00000004u
#define CYFLD_CM0P_IMPLEMENTER__OFFSET 0x00000018u
#define CYFLD_CM0P_IMPLEMENTER__SIZE 0x00000008u
#define CYREG_CM0P_ICSR 0xe000ed04u
#define CYFLD_CM0P_VECTACTIVE__OFFSET 0x00000000u
#define CYFLD_CM0P_VECTACTIVE__SIZE 0x00000009u
#define CYFLD_CM0P_VECTPENDING__OFFSET 0x0000000cu
#define CYFLD_CM0P_VECTPENDING__SIZE 0x00000009u
#define CYFLD_CM0P_ISRPENDING__OFFSET 0x00000016u
#define CYFLD_CM0P_ISRPENDING__SIZE 0x00000001u
#define CYFLD_CM0P_ISRPREEMPT__OFFSET 0x00000017u
#define CYFLD_CM0P_ISRPREEMPT__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSTCLR__OFFSET 0x00000019u
#define CYFLD_CM0P_PENDSTCLR__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSTSETb__OFFSET 0x0000001au
#define CYFLD_CM0P_PENDSTSETb__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSVCLR__OFFSET 0x0000001bu
#define CYFLD_CM0P_PENDSVCLR__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSVSET__OFFSET 0x0000001cu
#define CYFLD_CM0P_PENDSVSET__SIZE 0x00000001u
#define CYFLD_CM0P_NMIPENDSET__OFFSET 0x0000001fu
#define CYFLD_CM0P_NMIPENDSET__SIZE 0x00000001u
#define CYREG_CM0P_VTOR 0xe000ed08u
#define CYFLD_CM0P_TBLOFF__OFFSET 0x00000008u
#define CYFLD_CM0P_TBLOFF__SIZE 0x00000018u
#define CYREG_CM0P_AIRCR 0xe000ed0cu
#define CYFLD_CM0P_VECTCLRACTIVE__OFFSET 0x00000001u
#define CYFLD_CM0P_VECTCLRACTIVE__SIZE 0x00000001u
#define CYFLD_CM0P_SYSRESETREQ__OFFSET 0x00000002u
#define CYFLD_CM0P_SYSRESETREQ__SIZE 0x00000001u
#define CYFLD_CM0P_ENDIANNESS__OFFSET 0x0000000fu
#define CYFLD_CM0P_ENDIANNESS__SIZE 0x00000001u
#define CYFLD_CM0P_VECTKEY__OFFSET 0x00000010u
#define CYFLD_CM0P_VECTKEY__SIZE 0x00000010u
#define CYREG_CM0P_SCR 0xe000ed10u
#define CYFLD_CM0P_SLEEPONEXIT__OFFSET 0x00000001u
#define CYFLD_CM0P_SLEEPONEXIT__SIZE 0x00000001u
#define CYFLD_CM0P_SLEEPDEEP__OFFSET 0x00000002u
#define CYFLD_CM0P_SLEEPDEEP__SIZE 0x00000001u
#define CYFLD_CM0P_SEVONPEND__OFFSET 0x00000004u
#define CYFLD_CM0P_SEVONPEND__SIZE 0x00000001u
#define CYREG_CM0P_CCR 0xe000ed14u
#define CYFLD_CM0P_UNALIGN_TRP__OFFSET 0x00000003u
#define CYFLD_CM0P_UNALIGN_TRP__SIZE 0x00000001u
#define CYFLD_CM0P_STKALIGN__OFFSET 0x00000009u
#define CYFLD_CM0P_STKALIGN__SIZE 0x00000001u
#define CYREG_CM0P_SHPR2 0xe000ed1cu
#define CYFLD_CM0P_PRI_11__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_11__SIZE 0x00000002u
#define CYREG_CM0P_SHPR3 0xe000ed20u
#define CYFLD_CM0P_PRI_14__OFFSET 0x00000016u
#define CYFLD_CM0P_PRI_14__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_15__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_15__SIZE 0x00000002u
#define CYREG_CM0P_SHCSR 0xe000ed24u
#define CYFLD_CM0P_SVCALLPENDED__OFFSET 0x0000000fu
#define CYFLD_CM0P_SVCALLPENDED__SIZE 0x00000001u
#define CYREG_CM0P_SCS_PID4 0xe000efd0u
#define CYREG_CM0P_SCS_PID0 0xe000efe0u
#define CYREG_CM0P_SCS_PID1 0xe000efe4u
#define CYREG_CM0P_SCS_PID2 0xe000efe8u
#define CYREG_CM0P_SCS_PID3 0xe000efecu
#define CYREG_CM0P_SCS_CID0 0xe000eff0u
#define CYREG_CM0P_SCS_CID1 0xe000eff4u
#define CYREG_CM0P_SCS_CID2 0xe000eff8u
#define CYREG_CM0P_SCS_CID3 0xe000effcu
#define CYREG_CM0P_ROM_SCS 0xe00ff000u
#define CYREG_CM0P_ROM_DWT 0xe00ff004u
#define CYREG_CM0P_ROM_BPU 0xe00ff008u
#define CYREG_CM0P_ROM_END 0xe00ff00cu
#define CYREG_CM0P_ROM_CSMT 0xe00fffccu
#define CYREG_CM0P_ROM_PID4 0xe00fffd0u
#define CYREG_CM0P_ROM_PID0 0xe00fffe0u
#define CYREG_CM0P_ROM_PID1 0xe00fffe4u
#define CYREG_CM0P_ROM_PID2 0xe00fffe8u
#define CYREG_CM0P_ROM_PID3 0xe00fffecu
#define CYREG_CM0P_ROM_CID0 0xe00ffff0u
#define CYREG_CM0P_ROM_CID1 0xe00ffff4u
#define CYREG_CM0P_ROM_CID2 0xe00ffff8u
#define CYREG_CM0P_ROM_CID3 0xe00ffffcu
#define CYDEV_ROMTABLE_BASE 0xf0000000u
#define CYDEV_ROMTABLE_SIZE 0x00001000u
#define CYREG_ROMTABLE_ADDR 0xf0000000u
#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000cu
#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014u
#define CYREG_ROMTABLE_DID 0xf0000fccu
#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020u
#define CYREG_ROMTABLE_PID4 0xf0000fd0u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004u
#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID5 0xf0000fd4u
#define CYREG_ROMTABLE_PID6 0xf0000fd8u
#define CYREG_ROMTABLE_PID7 0xf0000fdcu
#define CYREG_ROMTABLE_PID0 0xf0000fe0u
#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008u
#define CYREG_ROMTABLE_PID1 0xf0000fe4u
#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID2 0xf0000fe8u
#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003u
#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID3 0xf0000fecu
#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_CM__SIZE 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004u
#define CYREG_ROMTABLE_CID0 0xf0000ff0u
#define CYREG_ROMTABLE_CID1 0xf0000ff4u
#define CYREG_ROMTABLE_CID2 0xf0000ff8u
#define CYREG_ROMTABLE_CID3 0xf0000ffcu
#define CYDEV_FLS_SECTOR_SIZE 0x00010000u
#define CYDEV_FLS_ROW_SIZE 0x00000080u
#define CYREG_SFLASH_PROT_ROW00 CYREG_SFLASH_PROT_ROW0
#define CYREG_SFLASH_PROT_ROW01 CYREG_SFLASH_PROT_ROW1
#define CYREG_SFLASH_PROT_ROW02 CYREG_SFLASH_PROT_ROW2
#define CYREG_SFLASH_PROT_ROW03 CYREG_SFLASH_PROT_ROW3
#define CYREG_SFLASH_PROT_ROW04 CYREG_SFLASH_PROT_ROW4
#define CYREG_SFLASH_PROT_ROW05 CYREG_SFLASH_PROT_ROW5
#define CYREG_SFLASH_PROT_ROW06 CYREG_SFLASH_PROT_ROW6
#define CYREG_SFLASH_PROT_ROW07 CYREG_SFLASH_PROT_ROW7
#define CYREG_SFLASH_PROT_ROW08 CYREG_SFLASH_PROT_ROW8
#define CYREG_SFLASH_PROT_ROW09 CYREG_SFLASH_PROT_ROW9
#define CYREG_SFLASH_AV_PAIRS_8B000 CYREG_SFLASH_AV_PAIRS_8B0
#define CYREG_SFLASH_AV_PAIRS_8B001 CYREG_SFLASH_AV_PAIRS_8B1
#define CYREG_SFLASH_AV_PAIRS_8B002 CYREG_SFLASH_AV_PAIRS_8B2
#define CYREG_SFLASH_AV_PAIRS_8B003 CYREG_SFLASH_AV_PAIRS_8B3
#define CYREG_SFLASH_AV_PAIRS_8B004 CYREG_SFLASH_AV_PAIRS_8B4
#define CYREG_SFLASH_AV_PAIRS_8B005 CYREG_SFLASH_AV_PAIRS_8B5
#define CYREG_SFLASH_AV_PAIRS_8B006 CYREG_SFLASH_AV_PAIRS_8B6
#define CYREG_SFLASH_AV_PAIRS_8B007 CYREG_SFLASH_AV_PAIRS_8B7
#define CYREG_SFLASH_AV_PAIRS_8B008 CYREG_SFLASH_AV_PAIRS_8B8
#define CYREG_SFLASH_AV_PAIRS_8B009 CYREG_SFLASH_AV_PAIRS_8B9
#define CYREG_SFLASH_AV_PAIRS_8B010 CYREG_SFLASH_AV_PAIRS_8B10
#define CYREG_SFLASH_AV_PAIRS_8B011 CYREG_SFLASH_AV_PAIRS_8B11
#define CYREG_SFLASH_AV_PAIRS_8B012 CYREG_SFLASH_AV_PAIRS_8B12
#define CYREG_SFLASH_AV_PAIRS_8B013 CYREG_SFLASH_AV_PAIRS_8B13
#define CYREG_SFLASH_AV_PAIRS_8B014 CYREG_SFLASH_AV_PAIRS_8B14
#define CYREG_SFLASH_AV_PAIRS_8B015 CYREG_SFLASH_AV_PAIRS_8B15
#define CYREG_SFLASH_AV_PAIRS_8B016 CYREG_SFLASH_AV_PAIRS_8B16
#define CYREG_SFLASH_AV_PAIRS_8B017 CYREG_SFLASH_AV_PAIRS_8B17
#define CYREG_SFLASH_AV_PAIRS_8B018 CYREG_SFLASH_AV_PAIRS_8B18
#define CYREG_SFLASH_AV_PAIRS_8B019 CYREG_SFLASH_AV_PAIRS_8B19
#define CYREG_SFLASH_AV_PAIRS_8B020 CYREG_SFLASH_AV_PAIRS_8B20
#define CYREG_SFLASH_AV_PAIRS_8B021 CYREG_SFLASH_AV_PAIRS_8B21
#define CYREG_SFLASH_AV_PAIRS_8B022 CYREG_SFLASH_AV_PAIRS_8B22
#define CYREG_SFLASH_AV_PAIRS_8B023 CYREG_SFLASH_AV_PAIRS_8B23
#define CYREG_SFLASH_AV_PAIRS_8B024 CYREG_SFLASH_AV_PAIRS_8B24
#define CYREG_SFLASH_AV_PAIRS_8B025 CYREG_SFLASH_AV_PAIRS_8B25
#define CYREG_SFLASH_AV_PAIRS_8B026 CYREG_SFLASH_AV_PAIRS_8B26
#define CYREG_SFLASH_AV_PAIRS_8B027 CYREG_SFLASH_AV_PAIRS_8B27
#define CYREG_SFLASH_AV_PAIRS_8B028 CYREG_SFLASH_AV_PAIRS_8B28
#define CYREG_SFLASH_AV_PAIRS_8B029 CYREG_SFLASH_AV_PAIRS_8B29
#define CYREG_SFLASH_AV_PAIRS_8B030 CYREG_SFLASH_AV_PAIRS_8B30
#define CYREG_SFLASH_AV_PAIRS_8B031 CYREG_SFLASH_AV_PAIRS_8B31
#define CYREG_SFLASH_AV_PAIRS_8B032 CYREG_SFLASH_AV_PAIRS_8B32
#define CYREG_SFLASH_AV_PAIRS_8B033 CYREG_SFLASH_AV_PAIRS_8B33
#define CYREG_SFLASH_AV_PAIRS_8B034 CYREG_SFLASH_AV_PAIRS_8B34
#define CYREG_SFLASH_AV_PAIRS_8B035 CYREG_SFLASH_AV_PAIRS_8B35
#define CYREG_SFLASH_AV_PAIRS_8B036 CYREG_SFLASH_AV_PAIRS_8B36
#define CYREG_SFLASH_AV_PAIRS_8B037 CYREG_SFLASH_AV_PAIRS_8B37
#define CYREG_SFLASH_AV_PAIRS_8B038 CYREG_SFLASH_AV_PAIRS_8B38
#define CYREG_SFLASH_AV_PAIRS_8B039 CYREG_SFLASH_AV_PAIRS_8B39
#define CYREG_SFLASH_AV_PAIRS_8B040 CYREG_SFLASH_AV_PAIRS_8B40
#define CYREG_SFLASH_AV_PAIRS_8B041 CYREG_SFLASH_AV_PAIRS_8B41
#define CYREG_SFLASH_AV_PAIRS_8B042 CYREG_SFLASH_AV_PAIRS_8B42
#define CYREG_SFLASH_AV_PAIRS_8B043 CYREG_SFLASH_AV_PAIRS_8B43
#define CYREG_SFLASH_AV_PAIRS_8B044 CYREG_SFLASH_AV_PAIRS_8B44
#define CYREG_SFLASH_AV_PAIRS_8B045 CYREG_SFLASH_AV_PAIRS_8B45
#define CYREG_SFLASH_AV_PAIRS_8B046 CYREG_SFLASH_AV_PAIRS_8B46
#define CYREG_SFLASH_AV_PAIRS_8B047 CYREG_SFLASH_AV_PAIRS_8B47
#define CYREG_SFLASH_AV_PAIRS_8B048 CYREG_SFLASH_AV_PAIRS_8B48
#define CYREG_SFLASH_AV_PAIRS_8B049 CYREG_SFLASH_AV_PAIRS_8B49
#define CYREG_SFLASH_AV_PAIRS_8B050 CYREG_SFLASH_AV_PAIRS_8B50
#define CYREG_SFLASH_AV_PAIRS_8B051 CYREG_SFLASH_AV_PAIRS_8B51
#define CYREG_SFLASH_AV_PAIRS_8B052 CYREG_SFLASH_AV_PAIRS_8B52
#define CYREG_SFLASH_AV_PAIRS_8B053 CYREG_SFLASH_AV_PAIRS_8B53
#define CYREG_SFLASH_AV_PAIRS_8B054 CYREG_SFLASH_AV_PAIRS_8B54
#define CYREG_SFLASH_AV_PAIRS_8B055 CYREG_SFLASH_AV_PAIRS_8B55
#define CYREG_SFLASH_AV_PAIRS_8B056 CYREG_SFLASH_AV_PAIRS_8B56
#define CYREG_SFLASH_AV_PAIRS_8B057 CYREG_SFLASH_AV_PAIRS_8B57
#define CYREG_SFLASH_AV_PAIRS_8B058 CYREG_SFLASH_AV_PAIRS_8B58
#define CYREG_SFLASH_AV_PAIRS_8B059 CYREG_SFLASH_AV_PAIRS_8B59
#define CYREG_SFLASH_AV_PAIRS_8B060 CYREG_SFLASH_AV_PAIRS_8B60
#define CYREG_SFLASH_AV_PAIRS_8B061 CYREG_SFLASH_AV_PAIRS_8B61
#define CYREG_SFLASH_AV_PAIRS_8B062 CYREG_SFLASH_AV_PAIRS_8B62
#define CYREG_SFLASH_AV_PAIRS_8B063 CYREG_SFLASH_AV_PAIRS_8B63
#define CYREG_SFLASH_AV_PAIRS_8B064 CYREG_SFLASH_AV_PAIRS_8B64
#define CYREG_SFLASH_AV_PAIRS_8B065 CYREG_SFLASH_AV_PAIRS_8B65
#define CYREG_SFLASH_AV_PAIRS_8B066 CYREG_SFLASH_AV_PAIRS_8B66
#define CYREG_SFLASH_AV_PAIRS_8B067 CYREG_SFLASH_AV_PAIRS_8B67
#define CYREG_SFLASH_AV_PAIRS_8B068 CYREG_SFLASH_AV_PAIRS_8B68
#define CYREG_SFLASH_AV_PAIRS_8B069 CYREG_SFLASH_AV_PAIRS_8B69
#define CYREG_SFLASH_AV_PAIRS_8B070 CYREG_SFLASH_AV_PAIRS_8B70
#define CYREG_SFLASH_AV_PAIRS_8B071 CYREG_SFLASH_AV_PAIRS_8B71
#define CYREG_SFLASH_AV_PAIRS_8B072 CYREG_SFLASH_AV_PAIRS_8B72
#define CYREG_SFLASH_AV_PAIRS_8B073 CYREG_SFLASH_AV_PAIRS_8B73
#define CYREG_SFLASH_AV_PAIRS_8B074 CYREG_SFLASH_AV_PAIRS_8B74
#define CYREG_SFLASH_AV_PAIRS_8B075 CYREG_SFLASH_AV_PAIRS_8B75
#define CYREG_SFLASH_AV_PAIRS_8B076 CYREG_SFLASH_AV_PAIRS_8B76
#define CYREG_SFLASH_AV_PAIRS_8B077 CYREG_SFLASH_AV_PAIRS_8B77
#define CYREG_SFLASH_AV_PAIRS_8B078 CYREG_SFLASH_AV_PAIRS_8B78
#define CYREG_SFLASH_AV_PAIRS_8B079 CYREG_SFLASH_AV_PAIRS_8B79
#define CYREG_SFLASH_AV_PAIRS_8B080 CYREG_SFLASH_AV_PAIRS_8B80
#define CYREG_SFLASH_AV_PAIRS_8B081 CYREG_SFLASH_AV_PAIRS_8B81
#define CYREG_SFLASH_AV_PAIRS_8B082 CYREG_SFLASH_AV_PAIRS_8B82
#define CYREG_SFLASH_AV_PAIRS_8B083 CYREG_SFLASH_AV_PAIRS_8B83
#define CYREG_SFLASH_AV_PAIRS_8B084 CYREG_SFLASH_AV_PAIRS_8B84
#define CYREG_SFLASH_AV_PAIRS_8B085 CYREG_SFLASH_AV_PAIRS_8B85
#define CYREG_SFLASH_AV_PAIRS_8B086 CYREG_SFLASH_AV_PAIRS_8B86
#define CYREG_SFLASH_AV_PAIRS_8B087 CYREG_SFLASH_AV_PAIRS_8B87
#define CYREG_SFLASH_AV_PAIRS_8B088 CYREG_SFLASH_AV_PAIRS_8B88
#define CYREG_SFLASH_AV_PAIRS_8B089 CYREG_SFLASH_AV_PAIRS_8B89
#define CYREG_SFLASH_AV_PAIRS_8B090 CYREG_SFLASH_AV_PAIRS_8B90
#define CYREG_SFLASH_AV_PAIRS_8B091 CYREG_SFLASH_AV_PAIRS_8B91
#define CYREG_SFLASH_AV_PAIRS_8B092 CYREG_SFLASH_AV_PAIRS_8B92
#define CYREG_SFLASH_AV_PAIRS_8B093 CYREG_SFLASH_AV_PAIRS_8B93
#define CYREG_SFLASH_AV_PAIRS_8B094 CYREG_SFLASH_AV_PAIRS_8B94
#define CYREG_SFLASH_AV_PAIRS_8B095 CYREG_SFLASH_AV_PAIRS_8B95
#define CYREG_SFLASH_AV_PAIRS_8B096 CYREG_SFLASH_AV_PAIRS_8B96
#define CYREG_SFLASH_AV_PAIRS_8B097 CYREG_SFLASH_AV_PAIRS_8B97
#define CYREG_SFLASH_AV_PAIRS_8B098 CYREG_SFLASH_AV_PAIRS_8B98
#define CYREG_SFLASH_AV_PAIRS_8B099 CYREG_SFLASH_AV_PAIRS_8B99
#define CYREG_SFLASH_AV_PAIRS_32B00 CYREG_SFLASH_AV_PAIRS_32B0
#define CYREG_SFLASH_AV_PAIRS_32B01 CYREG_SFLASH_AV_PAIRS_32B1
#define CYREG_SFLASH_AV_PAIRS_32B02 CYREG_SFLASH_AV_PAIRS_32B2
#define CYREG_SFLASH_AV_PAIRS_32B03 CYREG_SFLASH_AV_PAIRS_32B3
#define CYREG_SFLASH_AV_PAIRS_32B04 CYREG_SFLASH_AV_PAIRS_32B4
#define CYREG_SFLASH_AV_PAIRS_32B05 CYREG_SFLASH_AV_PAIRS_32B5
#define CYREG_SFLASH_AV_PAIRS_32B06 CYREG_SFLASH_AV_PAIRS_32B6
#define CYREG_SFLASH_AV_PAIRS_32B07 CYREG_SFLASH_AV_PAIRS_32B7
#define CYREG_SFLASH_AV_PAIRS_32B08 CYREG_SFLASH_AV_PAIRS_32B8
#define CYREG_SFLASH_AV_PAIRS_32B09 CYREG_SFLASH_AV_PAIRS_32B9
#define CYREG_SFLASH_PE_TE_DATA00 CYREG_SFLASH_PE_TE_DATA0
#define CYREG_SFLASH_PE_TE_DATA01 CYREG_SFLASH_PE_TE_DATA1
#define CYREG_SFLASH_PE_TE_DATA02 CYREG_SFLASH_PE_TE_DATA2
#define CYREG_SFLASH_PE_TE_DATA03 CYREG_SFLASH_PE_TE_DATA3
#define CYREG_SFLASH_PE_TE_DATA04 CYREG_SFLASH_PE_TE_DATA4
#define CYREG_SFLASH_PE_TE_DATA05 CYREG_SFLASH_PE_TE_DATA5
#define CYREG_SFLASH_PE_TE_DATA06 CYREG_SFLASH_PE_TE_DATA6
#define CYREG_SFLASH_PE_TE_DATA07 CYREG_SFLASH_PE_TE_DATA7
#define CYREG_SFLASH_PE_TE_DATA08 CYREG_SFLASH_PE_TE_DATA8
#define CYREG_SFLASH_PE_TE_DATA09 CYREG_SFLASH_PE_TE_DATA9
#define CYREG_SFLASH_IMO_TRIM00 CYREG_SFLASH_IMO_TRIM0
#define CYREG_SFLASH_IMO_TRIM01 CYREG_SFLASH_IMO_TRIM1
#define CYREG_SFLASH_IMO_TRIM02 CYREG_SFLASH_IMO_TRIM2
#define CYREG_SFLASH_IMO_TRIM03 CYREG_SFLASH_IMO_TRIM3
#define CYREG_SFLASH_IMO_TRIM04 CYREG_SFLASH_IMO_TRIM4
#define CYREG_SFLASH_IMO_TRIM05 CYREG_SFLASH_IMO_TRIM5
#define CYREG_SFLASH_IMO_TRIM06 CYREG_SFLASH_IMO_TRIM6
#define CYREG_SFLASH_IMO_TRIM07 CYREG_SFLASH_IMO_TRIM7
#define CYREG_SFLASH_IMO_TRIM08 CYREG_SFLASH_IMO_TRIM8
#define CYREG_SFLASH_IMO_TRIM09 CYREG_SFLASH_IMO_TRIM9
#define CYREG_SFLASH_ALT_PROT_ROW000 CYREG_SFLASH_ALT_PROT_ROW0
#define CYREG_SFLASH_ALT_PROT_ROW001 CYREG_SFLASH_ALT_PROT_ROW1
#define CYREG_SFLASH_ALT_PROT_ROW002 CYREG_SFLASH_ALT_PROT_ROW2
#define CYREG_SFLASH_ALT_PROT_ROW003 CYREG_SFLASH_ALT_PROT_ROW3
#define CYREG_SFLASH_ALT_PROT_ROW004 CYREG_SFLASH_ALT_PROT_ROW4
#define CYREG_SFLASH_ALT_PROT_ROW005 CYREG_SFLASH_ALT_PROT_ROW5
#define CYREG_SFLASH_ALT_PROT_ROW006 CYREG_SFLASH_ALT_PROT_ROW6
#define CYREG_SFLASH_ALT_PROT_ROW007 CYREG_SFLASH_ALT_PROT_ROW7
#define CYREG_SFLASH_ALT_PROT_ROW008 CYREG_SFLASH_ALT_PROT_ROW8
#define CYREG_SFLASH_ALT_PROT_ROW009 CYREG_SFLASH_ALT_PROT_ROW9
#define CYREG_SFLASH_ALT_PROT_ROW010 CYREG_SFLASH_ALT_PROT_ROW10
#define CYREG_SFLASH_ALT_PROT_ROW011 CYREG_SFLASH_ALT_PROT_ROW11
#define CYREG_SFLASH_ALT_PROT_ROW012 CYREG_SFLASH_ALT_PROT_ROW12
#define CYREG_SFLASH_ALT_PROT_ROW013 CYREG_SFLASH_ALT_PROT_ROW13
#define CYREG_SFLASH_ALT_PROT_ROW014 CYREG_SFLASH_ALT_PROT_ROW14
#define CYREG_SFLASH_ALT_PROT_ROW015 CYREG_SFLASH_ALT_PROT_ROW15
#define CYREG_SFLASH_ALT_PROT_ROW016 CYREG_SFLASH_ALT_PROT_ROW16
#define CYREG_SFLASH_ALT_PROT_ROW017 CYREG_SFLASH_ALT_PROT_ROW17
#define CYREG_SFLASH_ALT_PROT_ROW018 CYREG_SFLASH_ALT_PROT_ROW18
#define CYREG_SFLASH_ALT_PROT_ROW019 CYREG_SFLASH_ALT_PROT_ROW19
#define CYREG_SFLASH_ALT_PROT_ROW020 CYREG_SFLASH_ALT_PROT_ROW20
#define CYREG_SFLASH_ALT_PROT_ROW021 CYREG_SFLASH_ALT_PROT_ROW21
#define CYREG_SFLASH_ALT_PROT_ROW022 CYREG_SFLASH_ALT_PROT_ROW22
#define CYREG_SFLASH_ALT_PROT_ROW023 CYREG_SFLASH_ALT_PROT_ROW23
#define CYREG_SFLASH_ALT_PROT_ROW024 CYREG_SFLASH_ALT_PROT_ROW24
#define CYREG_SFLASH_ALT_PROT_ROW025 CYREG_SFLASH_ALT_PROT_ROW25
#define CYREG_SFLASH_ALT_PROT_ROW026 CYREG_SFLASH_ALT_PROT_ROW26
#define CYREG_SFLASH_ALT_PROT_ROW027 CYREG_SFLASH_ALT_PROT_ROW27
#define CYREG_SFLASH_ALT_PROT_ROW028 CYREG_SFLASH_ALT_PROT_ROW28
#define CYREG_SFLASH_ALT_PROT_ROW029 CYREG_SFLASH_ALT_PROT_ROW29
#define CYREG_SFLASH_ALT_PROT_ROW030 CYREG_SFLASH_ALT_PROT_ROW30
#define CYREG_SFLASH_ALT_PROT_ROW031 CYREG_SFLASH_ALT_PROT_ROW31
#define CYREG_SFLASH_ALT_PROT_ROW032 CYREG_SFLASH_ALT_PROT_ROW32
#define CYREG_SFLASH_ALT_PROT_ROW033 CYREG_SFLASH_ALT_PROT_ROW33
#define CYREG_SFLASH_ALT_PROT_ROW034 CYREG_SFLASH_ALT_PROT_ROW34
#define CYREG_SFLASH_ALT_PROT_ROW035 CYREG_SFLASH_ALT_PROT_ROW35
#define CYREG_SFLASH_ALT_PROT_ROW036 CYREG_SFLASH_ALT_PROT_ROW36
#define CYREG_SFLASH_ALT_PROT_ROW037 CYREG_SFLASH_ALT_PROT_ROW37
#define CYREG_SFLASH_ALT_PROT_ROW038 CYREG_SFLASH_ALT_PROT_ROW38
#define CYREG_SFLASH_ALT_PROT_ROW039 CYREG_SFLASH_ALT_PROT_ROW39
#define CYREG_SFLASH_ALT_PROT_ROW040 CYREG_SFLASH_ALT_PROT_ROW40
#define CYREG_SFLASH_ALT_PROT_ROW041 CYREG_SFLASH_ALT_PROT_ROW41
#define CYREG_SFLASH_ALT_PROT_ROW042 CYREG_SFLASH_ALT_PROT_ROW42
#define CYREG_SFLASH_ALT_PROT_ROW043 CYREG_SFLASH_ALT_PROT_ROW43
#define CYREG_SFLASH_ALT_PROT_ROW044 CYREG_SFLASH_ALT_PROT_ROW44
#define CYREG_SFLASH_ALT_PROT_ROW045 CYREG_SFLASH_ALT_PROT_ROW45
#define CYREG_SFLASH_ALT_PROT_ROW046 CYREG_SFLASH_ALT_PROT_ROW46
#define CYREG_SFLASH_ALT_PROT_ROW047 CYREG_SFLASH_ALT_PROT_ROW47
#define CYREG_SFLASH_ALT_PROT_ROW048 CYREG_SFLASH_ALT_PROT_ROW48
#define CYREG_SFLASH_ALT_PROT_ROW049 CYREG_SFLASH_ALT_PROT_ROW49
#define CYREG_SFLASH_ALT_PROT_ROW050 CYREG_SFLASH_ALT_PROT_ROW50
#define CYREG_SFLASH_ALT_PROT_ROW051 CYREG_SFLASH_ALT_PROT_ROW51
#define CYREG_SFLASH_ALT_PROT_ROW052 CYREG_SFLASH_ALT_PROT_ROW52
#define CYREG_SFLASH_ALT_PROT_ROW053 CYREG_SFLASH_ALT_PROT_ROW53
#define CYREG_SFLASH_ALT_PROT_ROW054 CYREG_SFLASH_ALT_PROT_ROW54
#define CYREG_SFLASH_ALT_PROT_ROW055 CYREG_SFLASH_ALT_PROT_ROW55
#define CYREG_SFLASH_ALT_PROT_ROW056 CYREG_SFLASH_ALT_PROT_ROW56
#define CYREG_SFLASH_ALT_PROT_ROW057 CYREG_SFLASH_ALT_PROT_ROW57
#define CYREG_SFLASH_ALT_PROT_ROW058 CYREG_SFLASH_ALT_PROT_ROW58
#define CYREG_SFLASH_ALT_PROT_ROW059 CYREG_SFLASH_ALT_PROT_ROW59
#define CYREG_SFLASH_ALT_PROT_ROW060 CYREG_SFLASH_ALT_PROT_ROW60
#define CYREG_SFLASH_ALT_PROT_ROW061 CYREG_SFLASH_ALT_PROT_ROW61
#define CYREG_SFLASH_ALT_PROT_ROW062 CYREG_SFLASH_ALT_PROT_ROW62
#define CYREG_SFLASH_ALT_PROT_ROW063 CYREG_SFLASH_ALT_PROT_ROW63
#define CYREG_SFLASH_ALT_PROT_ROW064 CYREG_SFLASH_ALT_PROT_ROW64
#define CYREG_SFLASH_ALT_PROT_ROW065 CYREG_SFLASH_ALT_PROT_ROW65
#define CYREG_SFLASH_ALT_PROT_ROW066 CYREG_SFLASH_ALT_PROT_ROW66
#define CYREG_SFLASH_ALT_PROT_ROW067 CYREG_SFLASH_ALT_PROT_ROW67
#define CYREG_SFLASH_ALT_PROT_ROW068 CYREG_SFLASH_ALT_PROT_ROW68
#define CYREG_SFLASH_ALT_PROT_ROW069 CYREG_SFLASH_ALT_PROT_ROW69
#define CYREG_SFLASH_ALT_PROT_ROW070 CYREG_SFLASH_ALT_PROT_ROW70
#define CYREG_SFLASH_ALT_PROT_ROW071 CYREG_SFLASH_ALT_PROT_ROW71
#define CYREG_SFLASH_ALT_PROT_ROW072 CYREG_SFLASH_ALT_PROT_ROW72
#define CYREG_SFLASH_ALT_PROT_ROW073 CYREG_SFLASH_ALT_PROT_ROW73
#define CYREG_SFLASH_ALT_PROT_ROW074 CYREG_SFLASH_ALT_PROT_ROW74
#define CYREG_SFLASH_ALT_PROT_ROW075 CYREG_SFLASH_ALT_PROT_ROW75
#define CYREG_SFLASH_ALT_PROT_ROW076 CYREG_SFLASH_ALT_PROT_ROW76
#define CYREG_SFLASH_ALT_PROT_ROW077 CYREG_SFLASH_ALT_PROT_ROW77
#define CYREG_SFLASH_ALT_PROT_ROW078 CYREG_SFLASH_ALT_PROT_ROW78
#define CYREG_SFLASH_ALT_PROT_ROW079 CYREG_SFLASH_ALT_PROT_ROW79
#define CYREG_SFLASH_ALT_PROT_ROW080 CYREG_SFLASH_ALT_PROT_ROW80
#define CYREG_SFLASH_ALT_PROT_ROW081 CYREG_SFLASH_ALT_PROT_ROW81
#define CYREG_SFLASH_ALT_PROT_ROW082 CYREG_SFLASH_ALT_PROT_ROW82
#define CYREG_SFLASH_ALT_PROT_ROW083 CYREG_SFLASH_ALT_PROT_ROW83
#define CYREG_SFLASH_ALT_PROT_ROW084 CYREG_SFLASH_ALT_PROT_ROW84
#define CYREG_SFLASH_ALT_PROT_ROW085 CYREG_SFLASH_ALT_PROT_ROW85
#define CYREG_SFLASH_ALT_PROT_ROW086 CYREG_SFLASH_ALT_PROT_ROW86
#define CYREG_SFLASH_ALT_PROT_ROW087 CYREG_SFLASH_ALT_PROT_ROW87
#define CYREG_SFLASH_ALT_PROT_ROW088 CYREG_SFLASH_ALT_PROT_ROW88
#define CYREG_SFLASH_ALT_PROT_ROW089 CYREG_SFLASH_ALT_PROT_ROW89
#define CYREG_SFLASH_ALT_PROT_ROW090 CYREG_SFLASH_ALT_PROT_ROW90
#define CYREG_SFLASH_ALT_PROT_ROW091 CYREG_SFLASH_ALT_PROT_ROW91
#define CYREG_SFLASH_ALT_PROT_ROW092 CYREG_SFLASH_ALT_PROT_ROW92
#define CYREG_SFLASH_ALT_PROT_ROW093 CYREG_SFLASH_ALT_PROT_ROW93
#define CYREG_SFLASH_ALT_PROT_ROW094 CYREG_SFLASH_ALT_PROT_ROW94
#define CYREG_SFLASH_ALT_PROT_ROW095 CYREG_SFLASH_ALT_PROT_ROW95
#define CYREG_SFLASH_ALT_PROT_ROW096 CYREG_SFLASH_ALT_PROT_ROW96
#define CYREG_SFLASH_ALT_PROT_ROW097 CYREG_SFLASH_ALT_PROT_ROW97
#define CYREG_SFLASH_ALT_PROT_ROW098 CYREG_SFLASH_ALT_PROT_ROW98
#define CYREG_SFLASH_ALT_PROT_ROW099 CYREG_SFLASH_ALT_PROT_ROW99
#define CYREG_PERI_PCLK_CTL00 CYREG_PERI_PCLK_CTL0
#define CYREG_PERI_PCLK_CTL01 CYREG_PERI_PCLK_CTL1
#define CYREG_PERI_PCLK_CTL02 CYREG_PERI_PCLK_CTL2
#define CYREG_PERI_PCLK_CTL03 CYREG_PERI_PCLK_CTL3
#define CYREG_PERI_PCLK_CTL04 CYREG_PERI_PCLK_CTL4
#define CYREG_PERI_PCLK_CTL05 CYREG_PERI_PCLK_CTL5
#define CYREG_PERI_PCLK_CTL06 CYREG_PERI_PCLK_CTL6
#define CYREG_PERI_PCLK_CTL07 CYREG_PERI_PCLK_CTL7
#define CYREG_PERI_PCLK_CTL08 CYREG_PERI_PCLK_CTL8
#define CYREG_PERI_PCLK_CTL09 CYREG_PERI_PCLK_CTL9
#define CYREG_PERI_DIV_16_CTL00 CYREG_PERI_DIV_16_CTL0
#define CYREG_PERI_DIV_16_CTL01 CYREG_PERI_DIV_16_CTL1
#define CYREG_PERI_DIV_16_CTL02 CYREG_PERI_DIV_16_CTL2
#define CYREG_PERI_DIV_16_CTL03 CYREG_PERI_DIV_16_CTL3
#define CYREG_PERI_DIV_16_CTL04 CYREG_PERI_DIV_16_CTL4
#define CYREG_PERI_DIV_16_CTL05 CYREG_PERI_DIV_16_CTL5
#define CYREG_PERI_DIV_16_CTL06 CYREG_PERI_DIV_16_CTL6
#define CYREG_PERI_DIV_16_CTL07 CYREG_PERI_DIV_16_CTL7
#define CYREG_PERI_DIV_16_CTL08 CYREG_PERI_DIV_16_CTL8
#define CYREG_PERI_DIV_16_CTL09 CYREG_PERI_DIV_16_CTL9
#define CYFLD_PERI_SEL__OFFSET CYFLD_PERI_TR_GROUP_SEL__OFFSET
#define CYFLD_PERI_SEL__SIZE CYFLD_PERI_TR_GROUP_SEL__SIZE
#define CYREG_CPUSS_SL_CTL00 CYREG_CPUSS_SL_CTL0
#define CYREG_CPUSS_SL_CTL01 CYREG_CPUSS_SL_CTL1
#define CYREG_CPUSS_SL_CTL02 CYREG_CPUSS_SL_CTL2
#define CYREG_DMAC_CH_CTL00 CYREG_DMAC_CH_CTL0
#define CYREG_DMAC_CH_CTL01 CYREG_DMAC_CH_CTL1
#define CYREG_DMAC_CH_CTL02 CYREG_DMAC_CH_CTL2
#define CYREG_DMAC_CH_CTL03 CYREG_DMAC_CH_CTL3
#define CYREG_DMAC_CH_CTL04 CYREG_DMAC_CH_CTL4
#define CYREG_DMAC_CH_CTL05 CYREG_DMAC_CH_CTL5
#define CYREG_DMAC_CH_CTL06 CYREG_DMAC_CH_CTL6
#define CYREG_DMAC_CH_CTL07 CYREG_DMAC_CH_CTL7
#define CYREG_WCO_WCO_CONFIG CYREG_WCO_CONFIG
#define CYREG_WCO_WCO_STATUS CYREG_WCO_STATUS
#define CYREG_WCO_WCO_DPLL CYREG_WCO_DPLL
#define CYREG_WCO_WCO_TRIM CYREG_WCO_TRIM
#define CYREG_SCB0_EZ_DATA00 CYREG_SCB0_EZ_DATA0
#define CYREG_SCB0_EZ_DATA01 CYREG_SCB0_EZ_DATA1
#define CYREG_SCB0_EZ_DATA02 CYREG_SCB0_EZ_DATA2
#define CYREG_SCB0_EZ_DATA03 CYREG_SCB0_EZ_DATA3
#define CYREG_SCB0_EZ_DATA04 CYREG_SCB0_EZ_DATA4
#define CYREG_SCB0_EZ_DATA05 CYREG_SCB0_EZ_DATA5
#define CYREG_SCB0_EZ_DATA06 CYREG_SCB0_EZ_DATA6
#define CYREG_SCB0_EZ_DATA07 CYREG_SCB0_EZ_DATA7
#define CYREG_SCB0_EZ_DATA08 CYREG_SCB0_EZ_DATA8
#define CYREG_SCB0_EZ_DATA09 CYREG_SCB0_EZ_DATA9
#define CYREG_SCB0_EZ_DATA000 CYREG_SCB0_EZ_DATA0
#define CYREG_SCB0_EZ_DATA001 CYREG_SCB0_EZ_DATA1
#define CYREG_SCB0_EZ_DATA002 CYREG_SCB0_EZ_DATA2
#define CYREG_SCB0_EZ_DATA003 CYREG_SCB0_EZ_DATA3
#define CYREG_SCB0_EZ_DATA004 CYREG_SCB0_EZ_DATA4
#define CYREG_SCB0_EZ_DATA005 CYREG_SCB0_EZ_DATA5
#define CYREG_SCB0_EZ_DATA006 CYREG_SCB0_EZ_DATA6
#define CYREG_SCB0_EZ_DATA007 CYREG_SCB0_EZ_DATA7
#define CYREG_SCB0_EZ_DATA008 CYREG_SCB0_EZ_DATA8
#define CYREG_SCB0_EZ_DATA009 CYREG_SCB0_EZ_DATA9
#define CYREG_SCB0_EZ_DATA010 CYREG_SCB0_EZ_DATA10
#define CYREG_SCB0_EZ_DATA011 CYREG_SCB0_EZ_DATA11
#define CYREG_SCB0_EZ_DATA012 CYREG_SCB0_EZ_DATA12
#define CYREG_SCB0_EZ_DATA013 CYREG_SCB0_EZ_DATA13
#define CYREG_SCB0_EZ_DATA014 CYREG_SCB0_EZ_DATA14
#define CYREG_SCB0_EZ_DATA015 CYREG_SCB0_EZ_DATA15
#define CYREG_SCB0_EZ_DATA016 CYREG_SCB0_EZ_DATA16
#define CYREG_SCB0_EZ_DATA017 CYREG_SCB0_EZ_DATA17
#define CYREG_SCB0_EZ_DATA018 CYREG_SCB0_EZ_DATA18
#define CYREG_SCB0_EZ_DATA019 CYREG_SCB0_EZ_DATA19
#define CYREG_SCB0_EZ_DATA020 CYREG_SCB0_EZ_DATA20
#define CYREG_SCB0_EZ_DATA021 CYREG_SCB0_EZ_DATA21
#define CYREG_SCB0_EZ_DATA022 CYREG_SCB0_EZ_DATA22
#define CYREG_SCB0_EZ_DATA023 CYREG_SCB0_EZ_DATA23
#define CYREG_SCB0_EZ_DATA024 CYREG_SCB0_EZ_DATA24
#define CYREG_SCB0_EZ_DATA025 CYREG_SCB0_EZ_DATA25
#define CYREG_SCB0_EZ_DATA026 CYREG_SCB0_EZ_DATA26
#define CYREG_SCB0_EZ_DATA027 CYREG_SCB0_EZ_DATA27
#define CYREG_SCB0_EZ_DATA028 CYREG_SCB0_EZ_DATA28
#define CYREG_SCB0_EZ_DATA029 CYREG_SCB0_EZ_DATA29
#define CYREG_SCB0_EZ_DATA030 CYREG_SCB0_EZ_DATA30
#define CYREG_SCB0_EZ_DATA031 CYREG_SCB0_EZ_DATA31
#define CYREG_SCB1_EZ_DATA00 CYREG_SCB1_EZ_DATA0
#define CYREG_SCB1_EZ_DATA01 CYREG_SCB1_EZ_DATA1
#define CYREG_SCB1_EZ_DATA02 CYREG_SCB1_EZ_DATA2
#define CYREG_SCB1_EZ_DATA03 CYREG_SCB1_EZ_DATA3
#define CYREG_SCB1_EZ_DATA04 CYREG_SCB1_EZ_DATA4
#define CYREG_SCB1_EZ_DATA05 CYREG_SCB1_EZ_DATA5
#define CYREG_SCB1_EZ_DATA06 CYREG_SCB1_EZ_DATA6
#define CYREG_SCB1_EZ_DATA07 CYREG_SCB1_EZ_DATA7
#define CYREG_SCB1_EZ_DATA08 CYREG_SCB1_EZ_DATA8
#define CYREG_SCB1_EZ_DATA09 CYREG_SCB1_EZ_DATA9
#define CYREG_SCB1_EZ_DATA000 CYREG_SCB1_EZ_DATA0
#define CYREG_SCB1_EZ_DATA001 CYREG_SCB1_EZ_DATA1
#define CYREG_SCB1_EZ_DATA002 CYREG_SCB1_EZ_DATA2
#define CYREG_SCB1_EZ_DATA003 CYREG_SCB1_EZ_DATA3
#define CYREG_SCB1_EZ_DATA004 CYREG_SCB1_EZ_DATA4
#define CYREG_SCB1_EZ_DATA005 CYREG_SCB1_EZ_DATA5
#define CYREG_SCB1_EZ_DATA006 CYREG_SCB1_EZ_DATA6
#define CYREG_SCB1_EZ_DATA007 CYREG_SCB1_EZ_DATA7
#define CYREG_SCB1_EZ_DATA008 CYREG_SCB1_EZ_DATA8
#define CYREG_SCB1_EZ_DATA009 CYREG_SCB1_EZ_DATA9
#define CYREG_SCB1_EZ_DATA010 CYREG_SCB1_EZ_DATA10
#define CYREG_SCB1_EZ_DATA011 CYREG_SCB1_EZ_DATA11
#define CYREG_SCB1_EZ_DATA012 CYREG_SCB1_EZ_DATA12
#define CYREG_SCB1_EZ_DATA013 CYREG_SCB1_EZ_DATA13
#define CYREG_SCB1_EZ_DATA014 CYREG_SCB1_EZ_DATA14
#define CYREG_SCB1_EZ_DATA015 CYREG_SCB1_EZ_DATA15
#define CYREG_SCB1_EZ_DATA016 CYREG_SCB1_EZ_DATA16
#define CYREG_SCB1_EZ_DATA017 CYREG_SCB1_EZ_DATA17
#define CYREG_SCB1_EZ_DATA018 CYREG_SCB1_EZ_DATA18
#define CYREG_SCB1_EZ_DATA019 CYREG_SCB1_EZ_DATA19
#define CYREG_SCB1_EZ_DATA020 CYREG_SCB1_EZ_DATA20
#define CYREG_SCB1_EZ_DATA021 CYREG_SCB1_EZ_DATA21
#define CYREG_SCB1_EZ_DATA022 CYREG_SCB1_EZ_DATA22
#define CYREG_SCB1_EZ_DATA023 CYREG_SCB1_EZ_DATA23
#define CYREG_SCB1_EZ_DATA024 CYREG_SCB1_EZ_DATA24
#define CYREG_SCB1_EZ_DATA025 CYREG_SCB1_EZ_DATA25
#define CYREG_SCB1_EZ_DATA026 CYREG_SCB1_EZ_DATA26
#define CYREG_SCB1_EZ_DATA027 CYREG_SCB1_EZ_DATA27
#define CYREG_SCB1_EZ_DATA028 CYREG_SCB1_EZ_DATA28
#define CYREG_SCB1_EZ_DATA029 CYREG_SCB1_EZ_DATA29
#define CYREG_SCB1_EZ_DATA030 CYREG_SCB1_EZ_DATA30
#define CYREG_SCB1_EZ_DATA031 CYREG_SCB1_EZ_DATA31
#define CYREG_SCB2_EZ_DATA00 CYREG_SCB2_EZ_DATA0
#define CYREG_SCB2_EZ_DATA01 CYREG_SCB2_EZ_DATA1
#define CYREG_SCB2_EZ_DATA02 CYREG_SCB2_EZ_DATA2
#define CYREG_SCB2_EZ_DATA03 CYREG_SCB2_EZ_DATA3
#define CYREG_SCB2_EZ_DATA04 CYREG_SCB2_EZ_DATA4
#define CYREG_SCB2_EZ_DATA05 CYREG_SCB2_EZ_DATA5
#define CYREG_SCB2_EZ_DATA06 CYREG_SCB2_EZ_DATA6
#define CYREG_SCB2_EZ_DATA07 CYREG_SCB2_EZ_DATA7
#define CYREG_SCB2_EZ_DATA08 CYREG_SCB2_EZ_DATA8
#define CYREG_SCB2_EZ_DATA09 CYREG_SCB2_EZ_DATA9
#define CYREG_SCB2_EZ_DATA000 CYREG_SCB2_EZ_DATA0
#define CYREG_SCB2_EZ_DATA001 CYREG_SCB2_EZ_DATA1
#define CYREG_SCB2_EZ_DATA002 CYREG_SCB2_EZ_DATA2
#define CYREG_SCB2_EZ_DATA003 CYREG_SCB2_EZ_DATA3
#define CYREG_SCB2_EZ_DATA004 CYREG_SCB2_EZ_DATA4
#define CYREG_SCB2_EZ_DATA005 CYREG_SCB2_EZ_DATA5
#define CYREG_SCB2_EZ_DATA006 CYREG_SCB2_EZ_DATA6
#define CYREG_SCB2_EZ_DATA007 CYREG_SCB2_EZ_DATA7
#define CYREG_SCB2_EZ_DATA008 CYREG_SCB2_EZ_DATA8
#define CYREG_SCB2_EZ_DATA009 CYREG_SCB2_EZ_DATA9
#define CYREG_SCB2_EZ_DATA010 CYREG_SCB2_EZ_DATA10
#define CYREG_SCB2_EZ_DATA011 CYREG_SCB2_EZ_DATA11
#define CYREG_SCB2_EZ_DATA012 CYREG_SCB2_EZ_DATA12
#define CYREG_SCB2_EZ_DATA013 CYREG_SCB2_EZ_DATA13
#define CYREG_SCB2_EZ_DATA014 CYREG_SCB2_EZ_DATA14
#define CYREG_SCB2_EZ_DATA015 CYREG_SCB2_EZ_DATA15
#define CYREG_SCB2_EZ_DATA016 CYREG_SCB2_EZ_DATA16
#define CYREG_SCB2_EZ_DATA017 CYREG_SCB2_EZ_DATA17
#define CYREG_SCB2_EZ_DATA018 CYREG_SCB2_EZ_DATA18
#define CYREG_SCB2_EZ_DATA019 CYREG_SCB2_EZ_DATA19
#define CYREG_SCB2_EZ_DATA020 CYREG_SCB2_EZ_DATA20
#define CYREG_SCB2_EZ_DATA021 CYREG_SCB2_EZ_DATA21
#define CYREG_SCB2_EZ_DATA022 CYREG_SCB2_EZ_DATA22
#define CYREG_SCB2_EZ_DATA023 CYREG_SCB2_EZ_DATA23
#define CYREG_SCB2_EZ_DATA024 CYREG_SCB2_EZ_DATA24
#define CYREG_SCB2_EZ_DATA025 CYREG_SCB2_EZ_DATA25
#define CYREG_SCB2_EZ_DATA026 CYREG_SCB2_EZ_DATA26
#define CYREG_SCB2_EZ_DATA027 CYREG_SCB2_EZ_DATA27
#define CYREG_SCB2_EZ_DATA028 CYREG_SCB2_EZ_DATA28
#define CYREG_SCB2_EZ_DATA029 CYREG_SCB2_EZ_DATA29
#define CYREG_SCB2_EZ_DATA030 CYREG_SCB2_EZ_DATA30
#define CYREG_SCB2_EZ_DATA031 CYREG_SCB2_EZ_DATA31
#define CYREG_SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG0
#define CYREG_SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG1
#define CYREG_SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG2
#define CYREG_SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG3
#define CYREG_SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG4
#define CYREG_SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG5
#define CYREG_SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG6
#define CYREG_SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG7
#define CYREG_SAR_CHAN_CONFIG08 CYREG_SAR_CHAN_CONFIG8
#define CYREG_SAR_CHAN_CONFIG09 CYREG_SAR_CHAN_CONFIG9
#define CYREG_SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK0
#define CYREG_SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK1
#define CYREG_SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK2
#define CYREG_SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK3
#define CYREG_SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK4
#define CYREG_SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK5
#define CYREG_SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK6
#define CYREG_SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK7
#define CYREG_SAR_CHAN_WORK08 CYREG_SAR_CHAN_WORK8
#define CYREG_SAR_CHAN_WORK09 CYREG_SAR_CHAN_WORK9
#define CYREG_SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT0
#define CYREG_SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT1
#define CYREG_SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT2
#define CYREG_SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT3
#define CYREG_SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT4
#define CYREG_SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT5
#define CYREG_SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT6
#define CYREG_SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT7
#define CYREG_SAR_CHAN_RESULT08 CYREG_SAR_CHAN_RESULT8
#define CYREG_SAR_CHAN_RESULT09 CYREG_SAR_CHAN_RESULT9
#endif /* CYDEVICE_TRM_H */
