Loading plugins phase: Elapsed time ==> 1s.011ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -d CY8C4146LQI-S433 -s Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
ADD: sdb.M0065: information: Analog terminal "ADC_SAR_Seq_1.vinMinus0" on TopDesign is unconnected.
 * Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\TopDesign\TopDesign.cysch (Signal: Net_49)
 * Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\TopDesign\TopDesign.cysch (Shape_12.19)

ADD: sdb.M0061: information: Info from component: ADC_SAR_Seq_1. The actual sample rate (166666 SPS) differs from the desired sample rate (166664 SPS) due to the clock configuration in the DWR.
 * Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\TopDesign\TopDesign.cysch (Instance:ADC_SAR_Seq_1)

</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 39s.127ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.360ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  I2C.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 I2C.v -verilog
======================================================================

======================================================================
Compiling:  I2C.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 I2C.v -verilog
======================================================================

======================================================================
Compiling:  I2C.v
Program  :   vlogfe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 -verilog I2C.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Sun Apr 29 13:14:34 2018


======================================================================
Compiling:  I2C.v
Program  :   vpp
Options  :    -yv2 -q10 I2C.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Sun Apr 29 13:14:34 2018

Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80\AMux_v1_80.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.v'

vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'I2C.ctl'.

vlogfe:  No errors.


======================================================================
Compiling:  I2C.v
Program  :   tovif
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 -verilog I2C.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Sun Apr 29 13:14:35 2018

Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\codegentemp\I2C.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\codegentemp\I2C.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80\AMux_v1_80.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v'.

tovif:  No errors.


======================================================================
Compiling:  I2C.v
Program  :   topld
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 -verilog I2C.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Sun Apr 29 13:14:36 2018

Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\codegentemp\I2C.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\codegentemp\I2C.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80\AMux_v1_80.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	\I2C_1:Net_1257\
	\I2C_1:uncfg_rx_irq\
	\I2C_1:Net_1099\
	\I2C_1:Net_1258\
	Net_2
	Net_3
	Net_12
	Net_13
	Net_14
	Net_15
	Net_16
	Net_17
	Net_18
	\ADC_SAR_Seq_1:Net_3125\
	\ADC_SAR_Seq_1:Net_3126\


Deleted 15 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing \I2C_1:rx_wire\ to \I2C_1:select_s_wire\
Aliasing \I2C_1:sclk_s_wire\ to \I2C_1:select_s_wire\
Aliasing \I2C_1:mosi_s_wire\ to \I2C_1:select_s_wire\
Aliasing \I2C_1:miso_m_wire\ to \I2C_1:select_s_wire\
Aliasing zero to \I2C_1:select_s_wire\
Aliasing one to \I2C_1:tmpOE__sda_net_0\
Aliasing \I2C_1:tmpOE__scl_net_0\ to \I2C_1:tmpOE__sda_net_0\
Aliasing \I2C_1:cts_wire\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3107\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3106\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3105\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3104\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3103\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3207_1\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3207_0\ to \I2C_1:select_s_wire\
Aliasing \ADC_SAR_Seq_1:Net_3235\ to \I2C_1:select_s_wire\
Aliasing tmpOE__Pin_1_net_0 to \I2C_1:tmpOE__sda_net_0\
Aliasing \SmartIO_1:clock\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data0_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data1_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data2_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data3_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data4_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data5_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data6_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:data7_in\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_766\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_776\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_797\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_798\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_799\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_800\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:Net_801\ to \I2C_1:select_s_wire\
Aliasing \SmartIO_1:tmpOE__internalPin_i0_net_0\ to \I2C_1:tmpOE__sda_net_0\
Aliasing \SmartIO_1:tmpOE__internalPin_o7_net_0\ to \I2C_1:tmpOE__sda_net_0\
Aliasing tmpOE__Pin_2_net_0 to \I2C_1:tmpOE__sda_net_0\
Removing Lhs of wire \I2C_1:rx_wire\[3] = \I2C_1:select_s_wire\[2]
Removing Lhs of wire \I2C_1:Net_1170\[6] = \I2C_1:Net_847\[1]
Removing Lhs of wire \I2C_1:sclk_s_wire\[7] = \I2C_1:select_s_wire\[2]
Removing Lhs of wire \I2C_1:mosi_s_wire\[8] = \I2C_1:select_s_wire\[2]
Removing Lhs of wire \I2C_1:miso_m_wire\[9] = \I2C_1:select_s_wire\[2]
Removing Rhs of wire zero[12] = \I2C_1:select_s_wire\[2]
Removing Rhs of wire one[16] = \I2C_1:tmpOE__sda_net_0\[11]
Removing Lhs of wire \I2C_1:tmpOE__scl_net_0\[19] = one[16]
Removing Lhs of wire \I2C_1:cts_wire\[28] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3107\[126] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3106\[127] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3105\[128] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3104\[129] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3103\[130] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_17\[172] = \ADC_SAR_Seq_1:Net_1845\[57]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3207_1\[194] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3207_0\[195] = zero[12]
Removing Lhs of wire \ADC_SAR_Seq_1:Net_3235\[196] = zero[12]
Removing Lhs of wire tmpOE__Pin_1_net_0[266] = one[16]
Removing Lhs of wire \SmartIO_1:clock\[272] = zero[12]
Removing Lhs of wire \SmartIO_1:data0_in\[273] = zero[12]
Removing Lhs of wire \SmartIO_1:data1_in\[276] = zero[12]
Removing Lhs of wire \SmartIO_1:data2_in\[279] = zero[12]
Removing Lhs of wire \SmartIO_1:data3_in\[282] = zero[12]
Removing Lhs of wire \SmartIO_1:data4_in\[285] = zero[12]
Removing Lhs of wire \SmartIO_1:data5_in\[288] = zero[12]
Removing Lhs of wire \SmartIO_1:data6_in\[291] = zero[12]
Removing Lhs of wire \SmartIO_1:data7_in\[294] = zero[12]
Removing Rhs of wire \SmartIO_1:Net_654\[297] = \SmartIO_1:Net_761\[321]
Removing Lhs of wire \SmartIO_1:Net_766\[300] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_776\[303] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_797\[306] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_798\[309] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_799\[312] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_800\[315] = zero[12]
Removing Lhs of wire \SmartIO_1:Net_801\[318] = zero[12]
Removing Lhs of wire \SmartIO_1:tmpOE__internalPin_i0_net_0\[323] = one[16]
Removing Lhs of wire \SmartIO_1:tmpOE__internalPin_o7_net_0\[328] = one[16]
Removing Lhs of wire tmpOE__Pin_2_net_0[334] = one[16]

------------------------------------------------------
Aliased 0 equations, 39 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:


----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

topld:  No errors.

CYPRESS_DIR    : C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp
Warp Program   : C:\Program Files\Cypress\PSoC Creator\4.0\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -dcpsoc3 I2C.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 3s.244ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.0.0.432, Family: PSoC3, Started at: Sunday, 29 April 2018 13:14:36
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=Z:\TMP\PSoC4SProj\CQ4S01_Sample\I2C.cydsn\I2C.cyprj -d CY8C4146LQI-S433 I2C.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.110ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
    Fixed Function Clock 12: Automatic-assigning  clock 'ADC_SAR_Seq_1_intClock'. Signal=\ADC_SAR_Seq_1:Net_1845_ff12\
    Fixed Function Clock 0: Automatic-assigning  clock 'I2C_1_SCBCLK'. Signal=\I2C_1:Net_847_ff0\
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
</CYPRESSTAG>
ADD: pft.M0040: information: The following 2 pin(s) will be assigned a location by the fitter: Pin_1(0), Pin_2(0)


Removing unused cells resulting from optimization
Done removing unused cells.
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = \I2C_1:sda(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \I2C_1:sda(0)\__PA ,
            fb => \I2C_1:sda_wire\ ,
            pad => \I2C_1:sda(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \I2C_1:scl(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \I2C_1:scl(0)\__PA ,
            fb => \I2C_1:scl_wire\ ,
            pad => \I2C_1:scl(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = Pin_1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: False
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: ANALOG
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => Pin_1(0)__PA ,
            analog_term => Net_20 ,
            pad => Pin_1(0)_PAD );

    Pin : Name = \SmartIO_1:internalPin_i0(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \SmartIO_1:internalPin_i0(0)\__PA ,
            fb => \SmartIO_1:Net_654\ ,
            pad => \SmartIO_1:internalPin_i0(0)_PAD\ );

    Pin : Name = \SmartIO_1:internalPin_o7(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \SmartIO_1:internalPin_o7(0)\__PA ,
            input => Net_108 ,
            pad => \SmartIO_1:internalPin_o7(0)_PAD\ );

    Pin : Name = Pin_2(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: False
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilitites: ANALOG
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => Pin_2(0)__PA ,
            analog_term => Net_21 ,
            pad => Pin_2(0)_PAD );
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">

    ------------------------------------------------------------
    Interrupt listing
    ------------------------------------------------------------

    interrupt: Name =\I2C_1:SCB_IRQ\
        PORT MAP (
            interrupt => Net_4 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\ADC_SAR_Seq_1:IRQ\
        PORT MAP (
            interrupt => \ADC_SAR_Seq_1:Net_3112\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Interrupts                    :    2 :   18 :   20 : 10.00 %
IO                            :    8 :   26 :   34 : 23.53 %
Segment LCD                   :    0 :    1 :    1 :  0.00 %
CapSense                      :    0 :    1 :    1 :  0.00 %
Die Temp                      :    0 :    1 :    1 :  0.00 %
Serial Communication (SCB)    :    1 :    2 :    3 : 33.33 %
Timer/Counter/PWM             :    0 :    5 :    5 :  0.00 %
Smart IO Ports                :    1 :    1 :    2 : 50.00 %
Comparator/Opamp              :    0 :    2 :    2 :  0.00 %
Comparator                    :    0 :    1 :    1 :  0.00 %
LP Comparator                 :    0 :    2 :    2 :  0.00 %
SAR ADC                       :    1 :    0 :    1 : 100.00 %
DAC                           :      :      :      :        
  7-bit IDAC                  :    0 :    2 :    2 :  0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.210ms
Tech Mapping phase: Elapsed time ==> 0s.610ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
<CYPRESSTAG name="Analog Placement">
Elapsed time ==> 0.4676524s
</CYPRESSTAG>
Analog Placement phase: Elapsed time ==> 1s.181ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
<CYPRESSTAG name="Analog Routing">
Route success=True, Iterations=1 Elapsed=0.0448015 secs
</CYPRESSTAG>
Analog Routing phase: Elapsed time ==> 0s.050ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
  Net: Net_20 {
    p2_4
  }
  Net: Net_21 {
    p2_5
  }
  Net: \ADC_SAR_Seq_1:Net_3113\ {
  }
  Net: \ADC_SAR_Seq_1:mux_bus_minus_1\ {
  }
  Net: \ADC_SAR_Seq_1:mux_bus_plus_1\ {
  }
  Net: Net_52 {
    PASS0_sarmux_vplus
  }
  Net: AMuxNet::AMux_1 {
    PASS0_SARMUX0_sw4
    PASS0_SARMUX0_sw5
  }
}
Map of item to net {
  p2_4                                             -> Net_20
  p2_5                                             -> Net_21
  PASS0_sarmux_vplus                               -> Net_52
  PASS0_SARMUX0_sw4                                -> AMuxNet::AMux_1
  PASS0_SARMUX0_sw5                                -> AMuxNet::AMux_1
}
Mux Info {
  Mux: AMux_1 {
     Mouth: Net_52
     Guts:  AMuxNet::AMux_1
     IsSingleSwitching: True
     IsStaticSwitching: False
     IsAtMostOneSwitch: False
    Arm: 0 {
      Net:   Net_20
      Outer: PASS0_SARMUX0_sw4
      Inner: __open__
      Path {
        PASS0_SARMUX0_sw4
        p2_4
      }
    }
    Arm: 1 {
      Net:   Net_21
      Outer: PASS0_SARMUX0_sw5
      Inner: __open__
      Path {
        PASS0_SARMUX0_sw5
        p2_5
      }
    }
  }
}
Analog Code Generation phase: Elapsed time ==> 0s.320ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2076: Total run-time: 0.4 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary">
No PLDs were packed.
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.030ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.180ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          0 :       0.00 :       0.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
Intr container @ [IntrContainer=(0)]: 
  Intr@ [IntrContainer=(0)][IntrId=(8)] 
    interrupt: Name =\I2C_1:SCB_IRQ\
        PORT MAP (
            interrupt => Net_4 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(19)] 
    interrupt: Name =\ADC_SAR_Seq_1:IRQ\
        PORT MAP (
            interrupt => \ADC_SAR_Seq_1:Net_3112\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
Port 0 contains the following IO cells:
[IoId=4]: 
Pin : Name = \I2C_1:scl(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \I2C_1:scl(0)\__PA ,
        fb => \I2C_1:scl_wire\ ,
        pad => \I2C_1:scl(0)_PAD\ );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = \I2C_1:sda(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \I2C_1:sda(0)\__PA ,
        fb => \I2C_1:sda_wire\ ,
        pad => \I2C_1:sda(0)_PAD\ );
    Properties:
    {
    }

Port 1 is empty
Port 2 contains the following IO cells:
[IoId=0]: 
Pin : Name = \SmartIO_1:internalPin_i0(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \SmartIO_1:internalPin_i0(0)\__PA ,
        fb => \SmartIO_1:Net_654\ ,
        pad => \SmartIO_1:internalPin_i0(0)_PAD\ );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = Pin_1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: False
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: ANALOG
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => Pin_1(0)__PA ,
        analog_term => Net_20 ,
        pad => Pin_1(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = Pin_2(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: False
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: ANALOG
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => Pin_2(0)__PA ,
        analog_term => Net_21 ,
        pad => Pin_2(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = \SmartIO_1:internalPin_o7(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \SmartIO_1:internalPin_o7(0)\__PA ,
        input => Net_108 ,
        pad => \SmartIO_1:internalPin_o7(0)_PAD\ );
    Properties:
    {
    }

Port 3 is empty
Port 4 is empty
Clock group 0: 
    Clock Block @ F(Clock,0): 
    m0s8clockblockcell: Name =ClockBlock
        PORT MAP (
            hfclk => ClockBlock_HFCLK ,
            imo => ClockBlock_IMO ,
            ext => ClockBlock_EXTCLK ,
            sysclk => ClockBlock_SYSCLK ,
            ilo => ClockBlock_ILO ,
            lfclk => ClockBlock_LFCLK ,
            wco => ClockBlock_WCO ,
            ff_div_12 => \ADC_SAR_Seq_1:Net_1845_ff12\ ,
            ff_div_0 => \I2C_1:Net_847_ff0\ );
        Properties:
        {
        }
SPC group 0: empty
Vref group 0: empty
WDT group 0: empty
LP Comparator group 0: empty
Serial Communication (SCB) group 0: 
    SCB Block @ F(SCB,1): 
    m0s8scbcell: Name =\I2C_1:SCB\
        PORT MAP (
            clock => \I2C_1:Net_847_ff0\ ,
            interrupt => Net_4 ,
            tx => \I2C_1:tx_wire\ ,
            rts => \I2C_1:rts_wire\ ,
            mosi_m => \I2C_1:mosi_m_wire\ ,
            select_m_3 => \I2C_1:select_m_wire_3\ ,
            select_m_2 => \I2C_1:select_m_wire_2\ ,
            select_m_1 => \I2C_1:select_m_wire_1\ ,
            select_m_0 => \I2C_1:select_m_wire_0\ ,
            sclk_m => \I2C_1:sclk_m_wire\ ,
            miso_s => \I2C_1:miso_s_wire\ ,
            scl => \I2C_1:scl_wire\ ,
            sda => \I2C_1:sda_wire\ ,
            tx_req => Net_7 ,
            rx_req => Net_6 );
        Properties:
        {
            cy_registers = ""
            scb_mode = 0
        }
CapSense group 0: empty
7-bit IDAC group 0: empty
Timer/Counter/PWM group 0: empty
Comparator/Opamp group 0: empty
Die Temp group 0: empty
SAR ADC group 0: 
    PSoC4 SAR ADC @ F(SARADC,0): 
    p4sarcell: Name =\ADC_SAR_Seq_1:cy_psoc4_sar\
        PORT MAP (
            vplus => Net_52 ,
            vminus => Net_49 ,
            vref => \ADC_SAR_Seq_1:Net_3113\ ,
            ext_vref => \ADC_SAR_Seq_1:Net_3225\ ,
            clock => \ADC_SAR_Seq_1:Net_1845_ff12\ ,
            sample_done => Net_40 ,
            chan_id_valid => \ADC_SAR_Seq_1:Net_3108\ ,
            chan_id_3 => \ADC_SAR_Seq_1:Net_3109_3\ ,
            chan_id_2 => \ADC_SAR_Seq_1:Net_3109_2\ ,
            chan_id_1 => \ADC_SAR_Seq_1:Net_3109_1\ ,
            chan_id_0 => \ADC_SAR_Seq_1:Net_3109_0\ ,
            data_valid => \ADC_SAR_Seq_1:Net_3110\ ,
            data_11 => \ADC_SAR_Seq_1:Net_3111_11\ ,
            data_10 => \ADC_SAR_Seq_1:Net_3111_10\ ,
            data_9 => \ADC_SAR_Seq_1:Net_3111_9\ ,
            data_8 => \ADC_SAR_Seq_1:Net_3111_8\ ,
            data_7 => \ADC_SAR_Seq_1:Net_3111_7\ ,
            data_6 => \ADC_SAR_Seq_1:Net_3111_6\ ,
            data_5 => \ADC_SAR_Seq_1:Net_3111_5\ ,
            data_4 => \ADC_SAR_Seq_1:Net_3111_4\ ,
            data_3 => \ADC_SAR_Seq_1:Net_3111_3\ ,
            data_2 => \ADC_SAR_Seq_1:Net_3111_2\ ,
            data_1 => \ADC_SAR_Seq_1:Net_3111_1\ ,
            data_0 => \ADC_SAR_Seq_1:Net_3111_0\ ,
            tr_sar_out => Net_41 ,
            irq => \ADC_SAR_Seq_1:Net_3112\ );
        Properties:
        {
            cy_registers = ""
        }
Segment LCD group 0: empty
CLK_GEN group 0: 
    M0S8 Clock Gen Block @ F(CLK_GEN,0): 
    m0s8clockgenblockcell: Name =ClockGenBlock
        PORT MAP (
             );
        Properties:
        {
        }
LPCOMPBLOCK group 0: empty
PASSBLOCK group 0: empty
GANGED_PICU group 0: empty
WCO group 0: empty
Smart IO Ports group 0: 
    PSoC4 Smart IO Ports @ F(SmartIO,2): 
    p4smartiocell: Name =\SmartIO_1:cy_m0s8_prgio\
        PORT MAP (
            gpio0_i => \SmartIO_1:Net_654\ ,
            gpio7_o => Net_108 );
        Properties:
        {
            cy_registers = ""
            port_id = 2
        }

Blocks not positioned by the digital component placer:
    Amux Block @ <No Location>: 
    amuxcell: Name =AMux_1
        PORT MAP (
            muxin_1 => Net_21 ,
            muxin_0 => Net_20 ,
            vout => Net_52 );
        Properties:
        {
            api_type = 0
            connect_mode = 1
            cy_registers = ""
            hw_control = 0
            init_mux_sel = "00"
            muxin_width = 2
            one_active = 0
        }
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |                               | 
Port | Pin | Fixed |      Type |       Drive Mode |                          Name | Connections
-----+-----+-------+-----------+------------------+-------------------------------+------------------------
   0 |   4 |     * |      NONE |    OPEN_DRAIN_LO |                \I2C_1:scl(0)\ | FB(\I2C_1:scl_wire\)
     |   5 |     * |      NONE |    OPEN_DRAIN_LO |                \I2C_1:sda(0)\ | FB(\I2C_1:sda_wire\)
-----+-----+-------+-----------+------------------+-------------------------------+------------------------
   2 |   0 |     * |      NONE |      HI_Z_ANALOG | \SmartIO_1:internalPin_i0(0)\ | FB(\SmartIO_1:Net_654\)
     |   4 |       |      NONE |      HI_Z_ANALOG |                      Pin_1(0) | Analog(Net_20)
     |   5 |       |      NONE |      HI_Z_ANALOG |                      Pin_2(0) | Analog(Net_21)
     |   7 |     * |      NONE |      HI_Z_ANALOG | \SmartIO_1:internalPin_o7(0)\ | In(Net_108)
-----------------------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.000ms
Digital Placement phase: Elapsed time ==> 1s.962ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
Info: pft.M0077: There is no timing information available for the selected device. Static timing checks will not be applied and digital routing will not be timing-driven. (App=cydsfit)
Routing successful.
Digital Routing phase: Elapsed time ==> 0s.680ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 1s.652ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.090ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
No timing parameter file available for CY8C4146LQI-S433
Static timing analysis phase: Elapsed time ==> 0s.020ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.630ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 7s.621ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 7s.731ms
API generation phase: Elapsed time ==> 9s.924ms
Dependency generation phase: Elapsed time ==> 0s.380ms
Cleanup phase: Elapsed time ==> 0s.050ms
