#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* WDT_Interrupt */
#define WDT_Interrupt__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define WDT_Interrupt__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define WDT_Interrupt__INTC_MASK 0x40u
#define WDT_Interrupt__INTC_NUMBER 6u
#define WDT_Interrupt__INTC_PRIOR_MASK 0xC00000u
#define WDT_Interrupt__INTC_PRIOR_NUM 3u
#define WDT_Interrupt__INTC_PRIOR_REG CYREG_CM0P_IPR1
#define WDT_Interrupt__INTC_SET_EN_REG CYREG_CM0P_ISER
#define WDT_Interrupt__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* EZI2C_SCB */
#define EZI2C_SCB__CTRL CYREG_SCB2_CTRL
#define EZI2C_SCB__EZ_DATA0 CYREG_SCB2_EZ_DATA0
#define EZI2C_SCB__EZ_DATA1 CYREG_SCB2_EZ_DATA1
#define EZI2C_SCB__EZ_DATA10 CYREG_SCB2_EZ_DATA10
#define EZI2C_SCB__EZ_DATA11 CYREG_SCB2_EZ_DATA11
#define EZI2C_SCB__EZ_DATA12 CYREG_SCB2_EZ_DATA12
#define EZI2C_SCB__EZ_DATA13 CYREG_SCB2_EZ_DATA13
#define EZI2C_SCB__EZ_DATA14 CYREG_SCB2_EZ_DATA14
#define EZI2C_SCB__EZ_DATA15 CYREG_SCB2_EZ_DATA15
#define EZI2C_SCB__EZ_DATA16 CYREG_SCB2_EZ_DATA16
#define EZI2C_SCB__EZ_DATA17 CYREG_SCB2_EZ_DATA17
#define EZI2C_SCB__EZ_DATA18 CYREG_SCB2_EZ_DATA18
#define EZI2C_SCB__EZ_DATA19 CYREG_SCB2_EZ_DATA19
#define EZI2C_SCB__EZ_DATA2 CYREG_SCB2_EZ_DATA2
#define EZI2C_SCB__EZ_DATA20 CYREG_SCB2_EZ_DATA20
#define EZI2C_SCB__EZ_DATA21 CYREG_SCB2_EZ_DATA21
#define EZI2C_SCB__EZ_DATA22 CYREG_SCB2_EZ_DATA22
#define EZI2C_SCB__EZ_DATA23 CYREG_SCB2_EZ_DATA23
#define EZI2C_SCB__EZ_DATA24 CYREG_SCB2_EZ_DATA24
#define EZI2C_SCB__EZ_DATA25 CYREG_SCB2_EZ_DATA25
#define EZI2C_SCB__EZ_DATA26 CYREG_SCB2_EZ_DATA26
#define EZI2C_SCB__EZ_DATA27 CYREG_SCB2_EZ_DATA27
#define EZI2C_SCB__EZ_DATA28 CYREG_SCB2_EZ_DATA28
#define EZI2C_SCB__EZ_DATA29 CYREG_SCB2_EZ_DATA29
#define EZI2C_SCB__EZ_DATA3 CYREG_SCB2_EZ_DATA3
#define EZI2C_SCB__EZ_DATA30 CYREG_SCB2_EZ_DATA30
#define EZI2C_SCB__EZ_DATA31 CYREG_SCB2_EZ_DATA31
#define EZI2C_SCB__EZ_DATA4 CYREG_SCB2_EZ_DATA4
#define EZI2C_SCB__EZ_DATA5 CYREG_SCB2_EZ_DATA5
#define EZI2C_SCB__EZ_DATA6 CYREG_SCB2_EZ_DATA6
#define EZI2C_SCB__EZ_DATA7 CYREG_SCB2_EZ_DATA7
#define EZI2C_SCB__EZ_DATA8 CYREG_SCB2_EZ_DATA8
#define EZI2C_SCB__EZ_DATA9 CYREG_SCB2_EZ_DATA9
#define EZI2C_SCB__I2C_CFG CYREG_SCB2_I2C_CFG
#define EZI2C_SCB__I2C_CTRL CYREG_SCB2_I2C_CTRL
#define EZI2C_SCB__I2C_M_CMD CYREG_SCB2_I2C_M_CMD
#define EZI2C_SCB__I2C_S_CMD CYREG_SCB2_I2C_S_CMD
#define EZI2C_SCB__I2C_STATUS CYREG_SCB2_I2C_STATUS
#define EZI2C_SCB__INTR_CAUSE CYREG_SCB2_INTR_CAUSE
#define EZI2C_SCB__INTR_I2C_EC CYREG_SCB2_INTR_I2C_EC
#define EZI2C_SCB__INTR_I2C_EC_MASK CYREG_SCB2_INTR_I2C_EC_MASK
#define EZI2C_SCB__INTR_I2C_EC_MASKED CYREG_SCB2_INTR_I2C_EC_MASKED
#define EZI2C_SCB__INTR_M CYREG_SCB2_INTR_M
#define EZI2C_SCB__INTR_M_MASK CYREG_SCB2_INTR_M_MASK
#define EZI2C_SCB__INTR_M_MASKED CYREG_SCB2_INTR_M_MASKED
#define EZI2C_SCB__INTR_M_SET CYREG_SCB2_INTR_M_SET
#define EZI2C_SCB__INTR_RX CYREG_SCB2_INTR_RX
#define EZI2C_SCB__INTR_RX_MASK CYREG_SCB2_INTR_RX_MASK
#define EZI2C_SCB__INTR_RX_MASKED CYREG_SCB2_INTR_RX_MASKED
#define EZI2C_SCB__INTR_RX_SET CYREG_SCB2_INTR_RX_SET
#define EZI2C_SCB__INTR_S CYREG_SCB2_INTR_S
#define EZI2C_SCB__INTR_S_MASK CYREG_SCB2_INTR_S_MASK
#define EZI2C_SCB__INTR_S_MASKED CYREG_SCB2_INTR_S_MASKED
#define EZI2C_SCB__INTR_S_SET CYREG_SCB2_INTR_S_SET
#define EZI2C_SCB__INTR_SPI_EC CYREG_SCB2_INTR_SPI_EC
#define EZI2C_SCB__INTR_SPI_EC_MASK CYREG_SCB2_INTR_SPI_EC_MASK
#define EZI2C_SCB__INTR_SPI_EC_MASKED CYREG_SCB2_INTR_SPI_EC_MASKED
#define EZI2C_SCB__INTR_TX CYREG_SCB2_INTR_TX
#define EZI2C_SCB__INTR_TX_MASK CYREG_SCB2_INTR_TX_MASK
#define EZI2C_SCB__INTR_TX_MASKED CYREG_SCB2_INTR_TX_MASKED
#define EZI2C_SCB__INTR_TX_SET CYREG_SCB2_INTR_TX_SET
#define EZI2C_SCB__RX_CTRL CYREG_SCB2_RX_CTRL
#define EZI2C_SCB__RX_FIFO_CTRL CYREG_SCB2_RX_FIFO_CTRL
#define EZI2C_SCB__RX_FIFO_RD CYREG_SCB2_RX_FIFO_RD
#define EZI2C_SCB__RX_FIFO_RD_SILENT CYREG_SCB2_RX_FIFO_RD_SILENT
#define EZI2C_SCB__RX_FIFO_STATUS CYREG_SCB2_RX_FIFO_STATUS
#define EZI2C_SCB__RX_MATCH CYREG_SCB2_RX_MATCH
#define EZI2C_SCB__SPI_CTRL CYREG_SCB2_SPI_CTRL
#define EZI2C_SCB__SPI_STATUS CYREG_SCB2_SPI_STATUS
#define EZI2C_SCB__SS0_POSISTION 0u
#define EZI2C_SCB__SS1_POSISTION 1u
#define EZI2C_SCB__SS2_POSISTION 2u
#define EZI2C_SCB__SS3_POSISTION 3u
#define EZI2C_SCB__STATUS CYREG_SCB2_STATUS
#define EZI2C_SCB__TX_CTRL CYREG_SCB2_TX_CTRL
#define EZI2C_SCB__TX_FIFO_CTRL CYREG_SCB2_TX_FIFO_CTRL
#define EZI2C_SCB__TX_FIFO_STATUS CYREG_SCB2_TX_FIFO_STATUS
#define EZI2C_SCB__TX_FIFO_WR CYREG_SCB2_TX_FIFO_WR
#define EZI2C_SCB__UART_CTRL CYREG_SCB2_UART_CTRL
#define EZI2C_SCB__UART_FLOW_CTRL CYREG_SCB2_UART_FLOW_CTRL
#define EZI2C_SCB__UART_RX_CTRL CYREG_SCB2_UART_RX_CTRL
#define EZI2C_SCB__UART_RX_STATUS CYREG_SCB2_UART_RX_STATUS
#define EZI2C_SCB__UART_TX_CTRL CYREG_SCB2_UART_TX_CTRL

/* EZI2C_SCB_IRQ */
#define EZI2C_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define EZI2C_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define EZI2C_SCB_IRQ__INTC_MASK 0x200u
#define EZI2C_SCB_IRQ__INTC_NUMBER 9u
#define EZI2C_SCB_IRQ__INTC_PRIOR_MASK 0xC000u
#define EZI2C_SCB_IRQ__INTC_PRIOR_NUM 3u
#define EZI2C_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR2
#define EZI2C_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER
#define EZI2C_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* EZI2C_SCBCLK */
#define EZI2C_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL2
#define EZI2C_SCBCLK__DIV_ID 0x00000041u
#define EZI2C_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define EZI2C_SCBCLK__PA_DIV_ID 0x000000FFu

/* EZI2C_scl */
#define EZI2C_scl__0__DR CYREG_GPIO_PRT1_DR
#define EZI2C_scl__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define EZI2C_scl__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define EZI2C_scl__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define EZI2C_scl__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define EZI2C_scl__0__HSIOM_GPIO 0u
#define EZI2C_scl__0__HSIOM_I2C 14u
#define EZI2C_scl__0__HSIOM_I2C_SCL 14u
#define EZI2C_scl__0__HSIOM_MASK 0x00000F00u
#define EZI2C_scl__0__HSIOM_SHIFT 8u
#define EZI2C_scl__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_scl__0__INTR CYREG_GPIO_PRT1_INTR
#define EZI2C_scl__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_scl__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define EZI2C_scl__0__MASK 0x04u
#define EZI2C_scl__0__PC CYREG_GPIO_PRT1_PC
#define EZI2C_scl__0__PC2 CYREG_GPIO_PRT1_PC2
#define EZI2C_scl__0__PORT 1u
#define EZI2C_scl__0__PS CYREG_GPIO_PRT1_PS
#define EZI2C_scl__0__SHIFT 2u
#define EZI2C_scl__DR CYREG_GPIO_PRT1_DR
#define EZI2C_scl__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define EZI2C_scl__DR_INV CYREG_GPIO_PRT1_DR_INV
#define EZI2C_scl__DR_SET CYREG_GPIO_PRT1_DR_SET
#define EZI2C_scl__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_scl__INTR CYREG_GPIO_PRT1_INTR
#define EZI2C_scl__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_scl__INTSTAT CYREG_GPIO_PRT1_INTR
#define EZI2C_scl__MASK 0x04u
#define EZI2C_scl__PC CYREG_GPIO_PRT1_PC
#define EZI2C_scl__PC2 CYREG_GPIO_PRT1_PC2
#define EZI2C_scl__PORT 1u
#define EZI2C_scl__PS CYREG_GPIO_PRT1_PS
#define EZI2C_scl__SHIFT 2u

/* EZI2C_sda */
#define EZI2C_sda__0__DR CYREG_GPIO_PRT1_DR
#define EZI2C_sda__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define EZI2C_sda__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define EZI2C_sda__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define EZI2C_sda__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define EZI2C_sda__0__HSIOM_GPIO 0u
#define EZI2C_sda__0__HSIOM_I2C 14u
#define EZI2C_sda__0__HSIOM_I2C_SDA 14u
#define EZI2C_sda__0__HSIOM_MASK 0x0000F000u
#define EZI2C_sda__0__HSIOM_SHIFT 12u
#define EZI2C_sda__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_sda__0__INTR CYREG_GPIO_PRT1_INTR
#define EZI2C_sda__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_sda__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define EZI2C_sda__0__MASK 0x08u
#define EZI2C_sda__0__PC CYREG_GPIO_PRT1_PC
#define EZI2C_sda__0__PC2 CYREG_GPIO_PRT1_PC2
#define EZI2C_sda__0__PORT 1u
#define EZI2C_sda__0__PS CYREG_GPIO_PRT1_PS
#define EZI2C_sda__0__SHIFT 3u
#define EZI2C_sda__DR CYREG_GPIO_PRT1_DR
#define EZI2C_sda__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define EZI2C_sda__DR_INV CYREG_GPIO_PRT1_DR_INV
#define EZI2C_sda__DR_SET CYREG_GPIO_PRT1_DR_SET
#define EZI2C_sda__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_sda__INTR CYREG_GPIO_PRT1_INTR
#define EZI2C_sda__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define EZI2C_sda__INTSTAT CYREG_GPIO_PRT1_INTR
#define EZI2C_sda__MASK 0x08u
#define EZI2C_sda__PC CYREG_GPIO_PRT1_PC
#define EZI2C_sda__PC2 CYREG_GPIO_PRT1_PC2
#define EZI2C_sda__PORT 1u
#define EZI2C_sda__PS CYREG_GPIO_PRT1_PS
#define EZI2C_sda__SHIFT 3u

/* Pin_LED */
#define Pin_LED__0__DR CYREG_GPIO_PRT0_DR
#define Pin_LED__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Pin_LED__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Pin_LED__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Pin_LED__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define Pin_LED__0__HSIOM_MASK 0x0000F000u
#define Pin_LED__0__HSIOM_SHIFT 12u
#define Pin_LED__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Pin_LED__0__INTR CYREG_GPIO_PRT0_INTR
#define Pin_LED__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Pin_LED__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define Pin_LED__0__MASK 0x08u
#define Pin_LED__0__PC CYREG_GPIO_PRT0_PC
#define Pin_LED__0__PC2 CYREG_GPIO_PRT0_PC2
#define Pin_LED__0__PORT 0u
#define Pin_LED__0__PS CYREG_GPIO_PRT0_PS
#define Pin_LED__0__SHIFT 3u
#define Pin_LED__DR CYREG_GPIO_PRT0_DR
#define Pin_LED__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Pin_LED__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Pin_LED__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Pin_LED__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Pin_LED__INTR CYREG_GPIO_PRT0_INTR
#define Pin_LED__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Pin_LED__INTSTAT CYREG_GPIO_PRT0_INTR
#define Pin_LED__MASK 0x08u
#define Pin_LED__PC CYREG_GPIO_PRT0_PC
#define Pin_LED__PC2 CYREG_GPIO_PRT0_PC2
#define Pin_LED__PORT 0u
#define Pin_LED__PS CYREG_GPIO_PRT0_PS
#define Pin_LED__SHIFT 3u

/* CapSense_Cmod */
#define CapSense_Cmod__0__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define CapSense_Cmod__0__HSIOM_MASK 0x000000F0u
#define CapSense_Cmod__0__HSIOM_SHIFT 4u
#define CapSense_Cmod__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__0__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__0__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__0__MASK 0x02u
#define CapSense_Cmod__0__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__0__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__0__PORT 4u
#define CapSense_Cmod__0__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__0__SHIFT 1u
#define CapSense_Cmod__Cmod__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__Cmod__MASK 0x02u
#define CapSense_Cmod__Cmod__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__Cmod__PORT 4u
#define CapSense_Cmod__Cmod__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__Cmod__SHIFT 1u
#define CapSense_Cmod__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__MASK 0x02u
#define CapSense_Cmod__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__PORT 4u
#define CapSense_Cmod__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__SHIFT 1u

/* CapSense_CSD */
#define CapSense_CSD__ADC_CTL CYREG_CSD_ADC_CTL
#define CapSense_CSD__CMOD_PAD 1u
#define CapSense_CSD__CSD_CONFIG CYREG_CSD_CONFIG
#define CapSense_CSD__CSD_INTR CYREG_CSD_INTR
#define CapSense_CSD__CSD_INTR_SET CYREG_CSD_INTR_SET
#define CapSense_CSD__CSD_NUMBER 0u
#define CapSense_CSD__CSD_STATUS CYREG_CSD_STATUS
#define CapSense_CSD__CSDCMP CYREG_CSD_CSDCMP
#define CapSense_CSD__CSH_TANK_PAD 2u
#define CapSense_CSD__CSHIELD_PAD 4u
#define CapSense_CSD__DEDICATED_IO CapSense_CSD__CSHIELD_PAD
#define CapSense_CSD__HSCMP CYREG_CSD_HSCMP
#define CapSense_CSD__INTR_MASK CYREG_CSD_INTR_MASK
#define CapSense_CSD__REFGEN CYREG_CSD_REFGEN
#define CapSense_CSD__RESULT_VAL1 CYREG_CSD_RESULT_VAL1
#define CapSense_CSD__RESULT_VAL2 CYREG_CSD_RESULT_VAL2
#define CapSense_CSD__SENSE_DUTY CYREG_CSD_SENSE_DUTY
#define CapSense_CSD__SENSE_PERIOD CYREG_CSD_SENSE_PERIOD
#define CapSense_CSD__SEQ_INIT_CNT CYREG_CSD_SEQ_INIT_CNT
#define CapSense_CSD__SEQ_NORM_CNT CYREG_CSD_SEQ_NORM_CNT
#define CapSense_CSD__SEQ_START CYREG_CSD_SEQ_START
#define CapSense_CSD__SEQ_TIME CYREG_CSD_SEQ_TIME
#define CapSense_CSD__SW_AMUXBUF_SEL CYREG_CSD_SW_AMUXBUF_SEL
#define CapSense_CSD__SW_BYP_SEL CYREG_CSD_SW_BYP_SEL
#define CapSense_CSD__SW_CMP_N_SEL CYREG_CSD_SW_CMP_N_SEL
#define CapSense_CSD__SW_CMP_P_SEL CYREG_CSD_SW_CMP_P_SEL
#define CapSense_CSD__SW_DSI_SEL CYREG_CSD_SW_DSI_SEL
#define CapSense_CSD__SW_FW_MOD_SEL CYREG_CSD_SW_FW_MOD_SEL
#define CapSense_CSD__SW_FW_TANK_SEL CYREG_CSD_SW_FW_TANK_SEL
#define CapSense_CSD__SW_HS_N_SEL CYREG_CSD_SW_HS_N_SEL
#define CapSense_CSD__SW_HS_P_SEL CYREG_CSD_SW_HS_P_SEL
#define CapSense_CSD__SW_REFGEN_SEL CYREG_CSD_SW_REFGEN_SEL
#define CapSense_CSD__SW_RES CYREG_CSD_SW_RES
#define CapSense_CSD__SW_SHIELD_SEL CYREG_CSD_SW_SHIELD_SEL

/* CapSense_IDACComp */
#define CapSense_IDACComp__CONFIG CYREG_CSD_CONFIG
#define CapSense_IDACComp__IDAC CYREG_CSD_IDACB
#define CapSense_IDACComp__POSITION 1u

/* CapSense_IDACMod */
#define CapSense_IDACMod__CONFIG CYREG_CSD_CONFIG
#define CapSense_IDACMod__IDAC CYREG_CSD_IDACA
#define CapSense_IDACMod__POSITION 0u

/* CapSense_ISR */
#define CapSense_ISR__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define CapSense_ISR__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define CapSense_ISR__INTC_MASK 0x2000u
#define CapSense_ISR__INTC_NUMBER 13u
#define CapSense_ISR__INTC_PRIOR_MASK 0xC000u
#define CapSense_ISR__INTC_PRIOR_NUM 3u
#define CapSense_ISR__INTC_PRIOR_REG CYREG_CM0P_IPR3
#define CapSense_ISR__INTC_SET_EN_REG CYREG_CM0P_ISER
#define CapSense_ISR__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* CapSense_ModClk */
#define CapSense_ModClk__CTRL_REGISTER CYREG_PERI_PCLK_CTL3
#define CapSense_ModClk__DIV_ID 0x00000040u
#define CapSense_ModClk__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define CapSense_ModClk__PA_DIV_ID 0x000000FFu

/* CapSense_Sns */
#define CapSense_Sns__0__DR CYREG_GPIO_PRT0_DR
#define CapSense_Sns__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define CapSense_Sns__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define CapSense_Sns__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define CapSense_Sns__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define CapSense_Sns__0__HSIOM_MASK 0x000000F0u
#define CapSense_Sns__0__HSIOM_SHIFT 4u
#define CapSense_Sns__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__0__INTR CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__0__MASK 0x02u
#define CapSense_Sns__0__PC CYREG_GPIO_PRT0_PC
#define CapSense_Sns__0__PC2 CYREG_GPIO_PRT0_PC2
#define CapSense_Sns__0__PORT 0u
#define CapSense_Sns__0__PS CYREG_GPIO_PRT0_PS
#define CapSense_Sns__0__SHIFT 1u
#define CapSense_Sns__Button0_Sns0__DR CYREG_GPIO_PRT0_DR
#define CapSense_Sns__Button0_Sns0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define CapSense_Sns__Button0_Sns0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define CapSense_Sns__Button0_Sns0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define CapSense_Sns__Button0_Sns0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__Button0_Sns0__INTR CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__Button0_Sns0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__Button0_Sns0__INTSTAT CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__Button0_Sns0__MASK 0x02u
#define CapSense_Sns__Button0_Sns0__PC CYREG_GPIO_PRT0_PC
#define CapSense_Sns__Button0_Sns0__PC2 CYREG_GPIO_PRT0_PC2
#define CapSense_Sns__Button0_Sns0__PORT 0u
#define CapSense_Sns__Button0_Sns0__PS CYREG_GPIO_PRT0_PS
#define CapSense_Sns__Button0_Sns0__SHIFT 1u
#define CapSense_Sns__DR CYREG_GPIO_PRT0_DR
#define CapSense_Sns__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define CapSense_Sns__DR_INV CYREG_GPIO_PRT0_DR_INV
#define CapSense_Sns__DR_SET CYREG_GPIO_PRT0_DR_SET
#define CapSense_Sns__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__INTR CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define CapSense_Sns__INTSTAT CYREG_GPIO_PRT0_INTR
#define CapSense_Sns__MASK 0x02u
#define CapSense_Sns__PC CYREG_GPIO_PRT0_PC
#define CapSense_Sns__PC2 CYREG_GPIO_PRT0_PC2
#define CapSense_Sns__PORT 0u
#define CapSense_Sns__PS CYREG_GPIO_PRT0_PS
#define CapSense_Sns__SHIFT 1u

/* Miscellaneous */
#define CY_PROJECT_NAME "CapSense_1Button"
#define CY_VERSION "PSoC Creator  4.0"
#define CYDEV_BANDGAP_VOLTAGE 1.200
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 12u
#define CYDEV_CHIP_DIE_PSOC5LP 19u
#define CYDEV_CHIP_DIE_PSOC5TM 20u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 4u
#define CYDEV_CHIP_FAMILY_FM3 5u
#define CYDEV_CHIP_FAMILY_FM4 6u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x1B0011ABu
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 12u
#define CYDEV_CHIP_MEMBER_4C 18u
#define CYDEV_CHIP_MEMBER_4D 8u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 13u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 11u
#define CYDEV_CHIP_MEMBER_4I 17u
#define CYDEV_CHIP_MEMBER_4J 9u
#define CYDEV_CHIP_MEMBER_4K 10u
#define CYDEV_CHIP_MEMBER_4L 16u
#define CYDEV_CHIP_MEMBER_4M 15u
#define CYDEV_CHIP_MEMBER_4N 6u
#define CYDEV_CHIP_MEMBER_4O 5u
#define CYDEV_CHIP_MEMBER_4P 14u
#define CYDEV_CHIP_MEMBER_4Q 7u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 20u
#define CYDEV_CHIP_MEMBER_5B 19u
#define CYDEV_CHIP_MEMBER_FM3 24u
#define CYDEV_CHIP_MEMBER_FM4 25u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4K
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4K_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_ENABLE 0
#define CYDEV_DFT_SELECT_CLK0 8u
#define CYDEV_DFT_SELECT_CLK1 9u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0400
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_WDT_GENERATE_ISR 0u
#define CYIPBLOCK_m0s8cpussv3_VERSION 1
#define CYIPBLOCK_m0s8csdv2_VERSION 1
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8lcd_VERSION 2
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
#define CYIPBLOCK_m0s8pass4a_VERSION 1
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8wco_VERSION 1
#define CYIPBLOCK_s8srsslt_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
