#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* I2C_1_SCB */
#define I2C_1_SCB__CTRL CYREG_SCB1_CTRL
#define I2C_1_SCB__EZ_DATA0 CYREG_SCB1_EZ_DATA0
#define I2C_1_SCB__EZ_DATA1 CYREG_SCB1_EZ_DATA1
#define I2C_1_SCB__EZ_DATA10 CYREG_SCB1_EZ_DATA10
#define I2C_1_SCB__EZ_DATA11 CYREG_SCB1_EZ_DATA11
#define I2C_1_SCB__EZ_DATA12 CYREG_SCB1_EZ_DATA12
#define I2C_1_SCB__EZ_DATA13 CYREG_SCB1_EZ_DATA13
#define I2C_1_SCB__EZ_DATA14 CYREG_SCB1_EZ_DATA14
#define I2C_1_SCB__EZ_DATA15 CYREG_SCB1_EZ_DATA15
#define I2C_1_SCB__EZ_DATA16 CYREG_SCB1_EZ_DATA16
#define I2C_1_SCB__EZ_DATA17 CYREG_SCB1_EZ_DATA17
#define I2C_1_SCB__EZ_DATA18 CYREG_SCB1_EZ_DATA18
#define I2C_1_SCB__EZ_DATA19 CYREG_SCB1_EZ_DATA19
#define I2C_1_SCB__EZ_DATA2 CYREG_SCB1_EZ_DATA2
#define I2C_1_SCB__EZ_DATA20 CYREG_SCB1_EZ_DATA20
#define I2C_1_SCB__EZ_DATA21 CYREG_SCB1_EZ_DATA21
#define I2C_1_SCB__EZ_DATA22 CYREG_SCB1_EZ_DATA22
#define I2C_1_SCB__EZ_DATA23 CYREG_SCB1_EZ_DATA23
#define I2C_1_SCB__EZ_DATA24 CYREG_SCB1_EZ_DATA24
#define I2C_1_SCB__EZ_DATA25 CYREG_SCB1_EZ_DATA25
#define I2C_1_SCB__EZ_DATA26 CYREG_SCB1_EZ_DATA26
#define I2C_1_SCB__EZ_DATA27 CYREG_SCB1_EZ_DATA27
#define I2C_1_SCB__EZ_DATA28 CYREG_SCB1_EZ_DATA28
#define I2C_1_SCB__EZ_DATA29 CYREG_SCB1_EZ_DATA29
#define I2C_1_SCB__EZ_DATA3 CYREG_SCB1_EZ_DATA3
#define I2C_1_SCB__EZ_DATA30 CYREG_SCB1_EZ_DATA30
#define I2C_1_SCB__EZ_DATA31 CYREG_SCB1_EZ_DATA31
#define I2C_1_SCB__EZ_DATA4 CYREG_SCB1_EZ_DATA4
#define I2C_1_SCB__EZ_DATA5 CYREG_SCB1_EZ_DATA5
#define I2C_1_SCB__EZ_DATA6 CYREG_SCB1_EZ_DATA6
#define I2C_1_SCB__EZ_DATA7 CYREG_SCB1_EZ_DATA7
#define I2C_1_SCB__EZ_DATA8 CYREG_SCB1_EZ_DATA8
#define I2C_1_SCB__EZ_DATA9 CYREG_SCB1_EZ_DATA9
#define I2C_1_SCB__I2C_CFG CYREG_SCB1_I2C_CFG
#define I2C_1_SCB__I2C_CTRL CYREG_SCB1_I2C_CTRL
#define I2C_1_SCB__I2C_M_CMD CYREG_SCB1_I2C_M_CMD
#define I2C_1_SCB__I2C_S_CMD CYREG_SCB1_I2C_S_CMD
#define I2C_1_SCB__I2C_STATUS CYREG_SCB1_I2C_STATUS
#define I2C_1_SCB__INTR_CAUSE CYREG_SCB1_INTR_CAUSE
#define I2C_1_SCB__INTR_I2C_EC CYREG_SCB1_INTR_I2C_EC
#define I2C_1_SCB__INTR_I2C_EC_MASK CYREG_SCB1_INTR_I2C_EC_MASK
#define I2C_1_SCB__INTR_I2C_EC_MASKED CYREG_SCB1_INTR_I2C_EC_MASKED
#define I2C_1_SCB__INTR_M CYREG_SCB1_INTR_M
#define I2C_1_SCB__INTR_M_MASK CYREG_SCB1_INTR_M_MASK
#define I2C_1_SCB__INTR_M_MASKED CYREG_SCB1_INTR_M_MASKED
#define I2C_1_SCB__INTR_M_SET CYREG_SCB1_INTR_M_SET
#define I2C_1_SCB__INTR_RX CYREG_SCB1_INTR_RX
#define I2C_1_SCB__INTR_RX_MASK CYREG_SCB1_INTR_RX_MASK
#define I2C_1_SCB__INTR_RX_MASKED CYREG_SCB1_INTR_RX_MASKED
#define I2C_1_SCB__INTR_RX_SET CYREG_SCB1_INTR_RX_SET
#define I2C_1_SCB__INTR_S CYREG_SCB1_INTR_S
#define I2C_1_SCB__INTR_S_MASK CYREG_SCB1_INTR_S_MASK
#define I2C_1_SCB__INTR_S_MASKED CYREG_SCB1_INTR_S_MASKED
#define I2C_1_SCB__INTR_S_SET CYREG_SCB1_INTR_S_SET
#define I2C_1_SCB__INTR_SPI_EC CYREG_SCB1_INTR_SPI_EC
#define I2C_1_SCB__INTR_SPI_EC_MASK CYREG_SCB1_INTR_SPI_EC_MASK
#define I2C_1_SCB__INTR_SPI_EC_MASKED CYREG_SCB1_INTR_SPI_EC_MASKED
#define I2C_1_SCB__INTR_TX CYREG_SCB1_INTR_TX
#define I2C_1_SCB__INTR_TX_MASK CYREG_SCB1_INTR_TX_MASK
#define I2C_1_SCB__INTR_TX_MASKED CYREG_SCB1_INTR_TX_MASKED
#define I2C_1_SCB__INTR_TX_SET CYREG_SCB1_INTR_TX_SET
#define I2C_1_SCB__RX_CTRL CYREG_SCB1_RX_CTRL
#define I2C_1_SCB__RX_FIFO_CTRL CYREG_SCB1_RX_FIFO_CTRL
#define I2C_1_SCB__RX_FIFO_RD CYREG_SCB1_RX_FIFO_RD
#define I2C_1_SCB__RX_FIFO_RD_SILENT CYREG_SCB1_RX_FIFO_RD_SILENT
#define I2C_1_SCB__RX_FIFO_STATUS CYREG_SCB1_RX_FIFO_STATUS
#define I2C_1_SCB__RX_MATCH CYREG_SCB1_RX_MATCH
#define I2C_1_SCB__SPI_CTRL CYREG_SCB1_SPI_CTRL
#define I2C_1_SCB__SPI_STATUS CYREG_SCB1_SPI_STATUS
#define I2C_1_SCB__SS0_POSISTION 0u
#define I2C_1_SCB__SS1_POSISTION 1u
#define I2C_1_SCB__SS2_POSISTION 2u
#define I2C_1_SCB__SS3_POSISTION 3u
#define I2C_1_SCB__STATUS CYREG_SCB1_STATUS
#define I2C_1_SCB__TX_CTRL CYREG_SCB1_TX_CTRL
#define I2C_1_SCB__TX_FIFO_CTRL CYREG_SCB1_TX_FIFO_CTRL
#define I2C_1_SCB__TX_FIFO_STATUS CYREG_SCB1_TX_FIFO_STATUS
#define I2C_1_SCB__TX_FIFO_WR CYREG_SCB1_TX_FIFO_WR
#define I2C_1_SCB__UART_CTRL CYREG_SCB1_UART_CTRL
#define I2C_1_SCB__UART_FLOW_CTRL CYREG_SCB1_UART_FLOW_CTRL
#define I2C_1_SCB__UART_RX_CTRL CYREG_SCB1_UART_RX_CTRL
#define I2C_1_SCB__UART_RX_STATUS CYREG_SCB1_UART_RX_STATUS
#define I2C_1_SCB__UART_TX_CTRL CYREG_SCB1_UART_TX_CTRL

/* I2C_1_SCB_IRQ */
#define I2C_1_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define I2C_1_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define I2C_1_SCB_IRQ__INTC_MASK 0x100u
#define I2C_1_SCB_IRQ__INTC_NUMBER 8u
#define I2C_1_SCB_IRQ__INTC_PRIOR_MASK 0xC0u
#define I2C_1_SCB_IRQ__INTC_PRIOR_NUM 3u
#define I2C_1_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR2
#define I2C_1_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER
#define I2C_1_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* I2C_1_SCBCLK */
#define I2C_1_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL1
#define I2C_1_SCBCLK__DIV_ID 0x00000041u
#define I2C_1_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define I2C_1_SCBCLK__PA_DIV_ID 0x000000FFu

/* I2C_1_scl */
#define I2C_1_scl__0__DR CYREG_GPIO_PRT0_DR
#define I2C_1_scl__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define I2C_1_scl__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define I2C_1_scl__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define I2C_1_scl__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define I2C_1_scl__0__HSIOM_GPIO 0u
#define I2C_1_scl__0__HSIOM_I2C 14u
#define I2C_1_scl__0__HSIOM_I2C_SCL 14u
#define I2C_1_scl__0__HSIOM_MASK 0x000F0000u
#define I2C_1_scl__0__HSIOM_SHIFT 16u
#define I2C_1_scl__0__HSIOM_SPI 15u
#define I2C_1_scl__0__HSIOM_SPI_MOSI 15u
#define I2C_1_scl__0__HSIOM_UART 9u
#define I2C_1_scl__0__HSIOM_UART_RX 9u
#define I2C_1_scl__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_scl__0__INTR CYREG_GPIO_PRT0_INTR
#define I2C_1_scl__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_scl__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define I2C_1_scl__0__MASK 0x10u
#define I2C_1_scl__0__PC CYREG_GPIO_PRT0_PC
#define I2C_1_scl__0__PC2 CYREG_GPIO_PRT0_PC2
#define I2C_1_scl__0__PORT 0u
#define I2C_1_scl__0__PS CYREG_GPIO_PRT0_PS
#define I2C_1_scl__0__SHIFT 4u
#define I2C_1_scl__DR CYREG_GPIO_PRT0_DR
#define I2C_1_scl__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define I2C_1_scl__DR_INV CYREG_GPIO_PRT0_DR_INV
#define I2C_1_scl__DR_SET CYREG_GPIO_PRT0_DR_SET
#define I2C_1_scl__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_scl__INTR CYREG_GPIO_PRT0_INTR
#define I2C_1_scl__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_scl__INTSTAT CYREG_GPIO_PRT0_INTR
#define I2C_1_scl__MASK 0x10u
#define I2C_1_scl__PC CYREG_GPIO_PRT0_PC
#define I2C_1_scl__PC2 CYREG_GPIO_PRT0_PC2
#define I2C_1_scl__PORT 0u
#define I2C_1_scl__PS CYREG_GPIO_PRT0_PS
#define I2C_1_scl__SHIFT 4u

/* I2C_1_sda */
#define I2C_1_sda__0__DR CYREG_GPIO_PRT0_DR
#define I2C_1_sda__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define I2C_1_sda__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define I2C_1_sda__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define I2C_1_sda__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define I2C_1_sda__0__HSIOM_GPIO 0u
#define I2C_1_sda__0__HSIOM_I2C 14u
#define I2C_1_sda__0__HSIOM_I2C_SDA 14u
#define I2C_1_sda__0__HSIOM_MASK 0x00F00000u
#define I2C_1_sda__0__HSIOM_SHIFT 20u
#define I2C_1_sda__0__HSIOM_SPI 15u
#define I2C_1_sda__0__HSIOM_SPI_MISO 15u
#define I2C_1_sda__0__HSIOM_UART 9u
#define I2C_1_sda__0__HSIOM_UART_TX 9u
#define I2C_1_sda__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_sda__0__INTR CYREG_GPIO_PRT0_INTR
#define I2C_1_sda__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_sda__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define I2C_1_sda__0__MASK 0x20u
#define I2C_1_sda__0__PC CYREG_GPIO_PRT0_PC
#define I2C_1_sda__0__PC2 CYREG_GPIO_PRT0_PC2
#define I2C_1_sda__0__PORT 0u
#define I2C_1_sda__0__PS CYREG_GPIO_PRT0_PS
#define I2C_1_sda__0__SHIFT 5u
#define I2C_1_sda__DR CYREG_GPIO_PRT0_DR
#define I2C_1_sda__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define I2C_1_sda__DR_INV CYREG_GPIO_PRT0_DR_INV
#define I2C_1_sda__DR_SET CYREG_GPIO_PRT0_DR_SET
#define I2C_1_sda__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_sda__INTR CYREG_GPIO_PRT0_INTR
#define I2C_1_sda__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define I2C_1_sda__INTSTAT CYREG_GPIO_PRT0_INTR
#define I2C_1_sda__MASK 0x20u
#define I2C_1_sda__PC CYREG_GPIO_PRT0_PC
#define I2C_1_sda__PC2 CYREG_GPIO_PRT0_PC2
#define I2C_1_sda__PORT 0u
#define I2C_1_sda__PS CYREG_GPIO_PRT0_PS
#define I2C_1_sda__SHIFT 5u

/* Pin_1 */
#define Pin_1__0__DR CYREG_GPIO_PRT2_DR
#define Pin_1__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_1__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_1__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_1__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_1__0__HSIOM_MASK 0x000F0000u
#define Pin_1__0__HSIOM_SHIFT 16u
#define Pin_1__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_1__0__INTR CYREG_GPIO_PRT2_INTR
#define Pin_1__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_1__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_1__0__MASK 0x10u
#define Pin_1__0__PC CYREG_GPIO_PRT2_PC
#define Pin_1__0__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_1__0__PORT 2u
#define Pin_1__0__PS CYREG_GPIO_PRT2_PS
#define Pin_1__0__SHIFT 4u
#define Pin_1__DR CYREG_GPIO_PRT2_DR
#define Pin_1__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_1__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_1__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_1__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_1__INTR CYREG_GPIO_PRT2_INTR
#define Pin_1__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_1__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_1__MASK 0x10u
#define Pin_1__PC CYREG_GPIO_PRT2_PC
#define Pin_1__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_1__PORT 2u
#define Pin_1__PS CYREG_GPIO_PRT2_PS
#define Pin_1__SHIFT 4u

/* Pin_2 */
#define Pin_2__0__DR CYREG_GPIO_PRT2_DR
#define Pin_2__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_2__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_2__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_2__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_2__0__HSIOM_MASK 0x00F00000u
#define Pin_2__0__HSIOM_SHIFT 20u
#define Pin_2__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_2__0__INTR CYREG_GPIO_PRT2_INTR
#define Pin_2__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_2__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_2__0__MASK 0x20u
#define Pin_2__0__PC CYREG_GPIO_PRT2_PC
#define Pin_2__0__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_2__0__PORT 2u
#define Pin_2__0__PS CYREG_GPIO_PRT2_PS
#define Pin_2__0__SHIFT 5u
#define Pin_2__DR CYREG_GPIO_PRT2_DR
#define Pin_2__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_2__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_2__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_2__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_2__INTR CYREG_GPIO_PRT2_INTR
#define Pin_2__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_2__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_2__MASK 0x20u
#define Pin_2__PC CYREG_GPIO_PRT2_PC
#define Pin_2__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_2__PORT 2u
#define Pin_2__PS CYREG_GPIO_PRT2_PS
#define Pin_2__SHIFT 5u

/* SmartIO_1_cy_m0s8_prgio */
#define SmartIO_1_cy_m0s8_prgio__CTL CYREG_PRGIO_PRT0_CTL
#define SmartIO_1_cy_m0s8_prgio__DATA CYREG_PRGIO_PRT0_DATA
#define SmartIO_1_cy_m0s8_prgio__DU_CTL CYREG_PRGIO_PRT0_DU_CTL
#define SmartIO_1_cy_m0s8_prgio__DU_SEL CYREG_PRGIO_PRT0_DU_SEL
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL0 CYREG_PRGIO_PRT0_LUT_CTL0
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL1 CYREG_PRGIO_PRT0_LUT_CTL1
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL2 CYREG_PRGIO_PRT0_LUT_CTL2
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL3 CYREG_PRGIO_PRT0_LUT_CTL3
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL4 CYREG_PRGIO_PRT0_LUT_CTL4
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL5 CYREG_PRGIO_PRT0_LUT_CTL5
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL6 CYREG_PRGIO_PRT0_LUT_CTL6
#define SmartIO_1_cy_m0s8_prgio__LUT_CTL7 CYREG_PRGIO_PRT0_LUT_CTL7
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL0 CYREG_PRGIO_PRT0_LUT_SEL0
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL1 CYREG_PRGIO_PRT0_LUT_SEL1
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL2 CYREG_PRGIO_PRT0_LUT_SEL2
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL3 CYREG_PRGIO_PRT0_LUT_SEL3
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL4 CYREG_PRGIO_PRT0_LUT_SEL4
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL5 CYREG_PRGIO_PRT0_LUT_SEL5
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL6 CYREG_PRGIO_PRT0_LUT_SEL6
#define SmartIO_1_cy_m0s8_prgio__LUT_SEL7 CYREG_PRGIO_PRT0_LUT_SEL7
#define SmartIO_1_cy_m0s8_prgio__SYNC_CTL CYREG_PRGIO_PRT0_SYNC_CTL

/* SmartIO_1_internalPin_i0 */
#define SmartIO_1_internalPin_i0__0__DR CYREG_GPIO_PRT2_DR
#define SmartIO_1_internalPin_i0__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SmartIO_1_internalPin_i0__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SmartIO_1_internalPin_i0__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SmartIO_1_internalPin_i0__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define SmartIO_1_internalPin_i0__0__HSIOM_MASK 0x0000000Fu
#define SmartIO_1_internalPin_i0__0__HSIOM_SHIFT 0u
#define SmartIO_1_internalPin_i0__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_i0__0__INTR CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_i0__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_i0__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_i0__0__MASK 0x01u
#define SmartIO_1_internalPin_i0__0__PC CYREG_GPIO_PRT2_PC
#define SmartIO_1_internalPin_i0__0__PC2 CYREG_GPIO_PRT2_PC2
#define SmartIO_1_internalPin_i0__0__PORT 2u
#define SmartIO_1_internalPin_i0__0__PS CYREG_GPIO_PRT2_PS
#define SmartIO_1_internalPin_i0__0__SHIFT 0u
#define SmartIO_1_internalPin_i0__DR CYREG_GPIO_PRT2_DR
#define SmartIO_1_internalPin_i0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SmartIO_1_internalPin_i0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SmartIO_1_internalPin_i0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SmartIO_1_internalPin_i0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_i0__INTR CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_i0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_i0__INTSTAT CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_i0__MASK 0x01u
#define SmartIO_1_internalPin_i0__PC CYREG_GPIO_PRT2_PC
#define SmartIO_1_internalPin_i0__PC2 CYREG_GPIO_PRT2_PC2
#define SmartIO_1_internalPin_i0__PORT 2u
#define SmartIO_1_internalPin_i0__PS CYREG_GPIO_PRT2_PS
#define SmartIO_1_internalPin_i0__SHIFT 0u

/* SmartIO_1_internalPin_o7 */
#define SmartIO_1_internalPin_o7__0__DR CYREG_GPIO_PRT2_DR
#define SmartIO_1_internalPin_o7__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SmartIO_1_internalPin_o7__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SmartIO_1_internalPin_o7__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SmartIO_1_internalPin_o7__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define SmartIO_1_internalPin_o7__0__HSIOM_MASK 0xF0000000u
#define SmartIO_1_internalPin_o7__0__HSIOM_SHIFT 28u
#define SmartIO_1_internalPin_o7__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_o7__0__INTR CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_o7__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_o7__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_o7__0__MASK 0x80u
#define SmartIO_1_internalPin_o7__0__PC CYREG_GPIO_PRT2_PC
#define SmartIO_1_internalPin_o7__0__PC2 CYREG_GPIO_PRT2_PC2
#define SmartIO_1_internalPin_o7__0__PORT 2u
#define SmartIO_1_internalPin_o7__0__PS CYREG_GPIO_PRT2_PS
#define SmartIO_1_internalPin_o7__0__SHIFT 7u
#define SmartIO_1_internalPin_o7__DR CYREG_GPIO_PRT2_DR
#define SmartIO_1_internalPin_o7__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SmartIO_1_internalPin_o7__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SmartIO_1_internalPin_o7__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SmartIO_1_internalPin_o7__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_o7__INTR CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_o7__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SmartIO_1_internalPin_o7__INTSTAT CYREG_GPIO_PRT2_INTR
#define SmartIO_1_internalPin_o7__MASK 0x80u
#define SmartIO_1_internalPin_o7__PC CYREG_GPIO_PRT2_PC
#define SmartIO_1_internalPin_o7__PC2 CYREG_GPIO_PRT2_PC2
#define SmartIO_1_internalPin_o7__PORT 2u
#define SmartIO_1_internalPin_o7__PS CYREG_GPIO_PRT2_PS
#define SmartIO_1_internalPin_o7__SHIFT 7u

/* ADC_SAR_Seq_1_cy_psoc4_sar */
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_ANA_TRIM CYREG_SAR_ANA_TRIM
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG0
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG1
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG2
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG3
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG4
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG5
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG6
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG7
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG08 CYREG_SAR_CHAN_CONFIG8
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG09 CYREG_SAR_CHAN_CONFIG9
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG10 CYREG_SAR_CHAN_CONFIG10
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG11 CYREG_SAR_CHAN_CONFIG11
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG12 CYREG_SAR_CHAN_CONFIG12
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG13 CYREG_SAR_CHAN_CONFIG13
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG14 CYREG_SAR_CHAN_CONFIG14
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG15 CYREG_SAR_CHAN_CONFIG15
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_EN CYREG_SAR_CHAN_EN
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT_VALID CYREG_SAR_CHAN_RESULT_VALID
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT0
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT1
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT2
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT3
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT4
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT5
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT6
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT7
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT08 CYREG_SAR_CHAN_RESULT8
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT09 CYREG_SAR_CHAN_RESULT9
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT10 CYREG_SAR_CHAN_RESULT10
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT11 CYREG_SAR_CHAN_RESULT11
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT12 CYREG_SAR_CHAN_RESULT12
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT13 CYREG_SAR_CHAN_RESULT13
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT14 CYREG_SAR_CHAN_RESULT14
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT15 CYREG_SAR_CHAN_RESULT15
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK_VALID CYREG_SAR_CHAN_WORK_VALID
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK0
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK1
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK2
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK3
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK4
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK5
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK6
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK7
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK08 CYREG_SAR_CHAN_WORK8
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK09 CYREG_SAR_CHAN_WORK9
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK10 CYREG_SAR_CHAN_WORK10
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK11 CYREG_SAR_CHAN_WORK11
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK12 CYREG_SAR_CHAN_WORK12
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK13 CYREG_SAR_CHAN_WORK13
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK14 CYREG_SAR_CHAN_WORK14
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK15 CYREG_SAR_CHAN_WORK15
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_DFT_CTRL CYREG_SAR_DFT_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL CYREG_SAR_MUX_SWITCH_HW_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH0 CYREG_SAR_MUX_SWITCH0
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_NUMBER 0u
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_PUMP_CTRL CYREG_SAR_PUMP_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR CYREG_SAR_RANGE_INTR
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR CYREG_SAR_SATURATE_INTR
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_START_CTRL CYREG_SAR_START_CTRL
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS
#define ADC_SAR_Seq_1_cy_psoc4_sar__SAR_WOUNDING CYREG_SAR_WOUNDING

/* ADC_SAR_Seq_1_intClock */
#define ADC_SAR_Seq_1_intClock__CTRL_REGISTER CYREG_PERI_PCLK_CTL12
#define ADC_SAR_Seq_1_intClock__DIV_ID 0x00000040u
#define ADC_SAR_Seq_1_intClock__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define ADC_SAR_Seq_1_intClock__PA_DIV_ID 0x000000FFu

/* ADC_SAR_Seq_1_IRQ */
#define ADC_SAR_Seq_1_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define ADC_SAR_Seq_1_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define ADC_SAR_Seq_1_IRQ__INTC_MASK 0x80000u
#define ADC_SAR_Seq_1_IRQ__INTC_NUMBER 19u
#define ADC_SAR_Seq_1_IRQ__INTC_PRIOR_MASK 0xC0000000u
#define ADC_SAR_Seq_1_IRQ__INTC_PRIOR_NUM 3u
#define ADC_SAR_Seq_1_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR4
#define ADC_SAR_Seq_1_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER
#define ADC_SAR_Seq_1_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* Miscellaneous */
#define CY_PROJECT_NAME "I2C"
#define CY_VERSION "PSoC Creator  4.0"
#define CYDEV_BANDGAP_VOLTAGE 1.200
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 12u
#define CYDEV_CHIP_DIE_PSOC5LP 19u
#define CYDEV_CHIP_DIE_PSOC5TM 20u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 4u
#define CYDEV_CHIP_FAMILY_FM3 5u
#define CYDEV_CHIP_FAMILY_FM4 6u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x1B0011ABu
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 12u
#define CYDEV_CHIP_MEMBER_4C 18u
#define CYDEV_CHIP_MEMBER_4D 8u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 13u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 11u
#define CYDEV_CHIP_MEMBER_4I 17u
#define CYDEV_CHIP_MEMBER_4J 9u
#define CYDEV_CHIP_MEMBER_4K 10u
#define CYDEV_CHIP_MEMBER_4L 16u
#define CYDEV_CHIP_MEMBER_4M 15u
#define CYDEV_CHIP_MEMBER_4N 6u
#define CYDEV_CHIP_MEMBER_4O 5u
#define CYDEV_CHIP_MEMBER_4P 14u
#define CYDEV_CHIP_MEMBER_4Q 7u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 20u
#define CYDEV_CHIP_MEMBER_5B 19u
#define CYDEV_CHIP_MEMBER_FM3 24u
#define CYDEV_CHIP_MEMBER_FM4 25u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4K
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4K_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_Disallowed
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DFT_SELECT_CLK0 8u
#define CYDEV_DFT_SELECT_CLK1 9u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_WDT_GENERATE_ISR 1u
#define CYIPBLOCK_m0s8cpussv3_VERSION 1
#define CYIPBLOCK_m0s8csdv2_VERSION 1
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8lcd_VERSION 2
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
#define CYIPBLOCK_m0s8pass4a_VERSION 1
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8wco_VERSION 1
#define CYIPBLOCK_s8srsslt_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
