#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* I2C_1_SCB */
I2C_1_SCB__CTRL EQU CYREG_SCB1_CTRL
I2C_1_SCB__EZ_DATA0 EQU CYREG_SCB1_EZ_DATA0
I2C_1_SCB__EZ_DATA1 EQU CYREG_SCB1_EZ_DATA1
I2C_1_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10
I2C_1_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11
I2C_1_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12
I2C_1_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13
I2C_1_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14
I2C_1_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15
I2C_1_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16
I2C_1_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17
I2C_1_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18
I2C_1_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19
I2C_1_SCB__EZ_DATA2 EQU CYREG_SCB1_EZ_DATA2
I2C_1_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20
I2C_1_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21
I2C_1_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22
I2C_1_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23
I2C_1_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24
I2C_1_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25
I2C_1_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26
I2C_1_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27
I2C_1_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28
I2C_1_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29
I2C_1_SCB__EZ_DATA3 EQU CYREG_SCB1_EZ_DATA3
I2C_1_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30
I2C_1_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31
I2C_1_SCB__EZ_DATA4 EQU CYREG_SCB1_EZ_DATA4
I2C_1_SCB__EZ_DATA5 EQU CYREG_SCB1_EZ_DATA5
I2C_1_SCB__EZ_DATA6 EQU CYREG_SCB1_EZ_DATA6
I2C_1_SCB__EZ_DATA7 EQU CYREG_SCB1_EZ_DATA7
I2C_1_SCB__EZ_DATA8 EQU CYREG_SCB1_EZ_DATA8
I2C_1_SCB__EZ_DATA9 EQU CYREG_SCB1_EZ_DATA9
I2C_1_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG
I2C_1_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL
I2C_1_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD
I2C_1_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD
I2C_1_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS
I2C_1_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE
I2C_1_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC
I2C_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK
I2C_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED
I2C_1_SCB__INTR_M EQU CYREG_SCB1_INTR_M
I2C_1_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK
I2C_1_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED
I2C_1_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET
I2C_1_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX
I2C_1_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK
I2C_1_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED
I2C_1_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET
I2C_1_SCB__INTR_S EQU CYREG_SCB1_INTR_S
I2C_1_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK
I2C_1_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED
I2C_1_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET
I2C_1_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC
I2C_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK
I2C_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED
I2C_1_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX
I2C_1_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK
I2C_1_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED
I2C_1_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET
I2C_1_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL
I2C_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL
I2C_1_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD
I2C_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT
I2C_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS
I2C_1_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH
I2C_1_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL
I2C_1_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS
I2C_1_SCB__SS0_POSISTION EQU 0
I2C_1_SCB__SS1_POSISTION EQU 1
I2C_1_SCB__SS2_POSISTION EQU 2
I2C_1_SCB__SS3_POSISTION EQU 3
I2C_1_SCB__STATUS EQU CYREG_SCB1_STATUS
I2C_1_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL
I2C_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL
I2C_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS
I2C_1_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR
I2C_1_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL
I2C_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB1_UART_FLOW_CTRL
I2C_1_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL
I2C_1_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS
I2C_1_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL

/* I2C_1_SCB_IRQ */
I2C_1_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
I2C_1_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
I2C_1_SCB_IRQ__INTC_MASK EQU 0x100
I2C_1_SCB_IRQ__INTC_NUMBER EQU 8
I2C_1_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0
I2C_1_SCB_IRQ__INTC_PRIOR_NUM EQU 3
I2C_1_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2
I2C_1_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
I2C_1_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

/* I2C_1_SCBCLK */
I2C_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1
I2C_1_SCBCLK__DIV_ID EQU 0x00000041
I2C_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
I2C_1_SCBCLK__PA_DIV_ID EQU 0x000000FF

/* I2C_1_scl */
I2C_1_scl__0__DR EQU CYREG_GPIO_PRT0_DR
I2C_1_scl__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
I2C_1_scl__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
I2C_1_scl__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
I2C_1_scl__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
I2C_1_scl__0__HSIOM_GPIO EQU 0
I2C_1_scl__0__HSIOM_I2C EQU 14
I2C_1_scl__0__HSIOM_I2C_SCL EQU 14
I2C_1_scl__0__HSIOM_MASK EQU 0x000F0000
I2C_1_scl__0__HSIOM_SHIFT EQU 16
I2C_1_scl__0__HSIOM_SPI EQU 15
I2C_1_scl__0__HSIOM_SPI_MOSI EQU 15
I2C_1_scl__0__HSIOM_UART EQU 9
I2C_1_scl__0__HSIOM_UART_RX EQU 9
I2C_1_scl__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_scl__0__INTR EQU CYREG_GPIO_PRT0_INTR
I2C_1_scl__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_scl__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
I2C_1_scl__0__MASK EQU 0x10
I2C_1_scl__0__PC EQU CYREG_GPIO_PRT0_PC
I2C_1_scl__0__PC2 EQU CYREG_GPIO_PRT0_PC2
I2C_1_scl__0__PORT EQU 0
I2C_1_scl__0__PS EQU CYREG_GPIO_PRT0_PS
I2C_1_scl__0__SHIFT EQU 4
I2C_1_scl__DR EQU CYREG_GPIO_PRT0_DR
I2C_1_scl__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
I2C_1_scl__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
I2C_1_scl__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
I2C_1_scl__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_scl__INTR EQU CYREG_GPIO_PRT0_INTR
I2C_1_scl__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_scl__INTSTAT EQU CYREG_GPIO_PRT0_INTR
I2C_1_scl__MASK EQU 0x10
I2C_1_scl__PC EQU CYREG_GPIO_PRT0_PC
I2C_1_scl__PC2 EQU CYREG_GPIO_PRT0_PC2
I2C_1_scl__PORT EQU 0
I2C_1_scl__PS EQU CYREG_GPIO_PRT0_PS
I2C_1_scl__SHIFT EQU 4

/* I2C_1_sda */
I2C_1_sda__0__DR EQU CYREG_GPIO_PRT0_DR
I2C_1_sda__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
I2C_1_sda__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
I2C_1_sda__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
I2C_1_sda__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
I2C_1_sda__0__HSIOM_GPIO EQU 0
I2C_1_sda__0__HSIOM_I2C EQU 14
I2C_1_sda__0__HSIOM_I2C_SDA EQU 14
I2C_1_sda__0__HSIOM_MASK EQU 0x00F00000
I2C_1_sda__0__HSIOM_SHIFT EQU 20
I2C_1_sda__0__HSIOM_SPI EQU 15
I2C_1_sda__0__HSIOM_SPI_MISO EQU 15
I2C_1_sda__0__HSIOM_UART EQU 9
I2C_1_sda__0__HSIOM_UART_TX EQU 9
I2C_1_sda__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_sda__0__INTR EQU CYREG_GPIO_PRT0_INTR
I2C_1_sda__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_sda__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
I2C_1_sda__0__MASK EQU 0x20
I2C_1_sda__0__PC EQU CYREG_GPIO_PRT0_PC
I2C_1_sda__0__PC2 EQU CYREG_GPIO_PRT0_PC2
I2C_1_sda__0__PORT EQU 0
I2C_1_sda__0__PS EQU CYREG_GPIO_PRT0_PS
I2C_1_sda__0__SHIFT EQU 5
I2C_1_sda__DR EQU CYREG_GPIO_PRT0_DR
I2C_1_sda__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
I2C_1_sda__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
I2C_1_sda__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
I2C_1_sda__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_sda__INTR EQU CYREG_GPIO_PRT0_INTR
I2C_1_sda__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
I2C_1_sda__INTSTAT EQU CYREG_GPIO_PRT0_INTR
I2C_1_sda__MASK EQU 0x20
I2C_1_sda__PC EQU CYREG_GPIO_PRT0_PC
I2C_1_sda__PC2 EQU CYREG_GPIO_PRT0_PC2
I2C_1_sda__PORT EQU 0
I2C_1_sda__PS EQU CYREG_GPIO_PRT0_PS
I2C_1_sda__SHIFT EQU 5

/* Pin_1 */
Pin_1__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_1__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_1__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_1__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_1__0__HSIOM_MASK EQU 0x000F0000
Pin_1__0__HSIOM_SHIFT EQU 16
Pin_1__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_1__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_1__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_1__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_1__0__MASK EQU 0x10
Pin_1__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_1__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_1__0__PORT EQU 2
Pin_1__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_1__0__SHIFT EQU 4
Pin_1__DR EQU CYREG_GPIO_PRT2_DR
Pin_1__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_1__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_1__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_1__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_1__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_1__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_1__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_1__MASK EQU 0x10
Pin_1__PC EQU CYREG_GPIO_PRT2_PC
Pin_1__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_1__PORT EQU 2
Pin_1__PS EQU CYREG_GPIO_PRT2_PS
Pin_1__SHIFT EQU 4

/* Pin_2 */
Pin_2__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_2__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_2__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_2__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_2__0__HSIOM_MASK EQU 0x00F00000
Pin_2__0__HSIOM_SHIFT EQU 20
Pin_2__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_2__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_2__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_2__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_2__0__MASK EQU 0x20
Pin_2__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_2__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_2__0__PORT EQU 2
Pin_2__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_2__0__SHIFT EQU 5
Pin_2__DR EQU CYREG_GPIO_PRT2_DR
Pin_2__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_2__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_2__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_2__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_2__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_2__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_2__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_2__MASK EQU 0x20
Pin_2__PC EQU CYREG_GPIO_PRT2_PC
Pin_2__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_2__PORT EQU 2
Pin_2__PS EQU CYREG_GPIO_PRT2_PS
Pin_2__SHIFT EQU 5

/* SmartIO_1_cy_m0s8_prgio */
SmartIO_1_cy_m0s8_prgio__CTL EQU CYREG_PRGIO_PRT0_CTL
SmartIO_1_cy_m0s8_prgio__DATA EQU CYREG_PRGIO_PRT0_DATA
SmartIO_1_cy_m0s8_prgio__DU_CTL EQU CYREG_PRGIO_PRT0_DU_CTL
SmartIO_1_cy_m0s8_prgio__DU_SEL EQU CYREG_PRGIO_PRT0_DU_SEL
SmartIO_1_cy_m0s8_prgio__LUT_CTL0 EQU CYREG_PRGIO_PRT0_LUT_CTL0
SmartIO_1_cy_m0s8_prgio__LUT_CTL1 EQU CYREG_PRGIO_PRT0_LUT_CTL1
SmartIO_1_cy_m0s8_prgio__LUT_CTL2 EQU CYREG_PRGIO_PRT0_LUT_CTL2
SmartIO_1_cy_m0s8_prgio__LUT_CTL3 EQU CYREG_PRGIO_PRT0_LUT_CTL3
SmartIO_1_cy_m0s8_prgio__LUT_CTL4 EQU CYREG_PRGIO_PRT0_LUT_CTL4
SmartIO_1_cy_m0s8_prgio__LUT_CTL5 EQU CYREG_PRGIO_PRT0_LUT_CTL5
SmartIO_1_cy_m0s8_prgio__LUT_CTL6 EQU CYREG_PRGIO_PRT0_LUT_CTL6
SmartIO_1_cy_m0s8_prgio__LUT_CTL7 EQU CYREG_PRGIO_PRT0_LUT_CTL7
SmartIO_1_cy_m0s8_prgio__LUT_SEL0 EQU CYREG_PRGIO_PRT0_LUT_SEL0
SmartIO_1_cy_m0s8_prgio__LUT_SEL1 EQU CYREG_PRGIO_PRT0_LUT_SEL1
SmartIO_1_cy_m0s8_prgio__LUT_SEL2 EQU CYREG_PRGIO_PRT0_LUT_SEL2
SmartIO_1_cy_m0s8_prgio__LUT_SEL3 EQU CYREG_PRGIO_PRT0_LUT_SEL3
SmartIO_1_cy_m0s8_prgio__LUT_SEL4 EQU CYREG_PRGIO_PRT0_LUT_SEL4
SmartIO_1_cy_m0s8_prgio__LUT_SEL5 EQU CYREG_PRGIO_PRT0_LUT_SEL5
SmartIO_1_cy_m0s8_prgio__LUT_SEL6 EQU CYREG_PRGIO_PRT0_LUT_SEL6
SmartIO_1_cy_m0s8_prgio__LUT_SEL7 EQU CYREG_PRGIO_PRT0_LUT_SEL7
SmartIO_1_cy_m0s8_prgio__SYNC_CTL EQU CYREG_PRGIO_PRT0_SYNC_CTL

/* SmartIO_1_internalPin_i0 */
SmartIO_1_internalPin_i0__0__DR EQU CYREG_GPIO_PRT2_DR
SmartIO_1_internalPin_i0__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SmartIO_1_internalPin_i0__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SmartIO_1_internalPin_i0__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SmartIO_1_internalPin_i0__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
SmartIO_1_internalPin_i0__0__HSIOM_MASK EQU 0x0000000F
SmartIO_1_internalPin_i0__0__HSIOM_SHIFT EQU 0
SmartIO_1_internalPin_i0__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_i0__0__INTR EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_i0__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_i0__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_i0__0__MASK EQU 0x01
SmartIO_1_internalPin_i0__0__PC EQU CYREG_GPIO_PRT2_PC
SmartIO_1_internalPin_i0__0__PC2 EQU CYREG_GPIO_PRT2_PC2
SmartIO_1_internalPin_i0__0__PORT EQU 2
SmartIO_1_internalPin_i0__0__PS EQU CYREG_GPIO_PRT2_PS
SmartIO_1_internalPin_i0__0__SHIFT EQU 0
SmartIO_1_internalPin_i0__DR EQU CYREG_GPIO_PRT2_DR
SmartIO_1_internalPin_i0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SmartIO_1_internalPin_i0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SmartIO_1_internalPin_i0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SmartIO_1_internalPin_i0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_i0__INTR EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_i0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_i0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_i0__MASK EQU 0x01
SmartIO_1_internalPin_i0__PC EQU CYREG_GPIO_PRT2_PC
SmartIO_1_internalPin_i0__PC2 EQU CYREG_GPIO_PRT2_PC2
SmartIO_1_internalPin_i0__PORT EQU 2
SmartIO_1_internalPin_i0__PS EQU CYREG_GPIO_PRT2_PS
SmartIO_1_internalPin_i0__SHIFT EQU 0

/* SmartIO_1_internalPin_o7 */
SmartIO_1_internalPin_o7__0__DR EQU CYREG_GPIO_PRT2_DR
SmartIO_1_internalPin_o7__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SmartIO_1_internalPin_o7__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SmartIO_1_internalPin_o7__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SmartIO_1_internalPin_o7__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
SmartIO_1_internalPin_o7__0__HSIOM_MASK EQU 0xF0000000
SmartIO_1_internalPin_o7__0__HSIOM_SHIFT EQU 28
SmartIO_1_internalPin_o7__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_o7__0__INTR EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_o7__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_o7__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_o7__0__MASK EQU 0x80
SmartIO_1_internalPin_o7__0__PC EQU CYREG_GPIO_PRT2_PC
SmartIO_1_internalPin_o7__0__PC2 EQU CYREG_GPIO_PRT2_PC2
SmartIO_1_internalPin_o7__0__PORT EQU 2
SmartIO_1_internalPin_o7__0__PS EQU CYREG_GPIO_PRT2_PS
SmartIO_1_internalPin_o7__0__SHIFT EQU 7
SmartIO_1_internalPin_o7__DR EQU CYREG_GPIO_PRT2_DR
SmartIO_1_internalPin_o7__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SmartIO_1_internalPin_o7__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SmartIO_1_internalPin_o7__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SmartIO_1_internalPin_o7__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_o7__INTR EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_o7__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SmartIO_1_internalPin_o7__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SmartIO_1_internalPin_o7__MASK EQU 0x80
SmartIO_1_internalPin_o7__PC EQU CYREG_GPIO_PRT2_PC
SmartIO_1_internalPin_o7__PC2 EQU CYREG_GPIO_PRT2_PC2
SmartIO_1_internalPin_o7__PORT EQU 2
SmartIO_1_internalPin_o7__PS EQU CYREG_GPIO_PRT2_PS
SmartIO_1_internalPin_o7__SHIFT EQU 7

/* ADC_SAR_Seq_1_cy_psoc4_sar */
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG0
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG1
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG2
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG3
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG4
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG5
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG6
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG7
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG08 EQU CYREG_SAR_CHAN_CONFIG8
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG09 EQU CYREG_SAR_CHAN_CONFIG9
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG10 EQU CYREG_SAR_CHAN_CONFIG10
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG11 EQU CYREG_SAR_CHAN_CONFIG11
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG12 EQU CYREG_SAR_CHAN_CONFIG12
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG13 EQU CYREG_SAR_CHAN_CONFIG13
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG14 EQU CYREG_SAR_CHAN_CONFIG14
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG15 EQU CYREG_SAR_CHAN_CONFIG15
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT0
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT1
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT2
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT3
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT4
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT5
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT6
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT7
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT08 EQU CYREG_SAR_CHAN_RESULT8
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT09 EQU CYREG_SAR_CHAN_RESULT9
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT10 EQU CYREG_SAR_CHAN_RESULT10
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT11 EQU CYREG_SAR_CHAN_RESULT11
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT12 EQU CYREG_SAR_CHAN_RESULT12
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT13 EQU CYREG_SAR_CHAN_RESULT13
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT14 EQU CYREG_SAR_CHAN_RESULT14
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT15 EQU CYREG_SAR_CHAN_RESULT15
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK0
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK1
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK2
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK3
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK4
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK5
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK6
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK7
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK08 EQU CYREG_SAR_CHAN_WORK8
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK09 EQU CYREG_SAR_CHAN_WORK9
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK10 EQU CYREG_SAR_CHAN_WORK10
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK11 EQU CYREG_SAR_CHAN_WORK11
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK12 EQU CYREG_SAR_CHAN_WORK12
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK13 EQU CYREG_SAR_CHAN_WORK13
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK14 EQU CYREG_SAR_CHAN_WORK14
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK15 EQU CYREG_SAR_CHAN_WORK15
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_NUMBER EQU 0
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS
ADC_SAR_Seq_1_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING

/* ADC_SAR_Seq_1_intClock */
ADC_SAR_Seq_1_intClock__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL12
ADC_SAR_Seq_1_intClock__DIV_ID EQU 0x00000040
ADC_SAR_Seq_1_intClock__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
ADC_SAR_Seq_1_intClock__PA_DIV_ID EQU 0x000000FF

/* ADC_SAR_Seq_1_IRQ */
ADC_SAR_Seq_1_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
ADC_SAR_Seq_1_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
ADC_SAR_Seq_1_IRQ__INTC_MASK EQU 0x80000
ADC_SAR_Seq_1_IRQ__INTC_NUMBER EQU 19
ADC_SAR_Seq_1_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
ADC_SAR_Seq_1_IRQ__INTC_PRIOR_NUM EQU 3
ADC_SAR_Seq_1_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR4
ADC_SAR_Seq_1_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
ADC_SAR_Seq_1_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 12
CYDEV_CHIP_DIE_PSOC5LP EQU 19
CYDEV_CHIP_DIE_PSOC5TM EQU 20
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 4
CYDEV_CHIP_FAMILY_FM3 EQU 5
CYDEV_CHIP_FAMILY_FM4 EQU 6
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x1B0011AB
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 12
CYDEV_CHIP_MEMBER_4C EQU 18
CYDEV_CHIP_MEMBER_4D EQU 8
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 13
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 11
CYDEV_CHIP_MEMBER_4I EQU 17
CYDEV_CHIP_MEMBER_4J EQU 9
CYDEV_CHIP_MEMBER_4K EQU 10
CYDEV_CHIP_MEMBER_4L EQU 16
CYDEV_CHIP_MEMBER_4M EQU 15
CYDEV_CHIP_MEMBER_4N EQU 6
CYDEV_CHIP_MEMBER_4O EQU 5
CYDEV_CHIP_MEMBER_4P EQU 14
CYDEV_CHIP_MEMBER_4Q EQU 7
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 20
CYDEV_CHIP_MEMBER_5B EQU 19
CYDEV_CHIP_MEMBER_FM3 EQU 24
CYDEV_CHIP_MEMBER_FM4 EQU 25
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4K
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4K_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 8
CYDEV_DFT_SELECT_CLK1 EQU 9
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 1
CYIPBLOCK_m0s8cpussv3_VERSION EQU 1
CYIPBLOCK_m0s8csdv2_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8lpcomp_VERSION EQU 2
CYIPBLOCK_m0s8pass4a_VERSION EQU 1
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8wco_VERSION EQU 1
CYIPBLOCK_s8srsslt_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
