.ifndef INCLUDED_CYFITTERGNU_INC
.set INCLUDED_CYFITTERGNU_INC, 1
.include "cydevicegnu_trm.inc"

/* I2C_1_SCB */
.set I2C_1_SCB__CTRL, CYREG_SCB1_CTRL
.set I2C_1_SCB__EZ_DATA0, CYREG_SCB1_EZ_DATA0
.set I2C_1_SCB__EZ_DATA1, CYREG_SCB1_EZ_DATA1
.set I2C_1_SCB__EZ_DATA10, CYREG_SCB1_EZ_DATA10
.set I2C_1_SCB__EZ_DATA11, CYREG_SCB1_EZ_DATA11
.set I2C_1_SCB__EZ_DATA12, CYREG_SCB1_EZ_DATA12
.set I2C_1_SCB__EZ_DATA13, CYREG_SCB1_EZ_DATA13
.set I2C_1_SCB__EZ_DATA14, CYREG_SCB1_EZ_DATA14
.set I2C_1_SCB__EZ_DATA15, CYREG_SCB1_EZ_DATA15
.set I2C_1_SCB__EZ_DATA16, CYREG_SCB1_EZ_DATA16
.set I2C_1_SCB__EZ_DATA17, CYREG_SCB1_EZ_DATA17
.set I2C_1_SCB__EZ_DATA18, CYREG_SCB1_EZ_DATA18
.set I2C_1_SCB__EZ_DATA19, CYREG_SCB1_EZ_DATA19
.set I2C_1_SCB__EZ_DATA2, CYREG_SCB1_EZ_DATA2
.set I2C_1_SCB__EZ_DATA20, CYREG_SCB1_EZ_DATA20
.set I2C_1_SCB__EZ_DATA21, CYREG_SCB1_EZ_DATA21
.set I2C_1_SCB__EZ_DATA22, CYREG_SCB1_EZ_DATA22
.set I2C_1_SCB__EZ_DATA23, CYREG_SCB1_EZ_DATA23
.set I2C_1_SCB__EZ_DATA24, CYREG_SCB1_EZ_DATA24
.set I2C_1_SCB__EZ_DATA25, CYREG_SCB1_EZ_DATA25
.set I2C_1_SCB__EZ_DATA26, CYREG_SCB1_EZ_DATA26
.set I2C_1_SCB__EZ_DATA27, CYREG_SCB1_EZ_DATA27
.set I2C_1_SCB__EZ_DATA28, CYREG_SCB1_EZ_DATA28
.set I2C_1_SCB__EZ_DATA29, CYREG_SCB1_EZ_DATA29
.set I2C_1_SCB__EZ_DATA3, CYREG_SCB1_EZ_DATA3
.set I2C_1_SCB__EZ_DATA30, CYREG_SCB1_EZ_DATA30
.set I2C_1_SCB__EZ_DATA31, CYREG_SCB1_EZ_DATA31
.set I2C_1_SCB__EZ_DATA4, CYREG_SCB1_EZ_DATA4
.set I2C_1_SCB__EZ_DATA5, CYREG_SCB1_EZ_DATA5
.set I2C_1_SCB__EZ_DATA6, CYREG_SCB1_EZ_DATA6
.set I2C_1_SCB__EZ_DATA7, CYREG_SCB1_EZ_DATA7
.set I2C_1_SCB__EZ_DATA8, CYREG_SCB1_EZ_DATA8
.set I2C_1_SCB__EZ_DATA9, CYREG_SCB1_EZ_DATA9
.set I2C_1_SCB__I2C_CFG, CYREG_SCB1_I2C_CFG
.set I2C_1_SCB__I2C_CTRL, CYREG_SCB1_I2C_CTRL
.set I2C_1_SCB__I2C_M_CMD, CYREG_SCB1_I2C_M_CMD
.set I2C_1_SCB__I2C_S_CMD, CYREG_SCB1_I2C_S_CMD
.set I2C_1_SCB__I2C_STATUS, CYREG_SCB1_I2C_STATUS
.set I2C_1_SCB__INTR_CAUSE, CYREG_SCB1_INTR_CAUSE
.set I2C_1_SCB__INTR_I2C_EC, CYREG_SCB1_INTR_I2C_EC
.set I2C_1_SCB__INTR_I2C_EC_MASK, CYREG_SCB1_INTR_I2C_EC_MASK
.set I2C_1_SCB__INTR_I2C_EC_MASKED, CYREG_SCB1_INTR_I2C_EC_MASKED
.set I2C_1_SCB__INTR_M, CYREG_SCB1_INTR_M
.set I2C_1_SCB__INTR_M_MASK, CYREG_SCB1_INTR_M_MASK
.set I2C_1_SCB__INTR_M_MASKED, CYREG_SCB1_INTR_M_MASKED
.set I2C_1_SCB__INTR_M_SET, CYREG_SCB1_INTR_M_SET
.set I2C_1_SCB__INTR_RX, CYREG_SCB1_INTR_RX
.set I2C_1_SCB__INTR_RX_MASK, CYREG_SCB1_INTR_RX_MASK
.set I2C_1_SCB__INTR_RX_MASKED, CYREG_SCB1_INTR_RX_MASKED
.set I2C_1_SCB__INTR_RX_SET, CYREG_SCB1_INTR_RX_SET
.set I2C_1_SCB__INTR_S, CYREG_SCB1_INTR_S
.set I2C_1_SCB__INTR_S_MASK, CYREG_SCB1_INTR_S_MASK
.set I2C_1_SCB__INTR_S_MASKED, CYREG_SCB1_INTR_S_MASKED
.set I2C_1_SCB__INTR_S_SET, CYREG_SCB1_INTR_S_SET
.set I2C_1_SCB__INTR_SPI_EC, CYREG_SCB1_INTR_SPI_EC
.set I2C_1_SCB__INTR_SPI_EC_MASK, CYREG_SCB1_INTR_SPI_EC_MASK
.set I2C_1_SCB__INTR_SPI_EC_MASKED, CYREG_SCB1_INTR_SPI_EC_MASKED
.set I2C_1_SCB__INTR_TX, CYREG_SCB1_INTR_TX
.set I2C_1_SCB__INTR_TX_MASK, CYREG_SCB1_INTR_TX_MASK
.set I2C_1_SCB__INTR_TX_MASKED, CYREG_SCB1_INTR_TX_MASKED
.set I2C_1_SCB__INTR_TX_SET, CYREG_SCB1_INTR_TX_SET
.set I2C_1_SCB__RX_CTRL, CYREG_SCB1_RX_CTRL
.set I2C_1_SCB__RX_FIFO_CTRL, CYREG_SCB1_RX_FIFO_CTRL
.set I2C_1_SCB__RX_FIFO_RD, CYREG_SCB1_RX_FIFO_RD
.set I2C_1_SCB__RX_FIFO_RD_SILENT, CYREG_SCB1_RX_FIFO_RD_SILENT
.set I2C_1_SCB__RX_FIFO_STATUS, CYREG_SCB1_RX_FIFO_STATUS
.set I2C_1_SCB__RX_MATCH, CYREG_SCB1_RX_MATCH
.set I2C_1_SCB__SPI_CTRL, CYREG_SCB1_SPI_CTRL
.set I2C_1_SCB__SPI_STATUS, CYREG_SCB1_SPI_STATUS
.set I2C_1_SCB__SS0_POSISTION, 0
.set I2C_1_SCB__SS1_POSISTION, 1
.set I2C_1_SCB__SS2_POSISTION, 2
.set I2C_1_SCB__SS3_POSISTION, 3
.set I2C_1_SCB__STATUS, CYREG_SCB1_STATUS
.set I2C_1_SCB__TX_CTRL, CYREG_SCB1_TX_CTRL
.set I2C_1_SCB__TX_FIFO_CTRL, CYREG_SCB1_TX_FIFO_CTRL
.set I2C_1_SCB__TX_FIFO_STATUS, CYREG_SCB1_TX_FIFO_STATUS
.set I2C_1_SCB__TX_FIFO_WR, CYREG_SCB1_TX_FIFO_WR
.set I2C_1_SCB__UART_CTRL, CYREG_SCB1_UART_CTRL
.set I2C_1_SCB__UART_FLOW_CTRL, CYREG_SCB1_UART_FLOW_CTRL
.set I2C_1_SCB__UART_RX_CTRL, CYREG_SCB1_UART_RX_CTRL
.set I2C_1_SCB__UART_RX_STATUS, CYREG_SCB1_UART_RX_STATUS
.set I2C_1_SCB__UART_TX_CTRL, CYREG_SCB1_UART_TX_CTRL

/* I2C_1_SCB_IRQ */
.set I2C_1_SCB_IRQ__INTC_CLR_EN_REG, CYREG_CM0P_ICER
.set I2C_1_SCB_IRQ__INTC_CLR_PD_REG, CYREG_CM0P_ICPR
.set I2C_1_SCB_IRQ__INTC_MASK, 0x100
.set I2C_1_SCB_IRQ__INTC_NUMBER, 8
.set I2C_1_SCB_IRQ__INTC_PRIOR_MASK, 0xC0
.set I2C_1_SCB_IRQ__INTC_PRIOR_NUM, 3
.set I2C_1_SCB_IRQ__INTC_PRIOR_REG, CYREG_CM0P_IPR2
.set I2C_1_SCB_IRQ__INTC_SET_EN_REG, CYREG_CM0P_ISER
.set I2C_1_SCB_IRQ__INTC_SET_PD_REG, CYREG_CM0P_ISPR

/* I2C_1_SCBCLK */
.set I2C_1_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL1
.set I2C_1_SCBCLK__DIV_ID, 0x00000041
.set I2C_1_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL1
.set I2C_1_SCBCLK__PA_DIV_ID, 0x000000FF

/* I2C_1_scl */
.set I2C_1_scl__0__DR, CYREG_GPIO_PRT0_DR
.set I2C_1_scl__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set I2C_1_scl__0__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set I2C_1_scl__0__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set I2C_1_scl__0__HSIOM, CYREG_HSIOM_PORT_SEL0
.set I2C_1_scl__0__HSIOM_GPIO, 0
.set I2C_1_scl__0__HSIOM_I2C, 14
.set I2C_1_scl__0__HSIOM_I2C_SCL, 14
.set I2C_1_scl__0__HSIOM_MASK, 0x000F0000
.set I2C_1_scl__0__HSIOM_SHIFT, 16
.set I2C_1_scl__0__HSIOM_SPI, 15
.set I2C_1_scl__0__HSIOM_SPI_MOSI, 15
.set I2C_1_scl__0__HSIOM_UART, 9
.set I2C_1_scl__0__HSIOM_UART_RX, 9
.set I2C_1_scl__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_scl__0__INTR, CYREG_GPIO_PRT0_INTR
.set I2C_1_scl__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_scl__0__INTSTAT, CYREG_GPIO_PRT0_INTR
.set I2C_1_scl__0__MASK, 0x10
.set I2C_1_scl__0__PC, CYREG_GPIO_PRT0_PC
.set I2C_1_scl__0__PC2, CYREG_GPIO_PRT0_PC2
.set I2C_1_scl__0__PORT, 0
.set I2C_1_scl__0__PS, CYREG_GPIO_PRT0_PS
.set I2C_1_scl__0__SHIFT, 4
.set I2C_1_scl__DR, CYREG_GPIO_PRT0_DR
.set I2C_1_scl__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set I2C_1_scl__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set I2C_1_scl__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set I2C_1_scl__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_scl__INTR, CYREG_GPIO_PRT0_INTR
.set I2C_1_scl__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_scl__INTSTAT, CYREG_GPIO_PRT0_INTR
.set I2C_1_scl__MASK, 0x10
.set I2C_1_scl__PC, CYREG_GPIO_PRT0_PC
.set I2C_1_scl__PC2, CYREG_GPIO_PRT0_PC2
.set I2C_1_scl__PORT, 0
.set I2C_1_scl__PS, CYREG_GPIO_PRT0_PS
.set I2C_1_scl__SHIFT, 4

/* I2C_1_sda */
.set I2C_1_sda__0__DR, CYREG_GPIO_PRT0_DR
.set I2C_1_sda__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set I2C_1_sda__0__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set I2C_1_sda__0__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set I2C_1_sda__0__HSIOM, CYREG_HSIOM_PORT_SEL0
.set I2C_1_sda__0__HSIOM_GPIO, 0
.set I2C_1_sda__0__HSIOM_I2C, 14
.set I2C_1_sda__0__HSIOM_I2C_SDA, 14
.set I2C_1_sda__0__HSIOM_MASK, 0x00F00000
.set I2C_1_sda__0__HSIOM_SHIFT, 20
.set I2C_1_sda__0__HSIOM_SPI, 15
.set I2C_1_sda__0__HSIOM_SPI_MISO, 15
.set I2C_1_sda__0__HSIOM_UART, 9
.set I2C_1_sda__0__HSIOM_UART_TX, 9
.set I2C_1_sda__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_sda__0__INTR, CYREG_GPIO_PRT0_INTR
.set I2C_1_sda__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_sda__0__INTSTAT, CYREG_GPIO_PRT0_INTR
.set I2C_1_sda__0__MASK, 0x20
.set I2C_1_sda__0__PC, CYREG_GPIO_PRT0_PC
.set I2C_1_sda__0__PC2, CYREG_GPIO_PRT0_PC2
.set I2C_1_sda__0__PORT, 0
.set I2C_1_sda__0__PS, CYREG_GPIO_PRT0_PS
.set I2C_1_sda__0__SHIFT, 5
.set I2C_1_sda__DR, CYREG_GPIO_PRT0_DR
.set I2C_1_sda__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set I2C_1_sda__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set I2C_1_sda__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set I2C_1_sda__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_sda__INTR, CYREG_GPIO_PRT0_INTR
.set I2C_1_sda__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set I2C_1_sda__INTSTAT, CYREG_GPIO_PRT0_INTR
.set I2C_1_sda__MASK, 0x20
.set I2C_1_sda__PC, CYREG_GPIO_PRT0_PC
.set I2C_1_sda__PC2, CYREG_GPIO_PRT0_PC2
.set I2C_1_sda__PORT, 0
.set I2C_1_sda__PS, CYREG_GPIO_PRT0_PS
.set I2C_1_sda__SHIFT, 5

/* Pin_1 */
.set Pin_1__0__DR, CYREG_GPIO_PRT2_DR
.set Pin_1__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set Pin_1__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set Pin_1__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set Pin_1__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set Pin_1__0__HSIOM_MASK, 0x000F0000
.set Pin_1__0__HSIOM_SHIFT, 16
.set Pin_1__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_1__0__INTR, CYREG_GPIO_PRT2_INTR
.set Pin_1__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_1__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set Pin_1__0__MASK, 0x10
.set Pin_1__0__PC, CYREG_GPIO_PRT2_PC
.set Pin_1__0__PC2, CYREG_GPIO_PRT2_PC2
.set Pin_1__0__PORT, 2
.set Pin_1__0__PS, CYREG_GPIO_PRT2_PS
.set Pin_1__0__SHIFT, 4
.set Pin_1__DR, CYREG_GPIO_PRT2_DR
.set Pin_1__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set Pin_1__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set Pin_1__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set Pin_1__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_1__INTR, CYREG_GPIO_PRT2_INTR
.set Pin_1__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_1__INTSTAT, CYREG_GPIO_PRT2_INTR
.set Pin_1__MASK, 0x10
.set Pin_1__PC, CYREG_GPIO_PRT2_PC
.set Pin_1__PC2, CYREG_GPIO_PRT2_PC2
.set Pin_1__PORT, 2
.set Pin_1__PS, CYREG_GPIO_PRT2_PS
.set Pin_1__SHIFT, 4

/* Pin_2 */
.set Pin_2__0__DR, CYREG_GPIO_PRT2_DR
.set Pin_2__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set Pin_2__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set Pin_2__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set Pin_2__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set Pin_2__0__HSIOM_MASK, 0x00F00000
.set Pin_2__0__HSIOM_SHIFT, 20
.set Pin_2__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_2__0__INTR, CYREG_GPIO_PRT2_INTR
.set Pin_2__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_2__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set Pin_2__0__MASK, 0x20
.set Pin_2__0__PC, CYREG_GPIO_PRT2_PC
.set Pin_2__0__PC2, CYREG_GPIO_PRT2_PC2
.set Pin_2__0__PORT, 2
.set Pin_2__0__PS, CYREG_GPIO_PRT2_PS
.set Pin_2__0__SHIFT, 5
.set Pin_2__DR, CYREG_GPIO_PRT2_DR
.set Pin_2__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set Pin_2__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set Pin_2__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set Pin_2__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_2__INTR, CYREG_GPIO_PRT2_INTR
.set Pin_2__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set Pin_2__INTSTAT, CYREG_GPIO_PRT2_INTR
.set Pin_2__MASK, 0x20
.set Pin_2__PC, CYREG_GPIO_PRT2_PC
.set Pin_2__PC2, CYREG_GPIO_PRT2_PC2
.set Pin_2__PORT, 2
.set Pin_2__PS, CYREG_GPIO_PRT2_PS
.set Pin_2__SHIFT, 5

/* SmartIO_1_cy_m0s8_prgio */
.set SmartIO_1_cy_m0s8_prgio__CTL, CYREG_PRGIO_PRT0_CTL
.set SmartIO_1_cy_m0s8_prgio__DATA, CYREG_PRGIO_PRT0_DATA
.set SmartIO_1_cy_m0s8_prgio__DU_CTL, CYREG_PRGIO_PRT0_DU_CTL
.set SmartIO_1_cy_m0s8_prgio__DU_SEL, CYREG_PRGIO_PRT0_DU_SEL
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL0, CYREG_PRGIO_PRT0_LUT_CTL0
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL1, CYREG_PRGIO_PRT0_LUT_CTL1
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL2, CYREG_PRGIO_PRT0_LUT_CTL2
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL3, CYREG_PRGIO_PRT0_LUT_CTL3
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL4, CYREG_PRGIO_PRT0_LUT_CTL4
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL5, CYREG_PRGIO_PRT0_LUT_CTL5
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL6, CYREG_PRGIO_PRT0_LUT_CTL6
.set SmartIO_1_cy_m0s8_prgio__LUT_CTL7, CYREG_PRGIO_PRT0_LUT_CTL7
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL0, CYREG_PRGIO_PRT0_LUT_SEL0
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL1, CYREG_PRGIO_PRT0_LUT_SEL1
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL2, CYREG_PRGIO_PRT0_LUT_SEL2
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL3, CYREG_PRGIO_PRT0_LUT_SEL3
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL4, CYREG_PRGIO_PRT0_LUT_SEL4
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL5, CYREG_PRGIO_PRT0_LUT_SEL5
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL6, CYREG_PRGIO_PRT0_LUT_SEL6
.set SmartIO_1_cy_m0s8_prgio__LUT_SEL7, CYREG_PRGIO_PRT0_LUT_SEL7
.set SmartIO_1_cy_m0s8_prgio__SYNC_CTL, CYREG_PRGIO_PRT0_SYNC_CTL

/* SmartIO_1_internalPin_i0 */
.set SmartIO_1_internalPin_i0__0__DR, CYREG_GPIO_PRT2_DR
.set SmartIO_1_internalPin_i0__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SmartIO_1_internalPin_i0__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SmartIO_1_internalPin_i0__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SmartIO_1_internalPin_i0__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set SmartIO_1_internalPin_i0__0__HSIOM_MASK, 0x0000000F
.set SmartIO_1_internalPin_i0__0__HSIOM_SHIFT, 0
.set SmartIO_1_internalPin_i0__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_i0__0__INTR, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_i0__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_i0__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_i0__0__MASK, 0x01
.set SmartIO_1_internalPin_i0__0__PC, CYREG_GPIO_PRT2_PC
.set SmartIO_1_internalPin_i0__0__PC2, CYREG_GPIO_PRT2_PC2
.set SmartIO_1_internalPin_i0__0__PORT, 2
.set SmartIO_1_internalPin_i0__0__PS, CYREG_GPIO_PRT2_PS
.set SmartIO_1_internalPin_i0__0__SHIFT, 0
.set SmartIO_1_internalPin_i0__DR, CYREG_GPIO_PRT2_DR
.set SmartIO_1_internalPin_i0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SmartIO_1_internalPin_i0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SmartIO_1_internalPin_i0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SmartIO_1_internalPin_i0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_i0__INTR, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_i0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_i0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_i0__MASK, 0x01
.set SmartIO_1_internalPin_i0__PC, CYREG_GPIO_PRT2_PC
.set SmartIO_1_internalPin_i0__PC2, CYREG_GPIO_PRT2_PC2
.set SmartIO_1_internalPin_i0__PORT, 2
.set SmartIO_1_internalPin_i0__PS, CYREG_GPIO_PRT2_PS
.set SmartIO_1_internalPin_i0__SHIFT, 0

/* SmartIO_1_internalPin_o7 */
.set SmartIO_1_internalPin_o7__0__DR, CYREG_GPIO_PRT2_DR
.set SmartIO_1_internalPin_o7__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SmartIO_1_internalPin_o7__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SmartIO_1_internalPin_o7__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SmartIO_1_internalPin_o7__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set SmartIO_1_internalPin_o7__0__HSIOM_MASK, 0xF0000000
.set SmartIO_1_internalPin_o7__0__HSIOM_SHIFT, 28
.set SmartIO_1_internalPin_o7__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_o7__0__INTR, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_o7__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_o7__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_o7__0__MASK, 0x80
.set SmartIO_1_internalPin_o7__0__PC, CYREG_GPIO_PRT2_PC
.set SmartIO_1_internalPin_o7__0__PC2, CYREG_GPIO_PRT2_PC2
.set SmartIO_1_internalPin_o7__0__PORT, 2
.set SmartIO_1_internalPin_o7__0__PS, CYREG_GPIO_PRT2_PS
.set SmartIO_1_internalPin_o7__0__SHIFT, 7
.set SmartIO_1_internalPin_o7__DR, CYREG_GPIO_PRT2_DR
.set SmartIO_1_internalPin_o7__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SmartIO_1_internalPin_o7__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SmartIO_1_internalPin_o7__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SmartIO_1_internalPin_o7__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_o7__INTR, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_o7__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SmartIO_1_internalPin_o7__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SmartIO_1_internalPin_o7__MASK, 0x80
.set SmartIO_1_internalPin_o7__PC, CYREG_GPIO_PRT2_PC
.set SmartIO_1_internalPin_o7__PC2, CYREG_GPIO_PRT2_PC2
.set SmartIO_1_internalPin_o7__PORT, 2
.set SmartIO_1_internalPin_o7__PS, CYREG_GPIO_PRT2_PS
.set SmartIO_1_internalPin_o7__SHIFT, 7

/* ADC_SAR_Seq_1_cy_psoc4_sar */
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_ANA_TRIM, CYREG_SAR_ANA_TRIM
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG00, CYREG_SAR_CHAN_CONFIG0
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG01, CYREG_SAR_CHAN_CONFIG1
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG02, CYREG_SAR_CHAN_CONFIG2
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG03, CYREG_SAR_CHAN_CONFIG3
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG04, CYREG_SAR_CHAN_CONFIG4
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG05, CYREG_SAR_CHAN_CONFIG5
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG06, CYREG_SAR_CHAN_CONFIG6
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG07, CYREG_SAR_CHAN_CONFIG7
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG08, CYREG_SAR_CHAN_CONFIG8
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG09, CYREG_SAR_CHAN_CONFIG9
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG10, CYREG_SAR_CHAN_CONFIG10
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG11, CYREG_SAR_CHAN_CONFIG11
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG12, CYREG_SAR_CHAN_CONFIG12
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG13, CYREG_SAR_CHAN_CONFIG13
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG14, CYREG_SAR_CHAN_CONFIG14
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_CONFIG15, CYREG_SAR_CHAN_CONFIG15
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_EN, CYREG_SAR_CHAN_EN
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT_VALID, CYREG_SAR_CHAN_RESULT_VALID
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT00, CYREG_SAR_CHAN_RESULT0
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT01, CYREG_SAR_CHAN_RESULT1
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT02, CYREG_SAR_CHAN_RESULT2
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT03, CYREG_SAR_CHAN_RESULT3
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT04, CYREG_SAR_CHAN_RESULT4
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT05, CYREG_SAR_CHAN_RESULT5
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT06, CYREG_SAR_CHAN_RESULT6
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT07, CYREG_SAR_CHAN_RESULT7
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT08, CYREG_SAR_CHAN_RESULT8
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT09, CYREG_SAR_CHAN_RESULT9
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT10, CYREG_SAR_CHAN_RESULT10
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT11, CYREG_SAR_CHAN_RESULT11
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT12, CYREG_SAR_CHAN_RESULT12
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT13, CYREG_SAR_CHAN_RESULT13
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT14, CYREG_SAR_CHAN_RESULT14
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_RESULT15, CYREG_SAR_CHAN_RESULT15
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK_VALID, CYREG_SAR_CHAN_WORK_VALID
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK00, CYREG_SAR_CHAN_WORK0
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK01, CYREG_SAR_CHAN_WORK1
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK02, CYREG_SAR_CHAN_WORK2
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK03, CYREG_SAR_CHAN_WORK3
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK04, CYREG_SAR_CHAN_WORK4
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK05, CYREG_SAR_CHAN_WORK5
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK06, CYREG_SAR_CHAN_WORK6
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK07, CYREG_SAR_CHAN_WORK7
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK08, CYREG_SAR_CHAN_WORK8
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK09, CYREG_SAR_CHAN_WORK9
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK10, CYREG_SAR_CHAN_WORK10
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK11, CYREG_SAR_CHAN_WORK11
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK12, CYREG_SAR_CHAN_WORK12
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK13, CYREG_SAR_CHAN_WORK13
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK14, CYREG_SAR_CHAN_WORK14
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CHAN_WORK15, CYREG_SAR_CHAN_WORK15
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_CTRL, CYREG_SAR_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_DFT_CTRL, CYREG_SAR_DFT_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR, CYREG_SAR_INTR
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_CAUSE, CYREG_SAR_INTR_CAUSE
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASK, CYREG_SAR_INTR_MASK
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_MASKED, CYREG_SAR_INTR_MASKED
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_INTR_SET, CYREG_SAR_INTR_SET
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL, CYREG_SAR_MUX_SWITCH_HW_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_MUX_SWITCH0, CYREG_SAR_MUX_SWITCH0
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_NUMBER, 0
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_PUMP_CTRL, CYREG_SAR_PUMP_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_COND, CYREG_SAR_RANGE_COND
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR, CYREG_SAR_RANGE_INTR
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASK, CYREG_SAR_RANGE_INTR_MASK
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_MASKED, CYREG_SAR_RANGE_INTR_MASKED
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_INTR_SET, CYREG_SAR_RANGE_INTR_SET
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_RANGE_THRES, CYREG_SAR_RANGE_THRES
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_CTRL, CYREG_SAR_SAMPLE_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME01, CYREG_SAR_SAMPLE_TIME01
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SAMPLE_TIME23, CYREG_SAR_SAMPLE_TIME23
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR, CYREG_SAR_SATURATE_INTR
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASK, CYREG_SAR_SATURATE_INTR_MASK
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED, CYREG_SAR_SATURATE_INTR_MASKED
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_SATURATE_INTR_SET, CYREG_SAR_SATURATE_INTR_SET
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_START_CTRL, CYREG_SAR_START_CTRL
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_STATUS, CYREG_SAR_STATUS
.set ADC_SAR_Seq_1_cy_psoc4_sar__SAR_WOUNDING, CYREG_SAR_WOUNDING

/* ADC_SAR_Seq_1_intClock */
.set ADC_SAR_Seq_1_intClock__CTRL_REGISTER, CYREG_PERI_PCLK_CTL12
.set ADC_SAR_Seq_1_intClock__DIV_ID, 0x00000040
.set ADC_SAR_Seq_1_intClock__DIV_REGISTER, CYREG_PERI_DIV_16_CTL0
.set ADC_SAR_Seq_1_intClock__PA_DIV_ID, 0x000000FF

/* ADC_SAR_Seq_1_IRQ */
.set ADC_SAR_Seq_1_IRQ__INTC_CLR_EN_REG, CYREG_CM0P_ICER
.set ADC_SAR_Seq_1_IRQ__INTC_CLR_PD_REG, CYREG_CM0P_ICPR
.set ADC_SAR_Seq_1_IRQ__INTC_MASK, 0x80000
.set ADC_SAR_Seq_1_IRQ__INTC_NUMBER, 19
.set ADC_SAR_Seq_1_IRQ__INTC_PRIOR_MASK, 0xC0000000
.set ADC_SAR_Seq_1_IRQ__INTC_PRIOR_NUM, 3
.set ADC_SAR_Seq_1_IRQ__INTC_PRIOR_REG, CYREG_CM0P_IPR4
.set ADC_SAR_Seq_1_IRQ__INTC_SET_EN_REG, CYREG_CM0P_ISER
.set ADC_SAR_Seq_1_IRQ__INTC_SET_PD_REG, CYREG_CM0P_ISPR

/* Miscellaneous */
.set CYDEV_BCLK__HFCLK__HZ, 24000000
.set CYDEV_BCLK__HFCLK__KHZ, 24000
.set CYDEV_BCLK__HFCLK__MHZ, 24
.set CYDEV_BCLK__SYSCLK__HZ, 24000000
.set CYDEV_BCLK__SYSCLK__KHZ, 24000
.set CYDEV_BCLK__SYSCLK__MHZ, 24
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PSOC4A, 12
.set CYDEV_CHIP_DIE_PSOC5LP, 19
.set CYDEV_CHIP_DIE_PSOC5TM, 20
.set CYDEV_CHIP_DIE_TMA4, 2
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_FM0P, 4
.set CYDEV_CHIP_FAMILY_FM3, 5
.set CYDEV_CHIP_FAMILY_FM4, 6
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4
.set CYDEV_CHIP_JTAG_ID, 0x1B0011AB
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 12
.set CYDEV_CHIP_MEMBER_4C, 18
.set CYDEV_CHIP_MEMBER_4D, 8
.set CYDEV_CHIP_MEMBER_4E, 4
.set CYDEV_CHIP_MEMBER_4F, 13
.set CYDEV_CHIP_MEMBER_4G, 2
.set CYDEV_CHIP_MEMBER_4H, 11
.set CYDEV_CHIP_MEMBER_4I, 17
.set CYDEV_CHIP_MEMBER_4J, 9
.set CYDEV_CHIP_MEMBER_4K, 10
.set CYDEV_CHIP_MEMBER_4L, 16
.set CYDEV_CHIP_MEMBER_4M, 15
.set CYDEV_CHIP_MEMBER_4N, 6
.set CYDEV_CHIP_MEMBER_4O, 5
.set CYDEV_CHIP_MEMBER_4P, 14
.set CYDEV_CHIP_MEMBER_4Q, 7
.set CYDEV_CHIP_MEMBER_4U, 3
.set CYDEV_CHIP_MEMBER_5A, 20
.set CYDEV_CHIP_MEMBER_5B, 19
.set CYDEV_CHIP_MEMBER_FM3, 24
.set CYDEV_CHIP_MEMBER_FM4, 25
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4K
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1
.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1
.set CYDEV_CHIP_REV_TMA4_ES, 17
.set CYDEV_CHIP_REV_TMA4_ES2, 33
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
.set CYDEV_CHIP_REVISION_4G_ES, 17
.set CYDEV_CHIP_REVISION_4G_ES2, 33
.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4K_PRODUCTION
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
.set CYDEV_CONFIG_READ_ACCELERATOR, 1
.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_Disallowed
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_PROTECT_KILL, 4
.set CYDEV_DEBUG_PROTECT_OPEN, 1
.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN
.set CYDEV_DEBUG_PROTECT_PROTECTED, 2
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DFT_SELECT_CLK0, 8
.set CYDEV_DFT_SELECT_CLK1, 9
.set CYDEV_HEAP_SIZE, 0x80
.set CYDEV_IMO_TRIMMED_BY_USB, 0
.set CYDEV_IMO_TRIMMED_BY_WCO, 0
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_STACK_SIZE, 0x0800
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 1
.set CYDEV_VDDA_MV, 3300
.set CYDEV_VDDD_MV, 3300
.set CYDEV_WDT_GENERATE_ISR, 1
.set CYIPBLOCK_m0s8cpussv3_VERSION, 1
.set CYIPBLOCK_m0s8csdv2_VERSION, 1
.set CYIPBLOCK_m0s8ioss_VERSION, 1
.set CYIPBLOCK_m0s8lcd_VERSION, 2
.set CYIPBLOCK_m0s8lpcomp_VERSION, 2
.set CYIPBLOCK_m0s8pass4a_VERSION, 1
.set CYIPBLOCK_m0s8peri_VERSION, 1
.set CYIPBLOCK_m0s8scb_VERSION, 2
.set CYIPBLOCK_m0s8tcpwm_VERSION, 2
.set CYIPBLOCK_m0s8wco_VERSION, 1
.set CYIPBLOCK_s8srsslt_VERSION, 1
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
