ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 1


   1              		.cpu cortex-m0plus
   2              		.fpu softvfp
   3              		.eabi_attribute 20, 1
   4              		.eabi_attribute 21, 1
   5              		.eabi_attribute 23, 3
   6              		.eabi_attribute 24, 1
   7              		.eabi_attribute 25, 1
   8              		.eabi_attribute 26, 1
   9              		.eabi_attribute 30, 1
  10              		.eabi_attribute 34, 0
  11              		.eabi_attribute 18, 4
  12              		.code	16
  13              		.file	"ADC_SAR_Seq_1_intClock.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.ADC_SAR_Seq_1_intClock_StartEx,"ax",%progbits
  18              		.align	2
  19              		.global	ADC_SAR_Seq_1_intClock_StartEx
  20              		.code	16
  21              		.thumb_func
  22              		.type	ADC_SAR_Seq_1_intClock_StartEx, %function
  23              	ADC_SAR_Seq_1_intClock_StartEx:
  24              	.LFB0:
  25              		.file 1 "Generated_Source\\PSoC4\\ADC_SAR_Seq_1_intClock.c"
   1:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
   2:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * File Name: ADC_SAR_Seq_1_intClock.c
   3:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Version 2.20
   4:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
   5:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Description:
   6:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *   Provides system API for the clocking, interrupts and watchdog timer.
   7:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
   8:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Note:
   9:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *   Documentation of the API's in this file is located in the
  10:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *   System Reference Guide provided with PSoC Creator.
  11:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  12:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
  13:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
  14:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * You may use this file only in accordance with the license, terms, conditions,
  15:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * disclaimers, and limitations in the end user license agreement accompanying
  16:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * the software package with which this file was provided.
  17:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
  18:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  19:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #include <cydevice_trm.h>
  20:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #include "ADC_SAR_Seq_1_intClock.h"
  21:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  22:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #if defined CYREG_PERI_DIV_CMD
  23:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  24:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
  25:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_StartEx
  26:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
  27:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  28:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
  29:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Starts the clock, aligned to the specified running clock.
  30:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  31:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
  32:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  alignClkDiv:  The divider to which phase alignment is performed when the
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 2


  33:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *    clock is started.
  34:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  35:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
  36:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
  37:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  38:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
  39:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** void ADC_SAR_Seq_1_intClock_StartEx(uint32 alignClkDiv)
  40:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
  26              		.loc 1 40 0
  27              		.cfi_startproc
  28              	.LVL0:
  29              	.L2:
  41:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Make sure any previous start command has finished. */
  42:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     while((ADC_SAR_Seq_1_intClock_CMD_REG & ADC_SAR_Seq_1_intClock_CMD_ENABLE_MASK) != 0u)
  30              		.loc 1 42 0 discriminator 1
  31 0000 044B     		ldr	r3, .L3
  32 0002 1B68     		ldr	r3, [r3]
  33 0004 002B     		cmp	r3, #0
  34 0006 FBDB     		blt	.L2
  43:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     {
  44:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     }
  45:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
  46:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Specify the target divider and it's alignment divider, and enable. */
  47:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     ADC_SAR_Seq_1_intClock_CMD_REG =
  48:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)ADC_SAR_Seq_1_intClock__DIV_ID << ADC_SAR_Seq_1_intClock_CMD_DIV_SHIFT)|
  49:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         (alignClkDiv << ADC_SAR_Seq_1_intClock_CMD_PA_DIV_SHIFT) |
  35              		.loc 1 49 0
  36 0008 0002     		lsl	r0, r0, #8
  37              	.LVL1:
  38 000a 034B     		ldr	r3, .L3+4
  39 000c 1843     		orr	r0, r3
  47:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)ADC_SAR_Seq_1_intClock__DIV_ID << ADC_SAR_Seq_1_intClock_CMD_DIV_SHIFT)|
  40              		.loc 1 47 0
  41 000e 014B     		ldr	r3, .L3
  42 0010 1860     		str	r0, [r3]
  50:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         (uint32)ADC_SAR_Seq_1_intClock_CMD_ENABLE_MASK;
  51:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
  43              		.loc 1 51 0
  44              		@ sp needed
  45 0012 7047     		bx	lr
  46              	.L4:
  47              		.align	2
  48              	.L3:
  49 0014 00000140 		.word	1073807360
  50 0018 40000080 		.word	-2147483584
  51              		.cfi_endproc
  52              	.LFE0:
  53              		.size	ADC_SAR_Seq_1_intClock_StartEx, .-ADC_SAR_Seq_1_intClock_StartEx
  54              		.section	.text.ADC_SAR_Seq_1_intClock_Stop,"ax",%progbits
  55              		.align	2
  56              		.global	ADC_SAR_Seq_1_intClock_Stop
  57              		.code	16
  58              		.thumb_func
  59              		.type	ADC_SAR_Seq_1_intClock_Stop, %function
  60              	ADC_SAR_Seq_1_intClock_Stop:
  61              	.LFB1:
  52:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 3


  53:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #else
  54:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  55:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
  56:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_Start
  57:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
  58:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  59:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
  60:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Starts the clock.
  61:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  62:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
  63:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
  64:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  65:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
  66:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
  67:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  68:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
  69:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  70:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** void ADC_SAR_Seq_1_intClock_Start(void)
  71:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
  72:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Set the bit to enable the clock. */
  73:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     ADC_SAR_Seq_1_intClock_ENABLE_REG |= ADC_SAR_Seq_1_intClock__ENABLE_MASK;
  74:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
  75:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  76:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #endif /* CYREG_PERI_DIV_CMD */
  77:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  78:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  79:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
  80:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_Stop
  81:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
  82:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  83:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
  84:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Stops the clock and returns immediately. This API does not require the
  85:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  source clock to be running but may return before the hardware is actually
  86:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  disabled.
  87:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  88:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
  89:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
  90:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  91:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
  92:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
  93:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
  94:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
  95:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** void ADC_SAR_Seq_1_intClock_Stop(void)
  96:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
  62              		.loc 1 96 0
  63              		.cfi_startproc
  64              	.L6:
  97:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #if defined CYREG_PERI_DIV_CMD
  98:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
  99:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Make sure any previous start command has finished. */
 100:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     while((ADC_SAR_Seq_1_intClock_CMD_REG & ADC_SAR_Seq_1_intClock_CMD_ENABLE_MASK) != 0u)
  65              		.loc 1 100 0 discriminator 1
  66 0000 034B     		ldr	r3, .L7
  67 0002 1B68     		ldr	r3, [r3]
  68 0004 002B     		cmp	r3, #0
  69 0006 FBDB     		blt	.L6
 101:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     {
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 4


 102:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     }
 103:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 104:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Specify the target divider and it's alignment divider, and disable. */
 105:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     ADC_SAR_Seq_1_intClock_CMD_REG =
  70              		.loc 1 105 0
  71 0008 024A     		ldr	r2, .L7+4
  72 000a 014B     		ldr	r3, .L7
  73 000c 1A60     		str	r2, [r3]
 106:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)ADC_SAR_Seq_1_intClock__DIV_ID << ADC_SAR_Seq_1_intClock_CMD_DIV_SHIFT)|
 107:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)ADC_SAR_Seq_1_intClock_CMD_DISABLE_MASK);
 108:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 109:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #else
 110:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 111:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* Clear the bit to disable the clock. */
 112:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     ADC_SAR_Seq_1_intClock_ENABLE_REG &= (uint32)(~ADC_SAR_Seq_1_intClock__ENABLE_MASK);
 113:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 114:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #endif /* CYREG_PERI_DIV_CMD */
 115:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
  74              		.loc 1 115 0
  75              		@ sp needed
  76 000e 7047     		bx	lr
  77              	.L8:
  78              		.align	2
  79              	.L7:
  80 0010 00000140 		.word	1073807360
  81 0014 40000040 		.word	1073741888
  82              		.cfi_endproc
  83              	.LFE1:
  84              		.size	ADC_SAR_Seq_1_intClock_Stop, .-ADC_SAR_Seq_1_intClock_Stop
  85              		.section	.text.ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister,"ax",%progbits
  86              		.align	2
  87              		.global	ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister
  88              		.code	16
  89              		.thumb_func
  90              		.type	ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister, %function
  91              	ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister:
  92              	.LFB2:
 116:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 117:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 118:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
 119:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister
 120:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
 121:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 122:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
 123:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Modifies the clock divider and the fractional divider.
 124:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 125:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
 126:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  clkDivider:  Divider register value (0-65535). This value is NOT the
 127:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *    divider; the clock hardware divides by clkDivider plus one. For example,
 128:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *    to divide the clock by 2, this parameter should be set to 1.
 129:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  fracDivider:  Fractional Divider register value (0-31).
 130:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
 131:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
 132:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 133:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
 134:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** void ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional)
 135:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 5


  93              		.loc 1 135 0
  94              		.cfi_startproc
  95              	.LVL2:
  96 0000 10B5     		push	{r4, lr}
  97              		.cfi_def_cfa_offset 8
  98              		.cfi_offset 4, -8
  99              		.cfi_offset 14, -4
 136:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     uint32 maskVal;
 137:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     uint32 regVal;
 138:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 139:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #if defined (ADC_SAR_Seq_1_intClock__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD)
 140:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 141:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 	/* get all but divider bits */
 142:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     maskVal = ADC_SAR_Seq_1_intClock_DIV_REG & 
 100              		.loc 1 142 0
 101 0002 064A     		ldr	r2, .L10
 102 0004 1368     		ldr	r3, [r2]
 103 0006 0724     		mov	r4, #7
 104 0008 2340     		and	r3, r4
 105              	.LVL3:
 143:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****                     (uint32)(~(uint32)(ADC_SAR_Seq_1_intClock_DIV_INT_MASK | ADC_SAR_Seq_1_intClock
 144:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 	/* combine mask and new divider vals into 32-bit value */
 145:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     regVal = maskVal |
 146:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)((uint32)clkDivider <<  ADC_SAR_Seq_1_intClock_DIV_INT_SHIFT) & ADC_SAR_Seq_1_intC
 106              		.loc 1 146 0
 107 000a 0002     		lsl	r0, r0, #8
 108              	.LVL4:
 145:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)((uint32)clkDivider <<  ADC_SAR_Seq_1_intClock_DIV_INT_SHIFT) & ADC_SAR_Seq_1_intC
 109              		.loc 1 145 0
 110 000c 1843     		orr	r0, r3
 147:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)((uint32)clkFractional << ADC_SAR_Seq_1_intClock_DIV_FRAC_SHIFT) & ADC_SAR_Seq_1_i
 111              		.loc 1 147 0
 112 000e CB00     		lsl	r3, r1, #3
 113              	.LVL5:
 114 0010 FF21     		mov	r1, #255
 115              	.LVL6:
 116 0012 1940     		and	r1, r3
 145:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         ((uint32)((uint32)clkDivider <<  ADC_SAR_Seq_1_intClock_DIV_INT_SHIFT) & ADC_SAR_Seq_1_intC
 117              		.loc 1 145 0
 118 0014 0143     		orr	r1, r0
 119              	.LVL7:
 148:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 149:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #else
 150:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* get all but integer divider bits */
 151:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     maskVal = ADC_SAR_Seq_1_intClock_DIV_REG & (uint32)(~(uint32)ADC_SAR_Seq_1_intClock__DIVIDER_MA
 152:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* combine mask and new divider val into 32-bit value */
 153:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     regVal = clkDivider | maskVal;
 154:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     
 155:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #endif /* ADC_SAR_Seq_1_intClock__FRAC_MASK || CYREG_PERI_DIV_CMD */
 156:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 157:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     ADC_SAR_Seq_1_intClock_DIV_REG = regVal;
 120              		.loc 1 157 0
 121 0016 1160     		str	r1, [r2]
 158:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
 122              		.loc 1 158 0
 123              		@ sp needed
 124 0018 10BD     		pop	{r4, pc}
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 6


 125              	.L11:
 126 001a C046     		.align	2
 127              	.L10:
 128 001c 00030140 		.word	1073808128
 129              		.cfi_endproc
 130              	.LFE2:
 131              		.size	ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister, .-ADC_SAR_Seq_1_intClock_SetFractionalD
 132              		.section	.text.ADC_SAR_Seq_1_intClock_GetDividerRegister,"ax",%progbits
 133              		.align	2
 134              		.global	ADC_SAR_Seq_1_intClock_GetDividerRegister
 135              		.code	16
 136              		.thumb_func
 137              		.type	ADC_SAR_Seq_1_intClock_GetDividerRegister, %function
 138              	ADC_SAR_Seq_1_intClock_GetDividerRegister:
 139              	.LFB3:
 159:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 160:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 161:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
 162:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_GetDividerRegister
 163:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
 164:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 165:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
 166:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Gets the clock divider register value.
 167:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 168:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
 169:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
 170:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 171:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
 172:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Divide value of the clock minus 1. For example, if the clock is set to
 173:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  divide by 2, the return value will be 1.
 174:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 175:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
 176:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** uint16 ADC_SAR_Seq_1_intClock_GetDividerRegister(void)
 177:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
 140              		.loc 1 177 0
 141              		.cfi_startproc
 178:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     return (uint16)((ADC_SAR_Seq_1_intClock_DIV_REG & ADC_SAR_Seq_1_intClock_DIV_INT_MASK)
 142              		.loc 1 178 0
 143 0000 024B     		ldr	r3, .L13
 144 0002 1868     		ldr	r0, [r3]
 179:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         >> ADC_SAR_Seq_1_intClock_DIV_INT_SHIFT);
 145              		.loc 1 179 0
 146 0004 000A     		lsr	r0, r0, #8
 178:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     return (uint16)((ADC_SAR_Seq_1_intClock_DIV_REG & ADC_SAR_Seq_1_intClock_DIV_INT_MASK)
 147              		.loc 1 178 0
 148 0006 80B2     		uxth	r0, r0
 180:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
 149              		.loc 1 180 0
 150              		@ sp needed
 151 0008 7047     		bx	lr
 152              	.L14:
 153 000a C046     		.align	2
 154              	.L13:
 155 000c 00030140 		.word	1073808128
 156              		.cfi_endproc
 157              	.LFE3:
 158              		.size	ADC_SAR_Seq_1_intClock_GetDividerRegister, .-ADC_SAR_Seq_1_intClock_GetDividerRegister
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 7


 159              		.section	.text.ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister,"ax",%progbits
 160              		.align	2
 161              		.global	ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister
 162              		.code	16
 163              		.thumb_func
 164              		.type	ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister, %function
 165              	ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister:
 166              	.LFB4:
 181:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 182:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** 
 183:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** /*******************************************************************************
 184:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Function Name: ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister
 185:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** ********************************************************************************
 186:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 187:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Summary:
 188:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Gets the clock fractional divider register value.
 189:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 190:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Parameters:
 191:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  None
 192:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 193:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** * Returns:
 194:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  Fractional Divide value of the clock
 195:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *  0 if the fractional divider is not in use.
 196:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *
 197:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** *******************************************************************************/
 198:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** uint8 ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister(void)
 199:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** {
 167              		.loc 1 199 0
 168              		.cfi_startproc
 200:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #if defined (ADC_SAR_Seq_1_intClock__FRAC_MASK)
 201:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     /* return fractional divider bits */
 202:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     return (uint8)((ADC_SAR_Seq_1_intClock_DIV_REG & ADC_SAR_Seq_1_intClock_DIV_FRAC_MASK)
 203:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****         >> ADC_SAR_Seq_1_intClock_DIV_FRAC_SHIFT);
 204:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #else
 205:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c ****     return 0u;
 206:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** #endif /* ADC_SAR_Seq_1_intClock__FRAC_MASK */
 207:Generated_Source\PSoC4/ADC_SAR_Seq_1_intClock.c **** }
 169              		.loc 1 207 0
 170 0000 0020     		mov	r0, #0
 171              		@ sp needed
 172 0002 7047     		bx	lr
 173              		.cfi_endproc
 174              	.LFE4:
 175              		.size	ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister, .-ADC_SAR_Seq_1_intClock_GetFractionalD
 176              		.text
 177              	.Letext0:
 178              		.file 2 "Generated_Source\\PSoC4/cytypes.h"
 179              		.section	.debug_info,"",%progbits
 180              	.Ldebug_info0:
 181 0000 62010000 		.4byte	0x162
 182 0004 0400     		.2byte	0x4
 183 0006 00000000 		.4byte	.Ldebug_abbrev0
 184 000a 04       		.byte	0x4
 185 000b 01       		.uleb128 0x1
 186 000c CB010000 		.4byte	.LASF25
 187 0010 01       		.byte	0x1
 188 0011 6A000000 		.4byte	.LASF26
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 8


 189 0015 9A000000 		.4byte	.LASF27
 190 0019 00000000 		.4byte	.Ldebug_ranges0+0
 191 001d 00000000 		.4byte	0
 192 0021 00000000 		.4byte	.Ldebug_line0
 193 0025 02       		.uleb128 0x2
 194 0026 01       		.byte	0x1
 195 0027 06       		.byte	0x6
 196 0028 5D020000 		.4byte	.LASF0
 197 002c 02       		.uleb128 0x2
 198 002d 01       		.byte	0x1
 199 002e 08       		.byte	0x8
 200 002f 10010000 		.4byte	.LASF1
 201 0033 02       		.uleb128 0x2
 202 0034 02       		.byte	0x2
 203 0035 05       		.byte	0x5
 204 0036 BB010000 		.4byte	.LASF2
 205 003a 02       		.uleb128 0x2
 206 003b 02       		.byte	0x2
 207 003c 07       		.byte	0x7
 208 003d 30010000 		.4byte	.LASF3
 209 0041 02       		.uleb128 0x2
 210 0042 04       		.byte	0x4
 211 0043 05       		.byte	0x5
 212 0044 42000000 		.4byte	.LASF4
 213 0048 02       		.uleb128 0x2
 214 0049 04       		.byte	0x4
 215 004a 07       		.byte	0x7
 216 004b 1E010000 		.4byte	.LASF5
 217 004f 02       		.uleb128 0x2
 218 0050 08       		.byte	0x8
 219 0051 05       		.byte	0x5
 220 0052 A8010000 		.4byte	.LASF6
 221 0056 02       		.uleb128 0x2
 222 0057 08       		.byte	0x8
 223 0058 07       		.byte	0x7
 224 0059 91010000 		.4byte	.LASF7
 225 005d 03       		.uleb128 0x3
 226 005e 04       		.byte	0x4
 227 005f 05       		.byte	0x5
 228 0060 696E7400 		.ascii	"int\000"
 229 0064 02       		.uleb128 0x2
 230 0065 04       		.byte	0x4
 231 0066 07       		.byte	0x7
 232 0067 84010000 		.4byte	.LASF8
 233 006b 04       		.uleb128 0x4
 234 006c C5010000 		.4byte	.LASF9
 235 0070 02       		.byte	0x2
 236 0071 B901     		.2byte	0x1b9
 237 0073 2C000000 		.4byte	0x2c
 238 0077 04       		.uleb128 0x4
 239 0078 76010000 		.4byte	.LASF10
 240 007c 02       		.byte	0x2
 241 007d BA01     		.2byte	0x1ba
 242 007f 3A000000 		.4byte	0x3a
 243 0083 04       		.uleb128 0x4
 244 0084 7D010000 		.4byte	.LASF11
 245 0088 02       		.byte	0x2
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 9


 246 0089 BB01     		.2byte	0x1bb
 247 008b 48000000 		.4byte	0x48
 248 008f 02       		.uleb128 0x2
 249 0090 04       		.byte	0x4
 250 0091 04       		.byte	0x4
 251 0092 C4000000 		.4byte	.LASF12
 252 0096 02       		.uleb128 0x2
 253 0097 08       		.byte	0x8
 254 0098 04       		.byte	0x4
 255 0099 4E010000 		.4byte	.LASF13
 256 009d 02       		.uleb128 0x2
 257 009e 01       		.byte	0x1
 258 009f 08       		.byte	0x8
 259 00a0 B6010000 		.4byte	.LASF14
 260 00a4 04       		.uleb128 0x4
 261 00a5 00000000 		.4byte	.LASF15
 262 00a9 02       		.byte	0x2
 263 00aa 6502     		.2byte	0x265
 264 00ac B0000000 		.4byte	0xb0
 265 00b0 05       		.uleb128 0x5
 266 00b1 83000000 		.4byte	0x83
 267 00b5 06       		.uleb128 0x6
 268 00b6 4B000000 		.4byte	.LASF16
 269 00ba 01       		.byte	0x1
 270 00bb 27       		.byte	0x27
 271 00bc 00000000 		.4byte	.LFB0
 272 00c0 1C000000 		.4byte	.LFE0-.LFB0
 273 00c4 01       		.uleb128 0x1
 274 00c5 9C       		.byte	0x9c
 275 00c6 DA000000 		.4byte	0xda
 276 00ca 07       		.uleb128 0x7
 277 00cb 5C010000 		.4byte	.LASF18
 278 00cf 01       		.byte	0x1
 279 00d0 27       		.byte	0x27
 280 00d1 83000000 		.4byte	0x83
 281 00d5 00000000 		.4byte	.LLST0
 282 00d9 00       		.byte	0
 283 00da 08       		.uleb128 0x8
 284 00db CA000000 		.4byte	.LASF28
 285 00df 01       		.byte	0x1
 286 00e0 5F       		.byte	0x5f
 287 00e1 00000000 		.4byte	.LFB1
 288 00e5 18000000 		.4byte	.LFE1-.LFB1
 289 00e9 01       		.uleb128 0x1
 290 00ea 9C       		.byte	0x9c
 291 00eb 06       		.uleb128 0x6
 292 00ec 0E000000 		.4byte	.LASF17
 293 00f0 01       		.byte	0x1
 294 00f1 86       		.byte	0x86
 295 00f2 00000000 		.4byte	.LFB2
 296 00f6 20000000 		.4byte	.LFE2-.LFB2
 297 00fa 01       		.uleb128 0x1
 298 00fb 9C       		.byte	0x9c
 299 00fc 3B010000 		.4byte	0x13b
 300 0100 07       		.uleb128 0x7
 301 0101 43010000 		.4byte	.LASF19
 302 0105 01       		.byte	0x1
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 10


 303 0106 86       		.byte	0x86
 304 0107 77000000 		.4byte	0x77
 305 010b 21000000 		.4byte	.LLST1
 306 010f 07       		.uleb128 0x7
 307 0110 68010000 		.4byte	.LASF20
 308 0114 01       		.byte	0x1
 309 0115 86       		.byte	0x86
 310 0116 6B000000 		.4byte	0x6b
 311 011a 42000000 		.4byte	.LLST2
 312 011e 09       		.uleb128 0x9
 313 011f 06000000 		.4byte	.LASF21
 314 0123 01       		.byte	0x1
 315 0124 88       		.byte	0x88
 316 0125 83000000 		.4byte	0x83
 317 0129 63000000 		.4byte	.LLST3
 318 012d 0A       		.uleb128 0xa
 319 012e 55010000 		.4byte	.LASF22
 320 0132 01       		.byte	0x1
 321 0133 89       		.byte	0x89
 322 0134 83000000 		.4byte	0x83
 323 0138 01       		.uleb128 0x1
 324 0139 51       		.byte	0x51
 325 013a 00       		.byte	0
 326 013b 0B       		.uleb128 0xb
 327 013c E6000000 		.4byte	.LASF23
 328 0140 01       		.byte	0x1
 329 0141 B0       		.byte	0xb0
 330 0142 77000000 		.4byte	0x77
 331 0146 00000000 		.4byte	.LFB3
 332 014a 10000000 		.4byte	.LFE3-.LFB3
 333 014e 01       		.uleb128 0x1
 334 014f 9C       		.byte	0x9c
 335 0150 0B       		.uleb128 0xb
 336 0151 69020000 		.4byte	.LASF24
 337 0155 01       		.byte	0x1
 338 0156 C6       		.byte	0xc6
 339 0157 6B000000 		.4byte	0x6b
 340 015b 00000000 		.4byte	.LFB4
 341 015f 04000000 		.4byte	.LFE4-.LFB4
 342 0163 01       		.uleb128 0x1
 343 0164 9C       		.byte	0x9c
 344 0165 00       		.byte	0
 345              		.section	.debug_abbrev,"",%progbits
 346              	.Ldebug_abbrev0:
 347 0000 01       		.uleb128 0x1
 348 0001 11       		.uleb128 0x11
 349 0002 01       		.byte	0x1
 350 0003 25       		.uleb128 0x25
 351 0004 0E       		.uleb128 0xe
 352 0005 13       		.uleb128 0x13
 353 0006 0B       		.uleb128 0xb
 354 0007 03       		.uleb128 0x3
 355 0008 0E       		.uleb128 0xe
 356 0009 1B       		.uleb128 0x1b
 357 000a 0E       		.uleb128 0xe
 358 000b 55       		.uleb128 0x55
 359 000c 17       		.uleb128 0x17
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 11


 360 000d 11       		.uleb128 0x11
 361 000e 01       		.uleb128 0x1
 362 000f 10       		.uleb128 0x10
 363 0010 17       		.uleb128 0x17
 364 0011 00       		.byte	0
 365 0012 00       		.byte	0
 366 0013 02       		.uleb128 0x2
 367 0014 24       		.uleb128 0x24
 368 0015 00       		.byte	0
 369 0016 0B       		.uleb128 0xb
 370 0017 0B       		.uleb128 0xb
 371 0018 3E       		.uleb128 0x3e
 372 0019 0B       		.uleb128 0xb
 373 001a 03       		.uleb128 0x3
 374 001b 0E       		.uleb128 0xe
 375 001c 00       		.byte	0
 376 001d 00       		.byte	0
 377 001e 03       		.uleb128 0x3
 378 001f 24       		.uleb128 0x24
 379 0020 00       		.byte	0
 380 0021 0B       		.uleb128 0xb
 381 0022 0B       		.uleb128 0xb
 382 0023 3E       		.uleb128 0x3e
 383 0024 0B       		.uleb128 0xb
 384 0025 03       		.uleb128 0x3
 385 0026 08       		.uleb128 0x8
 386 0027 00       		.byte	0
 387 0028 00       		.byte	0
 388 0029 04       		.uleb128 0x4
 389 002a 16       		.uleb128 0x16
 390 002b 00       		.byte	0
 391 002c 03       		.uleb128 0x3
 392 002d 0E       		.uleb128 0xe
 393 002e 3A       		.uleb128 0x3a
 394 002f 0B       		.uleb128 0xb
 395 0030 3B       		.uleb128 0x3b
 396 0031 05       		.uleb128 0x5
 397 0032 49       		.uleb128 0x49
 398 0033 13       		.uleb128 0x13
 399 0034 00       		.byte	0
 400 0035 00       		.byte	0
 401 0036 05       		.uleb128 0x5
 402 0037 35       		.uleb128 0x35
 403 0038 00       		.byte	0
 404 0039 49       		.uleb128 0x49
 405 003a 13       		.uleb128 0x13
 406 003b 00       		.byte	0
 407 003c 00       		.byte	0
 408 003d 06       		.uleb128 0x6
 409 003e 2E       		.uleb128 0x2e
 410 003f 01       		.byte	0x1
 411 0040 3F       		.uleb128 0x3f
 412 0041 19       		.uleb128 0x19
 413 0042 03       		.uleb128 0x3
 414 0043 0E       		.uleb128 0xe
 415 0044 3A       		.uleb128 0x3a
 416 0045 0B       		.uleb128 0xb
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 12


 417 0046 3B       		.uleb128 0x3b
 418 0047 0B       		.uleb128 0xb
 419 0048 27       		.uleb128 0x27
 420 0049 19       		.uleb128 0x19
 421 004a 11       		.uleb128 0x11
 422 004b 01       		.uleb128 0x1
 423 004c 12       		.uleb128 0x12
 424 004d 06       		.uleb128 0x6
 425 004e 40       		.uleb128 0x40
 426 004f 18       		.uleb128 0x18
 427 0050 9742     		.uleb128 0x2117
 428 0052 19       		.uleb128 0x19
 429 0053 01       		.uleb128 0x1
 430 0054 13       		.uleb128 0x13
 431 0055 00       		.byte	0
 432 0056 00       		.byte	0
 433 0057 07       		.uleb128 0x7
 434 0058 05       		.uleb128 0x5
 435 0059 00       		.byte	0
 436 005a 03       		.uleb128 0x3
 437 005b 0E       		.uleb128 0xe
 438 005c 3A       		.uleb128 0x3a
 439 005d 0B       		.uleb128 0xb
 440 005e 3B       		.uleb128 0x3b
 441 005f 0B       		.uleb128 0xb
 442 0060 49       		.uleb128 0x49
 443 0061 13       		.uleb128 0x13
 444 0062 02       		.uleb128 0x2
 445 0063 17       		.uleb128 0x17
 446 0064 00       		.byte	0
 447 0065 00       		.byte	0
 448 0066 08       		.uleb128 0x8
 449 0067 2E       		.uleb128 0x2e
 450 0068 00       		.byte	0
 451 0069 3F       		.uleb128 0x3f
 452 006a 19       		.uleb128 0x19
 453 006b 03       		.uleb128 0x3
 454 006c 0E       		.uleb128 0xe
 455 006d 3A       		.uleb128 0x3a
 456 006e 0B       		.uleb128 0xb
 457 006f 3B       		.uleb128 0x3b
 458 0070 0B       		.uleb128 0xb
 459 0071 27       		.uleb128 0x27
 460 0072 19       		.uleb128 0x19
 461 0073 11       		.uleb128 0x11
 462 0074 01       		.uleb128 0x1
 463 0075 12       		.uleb128 0x12
 464 0076 06       		.uleb128 0x6
 465 0077 40       		.uleb128 0x40
 466 0078 18       		.uleb128 0x18
 467 0079 9742     		.uleb128 0x2117
 468 007b 19       		.uleb128 0x19
 469 007c 00       		.byte	0
 470 007d 00       		.byte	0
 471 007e 09       		.uleb128 0x9
 472 007f 34       		.uleb128 0x34
 473 0080 00       		.byte	0
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 13


 474 0081 03       		.uleb128 0x3
 475 0082 0E       		.uleb128 0xe
 476 0083 3A       		.uleb128 0x3a
 477 0084 0B       		.uleb128 0xb
 478 0085 3B       		.uleb128 0x3b
 479 0086 0B       		.uleb128 0xb
 480 0087 49       		.uleb128 0x49
 481 0088 13       		.uleb128 0x13
 482 0089 02       		.uleb128 0x2
 483 008a 17       		.uleb128 0x17
 484 008b 00       		.byte	0
 485 008c 00       		.byte	0
 486 008d 0A       		.uleb128 0xa
 487 008e 34       		.uleb128 0x34
 488 008f 00       		.byte	0
 489 0090 03       		.uleb128 0x3
 490 0091 0E       		.uleb128 0xe
 491 0092 3A       		.uleb128 0x3a
 492 0093 0B       		.uleb128 0xb
 493 0094 3B       		.uleb128 0x3b
 494 0095 0B       		.uleb128 0xb
 495 0096 49       		.uleb128 0x49
 496 0097 13       		.uleb128 0x13
 497 0098 02       		.uleb128 0x2
 498 0099 18       		.uleb128 0x18
 499 009a 00       		.byte	0
 500 009b 00       		.byte	0
 501 009c 0B       		.uleb128 0xb
 502 009d 2E       		.uleb128 0x2e
 503 009e 00       		.byte	0
 504 009f 3F       		.uleb128 0x3f
 505 00a0 19       		.uleb128 0x19
 506 00a1 03       		.uleb128 0x3
 507 00a2 0E       		.uleb128 0xe
 508 00a3 3A       		.uleb128 0x3a
 509 00a4 0B       		.uleb128 0xb
 510 00a5 3B       		.uleb128 0x3b
 511 00a6 0B       		.uleb128 0xb
 512 00a7 27       		.uleb128 0x27
 513 00a8 19       		.uleb128 0x19
 514 00a9 49       		.uleb128 0x49
 515 00aa 13       		.uleb128 0x13
 516 00ab 11       		.uleb128 0x11
 517 00ac 01       		.uleb128 0x1
 518 00ad 12       		.uleb128 0x12
 519 00ae 06       		.uleb128 0x6
 520 00af 40       		.uleb128 0x40
 521 00b0 18       		.uleb128 0x18
 522 00b1 9742     		.uleb128 0x2117
 523 00b3 19       		.uleb128 0x19
 524 00b4 00       		.byte	0
 525 00b5 00       		.byte	0
 526 00b6 00       		.byte	0
 527              		.section	.debug_loc,"",%progbits
 528              	.Ldebug_loc0:
 529              	.LLST0:
 530 0000 00000000 		.4byte	.LVL0
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 14


 531 0004 0A000000 		.4byte	.LVL1
 532 0008 0100     		.2byte	0x1
 533 000a 50       		.byte	0x50
 534 000b 0A000000 		.4byte	.LVL1
 535 000f 1C000000 		.4byte	.LFE0
 536 0013 0400     		.2byte	0x4
 537 0015 F3       		.byte	0xf3
 538 0016 01       		.uleb128 0x1
 539 0017 50       		.byte	0x50
 540 0018 9F       		.byte	0x9f
 541 0019 00000000 		.4byte	0
 542 001d 00000000 		.4byte	0
 543              	.LLST1:
 544 0021 00000000 		.4byte	.LVL2
 545 0025 0C000000 		.4byte	.LVL4
 546 0029 0100     		.2byte	0x1
 547 002b 50       		.byte	0x50
 548 002c 0C000000 		.4byte	.LVL4
 549 0030 20000000 		.4byte	.LFE2
 550 0034 0400     		.2byte	0x4
 551 0036 F3       		.byte	0xf3
 552 0037 01       		.uleb128 0x1
 553 0038 50       		.byte	0x50
 554 0039 9F       		.byte	0x9f
 555 003a 00000000 		.4byte	0
 556 003e 00000000 		.4byte	0
 557              	.LLST2:
 558 0042 00000000 		.4byte	.LVL2
 559 0046 12000000 		.4byte	.LVL6
 560 004a 0100     		.2byte	0x1
 561 004c 51       		.byte	0x51
 562 004d 12000000 		.4byte	.LVL6
 563 0051 20000000 		.4byte	.LFE2
 564 0055 0400     		.2byte	0x4
 565 0057 F3       		.byte	0xf3
 566 0058 01       		.uleb128 0x1
 567 0059 51       		.byte	0x51
 568 005a 9F       		.byte	0x9f
 569 005b 00000000 		.4byte	0
 570 005f 00000000 		.4byte	0
 571              	.LLST3:
 572 0063 0A000000 		.4byte	.LVL3
 573 0067 10000000 		.4byte	.LVL5
 574 006b 0100     		.2byte	0x1
 575 006d 53       		.byte	0x53
 576 006e 00000000 		.4byte	0
 577 0072 00000000 		.4byte	0
 578              		.section	.debug_aranges,"",%progbits
 579 0000 3C000000 		.4byte	0x3c
 580 0004 0200     		.2byte	0x2
 581 0006 00000000 		.4byte	.Ldebug_info0
 582 000a 04       		.byte	0x4
 583 000b 00       		.byte	0
 584 000c 0000     		.2byte	0
 585 000e 0000     		.2byte	0
 586 0010 00000000 		.4byte	.LFB0
 587 0014 1C000000 		.4byte	.LFE0-.LFB0
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 15


 588 0018 00000000 		.4byte	.LFB1
 589 001c 18000000 		.4byte	.LFE1-.LFB1
 590 0020 00000000 		.4byte	.LFB2
 591 0024 20000000 		.4byte	.LFE2-.LFB2
 592 0028 00000000 		.4byte	.LFB3
 593 002c 10000000 		.4byte	.LFE3-.LFB3
 594 0030 00000000 		.4byte	.LFB4
 595 0034 04000000 		.4byte	.LFE4-.LFB4
 596 0038 00000000 		.4byte	0
 597 003c 00000000 		.4byte	0
 598              		.section	.debug_ranges,"",%progbits
 599              	.Ldebug_ranges0:
 600 0000 00000000 		.4byte	.LFB0
 601 0004 1C000000 		.4byte	.LFE0
 602 0008 00000000 		.4byte	.LFB1
 603 000c 18000000 		.4byte	.LFE1
 604 0010 00000000 		.4byte	.LFB2
 605 0014 20000000 		.4byte	.LFE2
 606 0018 00000000 		.4byte	.LFB3
 607 001c 10000000 		.4byte	.LFE3
 608 0020 00000000 		.4byte	.LFB4
 609 0024 04000000 		.4byte	.LFE4
 610 0028 00000000 		.4byte	0
 611 002c 00000000 		.4byte	0
 612              		.section	.debug_line,"",%progbits
 613              	.Ldebug_line0:
 614 0000 C7000000 		.section	.debug_str,"MS",%progbits,1
 614      02005300 
 614      00000201 
 614      FB0E0D00 
 614      01010101 
 615              	.LASF15:
 616 0000 72656733 		.ascii	"reg32\000"
 616      3200
 617              	.LASF21:
 618 0006 6D61736B 		.ascii	"maskVal\000"
 618      56616C00 
 619              	.LASF17:
 620 000e 4144435F 		.ascii	"ADC_SAR_Seq_1_intClock_SetFractionalDividerRegister"
 620      5341525F 
 620      5365715F 
 620      315F696E 
 620      74436C6F 
 621 0041 00       		.ascii	"\000"
 622              	.LASF4:
 623 0042 6C6F6E67 		.ascii	"long int\000"
 623      20696E74 
 623      00
 624              	.LASF16:
 625 004b 4144435F 		.ascii	"ADC_SAR_Seq_1_intClock_StartEx\000"
 625      5341525F 
 625      5365715F 
 625      315F696E 
 625      74436C6F 
 626              	.LASF26:
 627 006a 47656E65 		.ascii	"Generated_Source\\PSoC4\\ADC_SAR_Seq_1_intClock.c\000"
 627      72617465 
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 16


 627      645F536F 
 627      75726365 
 627      5C50536F 
 628              	.LASF27:
 629 009a 5A3A5C54 		.ascii	"Z:\\TMP\\PSoC4SProj\\CQ4S01_Sample\\I2C.cydsn\000"
 629      4D505C50 
 629      536F4334 
 629      5350726F 
 629      6A5C4351 
 630              	.LASF12:
 631 00c4 666C6F61 		.ascii	"float\000"
 631      7400
 632              	.LASF28:
 633 00ca 4144435F 		.ascii	"ADC_SAR_Seq_1_intClock_Stop\000"
 633      5341525F 
 633      5365715F 
 633      315F696E 
 633      74436C6F 
 634              	.LASF23:
 635 00e6 4144435F 		.ascii	"ADC_SAR_Seq_1_intClock_GetDividerRegister\000"
 635      5341525F 
 635      5365715F 
 635      315F696E 
 635      74436C6F 
 636              	.LASF1:
 637 0110 756E7369 		.ascii	"unsigned char\000"
 637      676E6564 
 637      20636861 
 637      7200
 638              	.LASF5:
 639 011e 6C6F6E67 		.ascii	"long unsigned int\000"
 639      20756E73 
 639      69676E65 
 639      6420696E 
 639      7400
 640              	.LASF3:
 641 0130 73686F72 		.ascii	"short unsigned int\000"
 641      7420756E 
 641      7369676E 
 641      65642069 
 641      6E7400
 642              	.LASF19:
 643 0143 636C6B44 		.ascii	"clkDivider\000"
 643      69766964 
 643      657200
 644              	.LASF13:
 645 014e 646F7562 		.ascii	"double\000"
 645      6C6500
 646              	.LASF22:
 647 0155 72656756 		.ascii	"regVal\000"
 647      616C00
 648              	.LASF18:
 649 015c 616C6967 		.ascii	"alignClkDiv\000"
 649      6E436C6B 
 649      44697600 
 650              	.LASF20:
 651 0168 636C6B46 		.ascii	"clkFractional\000"
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 17


 651      72616374 
 651      696F6E61 
 651      6C00
 652              	.LASF10:
 653 0176 75696E74 		.ascii	"uint16\000"
 653      313600
 654              	.LASF11:
 655 017d 75696E74 		.ascii	"uint32\000"
 655      333200
 656              	.LASF8:
 657 0184 756E7369 		.ascii	"unsigned int\000"
 657      676E6564 
 657      20696E74 
 657      00
 658              	.LASF7:
 659 0191 6C6F6E67 		.ascii	"long long unsigned int\000"
 659      206C6F6E 
 659      6720756E 
 659      7369676E 
 659      65642069 
 660              	.LASF6:
 661 01a8 6C6F6E67 		.ascii	"long long int\000"
 661      206C6F6E 
 661      6720696E 
 661      7400
 662              	.LASF14:
 663 01b6 63686172 		.ascii	"char\000"
 663      00
 664              	.LASF2:
 665 01bb 73686F72 		.ascii	"short int\000"
 665      7420696E 
 665      7400
 666              	.LASF9:
 667 01c5 75696E74 		.ascii	"uint8\000"
 667      3800
 668              	.LASF25:
 669 01cb 474E5520 		.ascii	"GNU C 4.9.3 20150303 (release) [ARM/embedded-4_9-br"
 669      4320342E 
 669      392E3320 
 669      32303135 
 669      30333033 
 670 01fe 616E6368 		.ascii	"anch revision 221220] -mcpu=cortex-m0plus -mthumb -"
 670      20726576 
 670      6973696F 
 670      6E203232 
 670      31323230 
 671 0231 67202D4F 		.ascii	"g -Og -ffunction-sections -ffat-lto-objects\000"
 671      67202D66 
 671      66756E63 
 671      74696F6E 
 671      2D736563 
 672              	.LASF0:
 673 025d 7369676E 		.ascii	"signed char\000"
 673      65642063 
 673      68617200 
 674              	.LASF24:
 675 0269 4144435F 		.ascii	"ADC_SAR_Seq_1_intClock_GetFractionalDividerRegister"
ARM GAS  C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\ccGs05WS.s 			page 18


 675      5341525F 
 675      5365715F 
 675      315F696E 
 675      74436C6F 
 676 029c 00       		.ascii	"\000"
 677              		.ident	"GCC: (GNU Tools for ARM Embedded Processors) 4.9.3 20150303 (release) [ARM/embedded-4_9-br
