Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	101	9,312	1%
Number of 4 input LUTs	121	9,312	1%
Logic Distribution
Number of occupied Slices	114	4,656	2%
Number of Slices containing only related logic	114	114	100%
Number of Slices containing unrelated logic	0	114	0%
Total Number 4 input LUTs	201	9,312	2%
Number used as logic	121
Number used as a route-thru	2
Number used for Dual Port RAMs	16
Number used for 32x1 RAMs	52
Number used as Shift registers	10
Number of bonded IOBs	30	232	12%
IOB Flip Flops	15
Number of Block RAMs	1	20	5%
Number of GCLKs	2	24	8%
Number of BSCANs	1	1	100%
Total equivalent gate count for design	75,933
Additional JTAG gate count for IOBs	1,440

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met