Static Timing Analysis

Project : 1halfadder
Build Time : 04/12/12 23:04:07
Device : CY8C3866LTI-030
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
A(0)/fb Second_Digit(0)_PAD 36.836
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 A(0) A(0)/clock A(0)/fb 6.160
Route 1 Net_1 A(0)/fb Net_3/main_1 5.577
macrocell2 U(3,4) 1 Net_3 Net_3/main_1 Net_3/q 3.350
Route 1 Net_3 Net_3/q Second_Digit(0)/pin_input 5.549
iocell P0[3] 1 Second_Digit(0) Second_Digit(0)/pin_input Second_Digit(0)/pad_out 16.200
Route 1 Second_Digit(0)_PAD Second_Digit(0)/pad_out Second_Digit(0)_PAD 0.000
Clock Clock path delay 0.000
A(0)/fb First_Digit(0)_PAD 36.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 A(0) A(0)/clock A(0)/fb 6.160
Route 1 Net_1 A(0)/fb Net_16/main_1 5.577
macrocell1 U(3,4) 1 Net_16 Net_16/main_1 Net_16/q 3.350
Route 1 Net_16 Net_16/q First_Digit(0)/pin_input 5.470
iocell P0[2] 1 First_Digit(0) First_Digit(0)/pin_input First_Digit(0)/pad_out 16.200
Route 1 First_Digit(0)_PAD First_Digit(0)/pad_out First_Digit(0)_PAD 0.000
Clock Clock path delay 0.000