Static Timing Analysis

Project : FlipFLop
Build Time : 04/12/12 23:06:18
Device : CY8C3866LTI-030
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
FF_R(0)/fb FF_QB(0)_PAD 43.896
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[1] 1 FF_R(0) FF_R(0)/clock FF_R(0)/fb 6.160
Route 1 Net_24 FF_R(0)/fb Net_9/main_2 5.601
macrocell2 U(3,4) 1 Net_9 Net_9/main_2 Net_9/q 3.350
Route 1 Net_9 Net_9/q Net_10/main_0 3.765
macrocell1 U(3,4) 1 Net_10 Net_10/main_0 Net_10/q 3.350
Route 1 Net_10 Net_10/q FF_QB(0)/pin_input 5.470
iocell P0[3] 1 FF_QB(0) FF_QB(0)/pin_input FF_QB(0)/pad_out 16.200
Route 1 FF_QB(0)_PAD FF_QB(0)/pad_out FF_QB(0)_PAD 0.000
Clock Clock path delay 0.000
FF_R(0)/fb FF_Q(0)_PAD 37.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[1] 1 FF_R(0) FF_R(0)/clock FF_R(0)/fb 6.160
Route 1 Net_24 FF_R(0)/fb Net_9/main_2 5.601
macrocell2 U(3,4) 1 Net_9 Net_9/main_2 Net_9/q 3.350
Route 1 Net_9 Net_9/q FF_Q(0)/pin_input 6.611
iocell P0[2] 1 FF_Q(0) FF_Q(0)/pin_input FF_Q(0)/pad_out 16.200
Route 1 FF_Q(0)_PAD FF_Q(0)/pad_out FF_Q(0)_PAD 0.000
Clock Clock path delay 0.000