Static Timing Analysis

Project : AND_OR
Build Time : 04/12/12 23:05:15
Device : CY8C3866LTI-030
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
OR_B(0)/fb OR_Q(0)_PAD 39.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P2[1] 1 OR_B(0) OR_B(0)/clock OR_B(0)/fb 6.160
Route 1 Net_14 OR_B(0)/fb Net_6/main_0 6.853
macrocell2 U(3,4) 1 Net_6 Net_6/main_0 Net_6/q 3.350
Route 1 Net_6 Net_6/q OR_Q(0)/pin_input 7.063
iocell P2[2] 1 OR_Q(0) OR_Q(0)/pin_input OR_Q(0)/pad_out 16.200
Route 1 OR_Q(0)_PAD OR_Q(0)/pad_out OR_Q(0)_PAD 0.000
Clock Clock path delay 0.000
AND_B(0)/fb AND_Q(0)_PAD 36.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[1] 1 AND_B(0) AND_B(0)/clock AND_B(0)/fb 6.160
Route 1 Net_19 AND_B(0)/fb Net_3/main_0 5.738
macrocell1 U(3,4) 1 Net_3 Net_3/main_0 Net_3/q 3.350
Route 1 Net_3 Net_3/q AND_Q(0)/pin_input 5.445
iocell P0[2] 1 AND_Q(0) AND_Q(0)/pin_input AND_Q(0)/pad_out 16.200
Route 1 AND_Q(0)_PAD AND_Q(0)/pad_out AND_Q(0)_PAD 0.000
Clock Clock path delay 0.000